mirror of https://gitee.com/openkylin/linux.git
110 lines
3.1 KiB
C
110 lines
3.1 KiB
C
/* MN10300 SMP support
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* Modified by Matsushita Electric Industrial Co., Ltd.
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* Modifications:
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* 13-Nov-2006 MEI Define IPI-IRQ number and add inline/macro function
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* for SMP support.
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* 22-Jan-2007 MEI Add the define related to SMP_BOOT_IRQ.
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* 23-Feb-2007 MEI Add the define related to SMP icahce invalidate.
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* 23-Jun-2008 MEI Delete INTC_IPI.
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* 22-Jul-2008 MEI Add smp_nmi_call_function and related defines.
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* 04-Aug-2008 MEI Delete USE_DOIRQ_CACHE_IPI.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_SMP_H
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#define _ASM_SMP_H
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#ifndef __ASSEMBLY__
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#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/thread_info.h>
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#endif
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#ifdef CONFIG_SMP
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#include <proc/smp-regs.h>
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#define RESCHEDULE_IPI 63
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#define CALL_FUNC_SINGLE_IPI 192
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#define LOCAL_TIMER_IPI 193
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#define FLUSH_CACHE_IPI 194
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#define CALL_FUNCTION_NMI_IPI 195
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#define DEBUGGER_NMI_IPI 196
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#define SMP_BOOT_IRQ 195
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#define RESCHEDULE_GxICR_LV GxICR_LEVEL_6
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#define CALL_FUNCTION_GxICR_LV GxICR_LEVEL_4
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#define LOCAL_TIMER_GxICR_LV GxICR_LEVEL_4
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#define FLUSH_CACHE_GxICR_LV GxICR_LEVEL_0
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#define SMP_BOOT_GxICR_LV GxICR_LEVEL_0
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#define DEBUGGER_GxICR_LV CONFIG_DEBUGGER_IRQ_LEVEL
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#define TIME_OUT_COUNT_BOOT_IPI 100
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#define DELAY_TIME_BOOT_IPI 75000
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#ifndef __ASSEMBLY__
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/**
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* raw_smp_processor_id - Determine the raw CPU ID of the CPU running it
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*
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* What we really want to do is to use the CPUID hardware CPU register to get
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* this information, but accesses to that aren't cached, and run at system bus
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* speed, not CPU speed. A copy of this value is, however, stored in the
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* thread_info struct, and that can be cached.
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*
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* An alternate way of dealing with this could be to use the EPSW.S bits to
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* cache this information for systems with up to four CPUs.
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*/
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#define arch_smp_processor_id() (CPUID)
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#if 0
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#define raw_smp_processor_id() (arch_smp_processor_id())
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#else
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#define raw_smp_processor_id() (current_thread_info()->cpu)
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#endif
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static inline int cpu_logical_map(int cpu)
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{
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return cpu;
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}
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static inline int cpu_number_map(int cpu)
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{
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return cpu;
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}
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extern cpumask_t cpu_boot_map;
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extern void smp_init_cpus(void);
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extern void smp_cache_interrupt(void);
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extern void send_IPI_allbutself(int irq);
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extern int smp_nmi_call_function(void (*func)(void *), void *info, int wait);
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extern void arch_send_call_function_single_ipi(int cpu);
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extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
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#ifdef CONFIG_HOTPLUG_CPU
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extern int __cpu_disable(void);
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extern void __cpu_die(unsigned int cpu);
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#endif /* CONFIG_HOTPLUG_CPU */
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#endif /* __ASSEMBLY__ */
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#else /* CONFIG_SMP */
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#ifndef __ASSEMBLY__
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static inline void smp_init_cpus(void) {}
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#define raw_smp_processor_id() 0
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_SMP */
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#endif /* _ASM_SMP_H */
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