mirror of https://gitee.com/openkylin/linux.git
157 lines
5.5 KiB
C
157 lines
5.5 KiB
C
/*
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* Copyright (C) 2003-2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#ifndef MSI_H
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#define MSI_H
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/*
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* MSI operation vector. Used by the msi core code (drivers/pci/msi.c)
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* to abstract platform-specific tasks relating to MSI address generation
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* and resource management.
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*/
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struct msi_ops {
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/**
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* setup - generate an MSI bus address and data for a given vector
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* @pdev: PCI device context (in)
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* @vector: vector allocated by the msi core (in)
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* @addr_hi: upper 32 bits of PCI bus MSI address (out)
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* @addr_lo: lower 32 bits of PCI bus MSI address (out)
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* @data: MSI data payload (out)
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*
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* Description: The setup op is used to generate a PCI bus addres and
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* data which the msi core will program into the card MSI capability
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* registers. The setup routine is responsible for picking an initial
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* cpu to target the MSI at. The setup routine is responsible for
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* examining pdev to determine the MSI capabilities of the card and
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* generating a suitable address/data. The setup routine is
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* responsible for allocating and tracking any system resources it
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* needs to route the MSI to the cpu it picks, and for associating
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* those resources with the passed in vector.
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*
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* Returns 0 if the MSI address/data was successfully setup.
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**/
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int (*setup) (struct pci_dev *pdev, unsigned int vector,
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u32 *addr_hi, u32 *addr_lo, u32 *data);
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/**
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* teardown - release resources allocated by setup
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* @vector: vector context for resources (in)
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*
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* Description: The teardown op is used to release any resources
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* that were allocated in the setup routine associated with the passed
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* in vector.
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**/
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void (*teardown) (unsigned int vector);
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/**
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* target - retarget an MSI at a different cpu
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* @vector: vector context for resources (in)
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* @cpu: new cpu to direct vector at (in)
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* @addr_hi: new value of PCI bus upper 32 bits (in/out)
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* @addr_lo: new value of PCI bus lower 32 bits (in/out)
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*
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* Description: The target op is used to redirect an MSI vector
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* at a different cpu. addr_hi/addr_lo coming in are the existing
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* values that the MSI core has programmed into the card. The
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* target code is responsible for freeing any resources (if any)
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* associated with the old address, and generating a new PCI bus
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* addr_hi/addr_lo that will redirect the vector at the indicated cpu.
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**/
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void (*target) (unsigned int vector, unsigned int cpu,
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u32 *addr_hi, u32 *addr_lo);
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};
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extern int msi_register(struct msi_ops *ops);
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#include <asm/msi.h>
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/*
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* Assume the maximum number of hot plug slots supported by the system is about
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* ten. The worstcase is that each of these slots is hot-added with a device,
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* which has two MSI/MSI-X capable functions. To avoid any MSI-X driver, which
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* attempts to request all available vectors, NR_HP_RESERVED_VECTORS is defined
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* as below to ensure at least one message is assigned to each detected MSI/
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* MSI-X device function.
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*/
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#define NR_HP_RESERVED_VECTORS 20
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extern int vector_irq[NR_VECTORS];
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extern void (*interrupt[NR_IRQS])(void);
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extern int pci_vector_resources(int last, int nr_released);
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/*
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* MSI-X Address Register
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*/
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#define PCI_MSIX_FLAGS_QSIZE 0x7FF
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#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
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#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
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#define PCI_MSIX_FLAGS_BITMASK (1 << 0)
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#define PCI_MSIX_ENTRY_SIZE 16
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#define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0
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#define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4
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#define PCI_MSIX_ENTRY_DATA_OFFSET 8
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#define PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET 12
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#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
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#define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
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#define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
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#define msi_data_reg(base, is64bit) \
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( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 )
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#define msi_mask_bits_reg(base, is64bit) \
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( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4)
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#define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE
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#define multi_msi_capable(control) \
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(1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1))
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#define multi_msi_enable(control, num) \
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control |= (((num >> 1) << 4) & PCI_MSI_FLAGS_QSIZE);
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#define is_64bit_address(control) (control & PCI_MSI_FLAGS_64BIT)
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#define is_mask_bit_support(control) (control & PCI_MSI_FLAGS_MASKBIT)
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#define msi_enable(control, num) multi_msi_enable(control, num); \
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control |= PCI_MSI_FLAGS_ENABLE
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#define msix_table_offset_reg(base) (base + 0x04)
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#define msix_pba_offset_reg(base) (base + 0x08)
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#define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE
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#define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE
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#define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
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#define multi_msix_capable msix_table_size
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#define msix_unmask(address) (address & ~PCI_MSIX_FLAGS_BITMASK)
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#define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK)
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#define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK)
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struct msi_desc {
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struct {
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__u8 type : 5; /* {0: unused, 5h:MSI, 11h:MSI-X} */
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__u8 maskbit : 1; /* mask-pending bit supported ? */
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__u8 state : 1; /* {0: free, 1: busy} */
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__u8 reserved: 1; /* reserved */
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__u8 entry_nr; /* specific enabled entry */
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__u8 default_vector; /* default pre-assigned vector */
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__u8 unused; /* formerly unused destination cpu*/
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}msi_attrib;
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struct {
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__u16 head;
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__u16 tail;
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}link;
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void __iomem *mask_base;
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struct pci_dev *dev;
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#ifdef CONFIG_PM
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/* PM save area for MSIX address/data */
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u32 address_hi_save;
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u32 address_lo_save;
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u32 data_save;
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#endif
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};
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#endif /* MSI_H */
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