mirror of https://gitee.com/openkylin/linux.git
275 lines
6.3 KiB
C
275 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* X1000 SoC CGU driver
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* Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <dt-bindings/clock/x1000-cgu.h>
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#include "cgu.h"
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#include "pm.h"
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/* CGU register offsets */
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#define CGU_REG_CPCCR 0x00
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#define CGU_REG_APLL 0x10
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#define CGU_REG_MPLL 0x14
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#define CGU_REG_CLKGR 0x20
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#define CGU_REG_OPCR 0x24
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#define CGU_REG_DDRCDR 0x2c
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#define CGU_REG_MACCDR 0x54
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#define CGU_REG_I2SCDR 0x60
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#define CGU_REG_LPCDR 0x64
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#define CGU_REG_MSC0CDR 0x68
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#define CGU_REG_I2SCDR1 0x70
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#define CGU_REG_SSICDR 0x74
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#define CGU_REG_CIMCDR 0x7c
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#define CGU_REG_PCMCDR 0x84
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#define CGU_REG_MSC1CDR 0xa4
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#define CGU_REG_CMP_INTR 0xb0
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#define CGU_REG_CMP_INTRE 0xb4
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#define CGU_REG_DRCG 0xd0
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#define CGU_REG_CPCSR 0xd4
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#define CGU_REG_PCMCDR1 0xe0
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#define CGU_REG_MACPHYC 0xe8
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/* bits within the OPCR register */
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#define OPCR_SPENDN0 BIT(7)
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#define OPCR_SPENDN1 BIT(6)
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static struct ingenic_cgu *cgu;
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static const s8 pll_od_encoding[8] = {
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0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
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};
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static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
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/* External clocks */
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[X1000_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
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[X1000_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
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/* PLLs */
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[X1000_CLK_APLL] = {
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"apll", CGU_CLK_PLL,
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.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
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.pll = {
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.reg = CGU_REG_APLL,
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.m_shift = 24,
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.m_bits = 7,
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.m_offset = 1,
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.n_shift = 18,
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.n_bits = 5,
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.n_offset = 1,
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.od_shift = 16,
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.od_bits = 2,
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.od_max = 8,
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.od_encoding = pll_od_encoding,
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.bypass_bit = 9,
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.enable_bit = 8,
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.stable_bit = 10,
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},
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},
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[X1000_CLK_MPLL] = {
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"mpll", CGU_CLK_PLL,
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.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
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.pll = {
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.reg = CGU_REG_MPLL,
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.m_shift = 24,
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.m_bits = 7,
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.m_offset = 1,
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.n_shift = 18,
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.n_bits = 5,
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.n_offset = 1,
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.od_shift = 16,
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.od_bits = 2,
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.od_max = 8,
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.od_encoding = pll_od_encoding,
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.bypass_bit = 6,
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.enable_bit = 7,
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.stable_bit = 0,
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},
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},
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/* Muxes & dividers */
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[X1000_CLK_SCLKA] = {
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"sclk_a", CGU_CLK_MUX,
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.parents = { -1, X1000_CLK_EXCLK, X1000_CLK_APLL, -1 },
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.mux = { CGU_REG_CPCCR, 30, 2 },
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},
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[X1000_CLK_CPUMUX] = {
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"cpu_mux", CGU_CLK_MUX,
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.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
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.mux = { CGU_REG_CPCCR, 28, 2 },
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},
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[X1000_CLK_CPU] = {
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"cpu", CGU_CLK_DIV,
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.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
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},
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[X1000_CLK_L2CACHE] = {
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"l2cache", CGU_CLK_DIV,
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.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
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},
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[X1000_CLK_AHB0] = {
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"ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
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.mux = { CGU_REG_CPCCR, 26, 2 },
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.div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
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},
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[X1000_CLK_AHB2PMUX] = {
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"ahb2_apb_mux", CGU_CLK_MUX,
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.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
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.mux = { CGU_REG_CPCCR, 24, 2 },
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},
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[X1000_CLK_AHB2] = {
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"ahb2", CGU_CLK_DIV,
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.parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
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},
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[X1000_CLK_PCLK] = {
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"pclk", CGU_CLK_DIV,
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.parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
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},
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[X1000_CLK_DDR] = {
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"ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { -1, X1000_CLK_SCLKA, X1000_CLK_MPLL, -1 },
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.mux = { CGU_REG_DDRCDR, 30, 2 },
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.div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
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.gate = { CGU_REG_CLKGR, 31 },
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},
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[X1000_CLK_MAC] = {
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"mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
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.mux = { CGU_REG_MACCDR, 31, 1 },
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.div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
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.gate = { CGU_REG_CLKGR, 25 },
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},
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[X1000_CLK_MSCMUX] = {
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"msc_mux", CGU_CLK_MUX,
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.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
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.mux = { CGU_REG_MSC0CDR, 31, 1 },
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},
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[X1000_CLK_MSC0] = {
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"msc0", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
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.div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
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.gate = { CGU_REG_CLKGR, 4 },
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},
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[X1000_CLK_MSC1] = {
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"msc1", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { X1000_CLK_MSCMUX, -1, -1, -1 },
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.div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
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.gate = { CGU_REG_CLKGR, 5 },
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},
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[X1000_CLK_SSIPLL] = {
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"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 },
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.mux = { CGU_REG_SSICDR, 31, 1 },
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.div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
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},
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[X1000_CLK_SSIMUX] = {
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"ssi_mux", CGU_CLK_MUX,
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.parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL, -1, -1 },
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.mux = { CGU_REG_SSICDR, 30, 1 },
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},
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/* Gate-only clocks */
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[X1000_CLK_SFC] = {
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"sfc", CGU_CLK_GATE,
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.parents = { X1000_CLK_SSIPLL, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 2 },
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},
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[X1000_CLK_I2C0] = {
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"i2c0", CGU_CLK_GATE,
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.parents = { X1000_CLK_PCLK, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 7 },
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},
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[X1000_CLK_I2C1] = {
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"i2c1", CGU_CLK_GATE,
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.parents = { X1000_CLK_PCLK, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 8 },
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},
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[X1000_CLK_I2C2] = {
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"i2c2", CGU_CLK_GATE,
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.parents = { X1000_CLK_PCLK, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 9 },
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},
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[X1000_CLK_UART0] = {
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"uart0", CGU_CLK_GATE,
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.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 14 },
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},
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[X1000_CLK_UART1] = {
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"uart1", CGU_CLK_GATE,
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.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 15 },
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},
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[X1000_CLK_UART2] = {
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"uart2", CGU_CLK_GATE,
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.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 16 },
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},
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[X1000_CLK_SSI] = {
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"ssi", CGU_CLK_GATE,
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.parents = { X1000_CLK_SSIMUX, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 19 },
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},
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[X1000_CLK_PDMA] = {
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"pdma", CGU_CLK_GATE,
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.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 21 },
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},
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};
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static void __init x1000_cgu_init(struct device_node *np)
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{
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int retval;
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cgu = ingenic_cgu_new(x1000_cgu_clocks,
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ARRAY_SIZE(x1000_cgu_clocks), np);
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if (!cgu) {
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pr_err("%s: failed to initialise CGU\n", __func__);
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return;
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}
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retval = ingenic_cgu_register_clocks(cgu);
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if (retval) {
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pr_err("%s: failed to register CGU Clocks\n", __func__);
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return;
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}
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ingenic_cgu_register_syscore_ops(cgu);
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}
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CLK_OF_DECLARE(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
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