mirror of https://gitee.com/openkylin/linux.git
775 lines
20 KiB
C
775 lines
20 KiB
C
/*
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* Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __IW_CXGB4_H__
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#define __IW_CXGB4_H__
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#include <linux/mutex.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/idr.h>
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#include <linux/workqueue.h>
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#include <linux/netdevice.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/inet.h>
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#include <linux/wait.h>
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#include <linux/kref.h>
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#include <linux/timer.h>
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#include <linux/io.h>
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#include <linux/kfifo.h>
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#include <asm/byteorder.h>
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#include <net/net_namespace.h>
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#include <rdma/ib_verbs.h>
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#include <rdma/iw_cm.h>
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#include "cxgb4.h"
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#include "cxgb4_uld.h"
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#include "l2t.h"
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#include "user.h"
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#define DRV_NAME "iw_cxgb4"
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#define MOD DRV_NAME ":"
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extern int c4iw_debug;
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#define PDBG(fmt, args...) \
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do { \
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if (c4iw_debug) \
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printk(MOD fmt, ## args); \
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} while (0)
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#include "t4.h"
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#define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
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#define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
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static inline void *cplhdr(struct sk_buff *skb)
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{
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return skb->data;
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}
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struct c4iw_resource {
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struct kfifo tpt_fifo;
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spinlock_t tpt_fifo_lock;
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struct kfifo qid_fifo;
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spinlock_t qid_fifo_lock;
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struct kfifo pdid_fifo;
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spinlock_t pdid_fifo_lock;
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};
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struct c4iw_qid_list {
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struct list_head entry;
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u32 qid;
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};
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struct c4iw_dev_ucontext {
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struct list_head qpids;
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struct list_head cqids;
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struct mutex lock;
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};
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enum c4iw_rdev_flags {
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T4_FATAL_ERROR = (1<<0),
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};
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struct c4iw_rdev {
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struct c4iw_resource resource;
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unsigned long qpshift;
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u32 qpmask;
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unsigned long cqshift;
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u32 cqmask;
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struct c4iw_dev_ucontext uctx;
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struct gen_pool *pbl_pool;
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struct gen_pool *rqt_pool;
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struct gen_pool *ocqp_pool;
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u32 flags;
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struct cxgb4_lld_info lldi;
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unsigned long oc_mw_pa;
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void __iomem *oc_mw_kva;
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};
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static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
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{
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return rdev->flags & T4_FATAL_ERROR;
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}
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static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
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{
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return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5));
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}
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#define C4IW_WR_TO (10*HZ)
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struct c4iw_wr_wait {
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wait_queue_head_t wait;
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int done;
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int ret;
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};
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static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
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{
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wr_waitp->ret = 0;
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wr_waitp->done = 0;
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init_waitqueue_head(&wr_waitp->wait);
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}
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static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
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struct c4iw_wr_wait *wr_waitp,
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u32 hwtid, u32 qpid,
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const char *func)
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{
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unsigned to = C4IW_WR_TO;
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do {
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wait_event_timeout(wr_waitp->wait, wr_waitp->done, to);
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if (!wr_waitp->done) {
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printk(KERN_ERR MOD "%s - Device %s not responding - "
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"tid %u qpid %u\n", func,
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pci_name(rdev->lldi.pdev), hwtid, qpid);
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to = to << 2;
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}
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} while (!wr_waitp->done);
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if (wr_waitp->ret)
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printk(KERN_WARNING MOD "%s: FW reply %d tid %u qpid %u\n",
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pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
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return wr_waitp->ret;
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}
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struct c4iw_dev {
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struct ib_device ibdev;
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struct c4iw_rdev rdev;
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u32 device_cap_flags;
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struct idr cqidr;
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struct idr qpidr;
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struct idr mmidr;
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spinlock_t lock;
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struct list_head entry;
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struct dentry *debugfs_root;
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u8 registered;
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};
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static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
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{
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return container_of(ibdev, struct c4iw_dev, ibdev);
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}
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static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
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{
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return container_of(rdev, struct c4iw_dev, rdev);
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}
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static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
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{
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return idr_find(&rhp->cqidr, cqid);
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}
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static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
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{
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return idr_find(&rhp->qpidr, qpid);
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}
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static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
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{
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return idr_find(&rhp->mmidr, mmid);
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}
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static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
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void *handle, u32 id)
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{
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int ret;
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int newid;
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do {
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if (!idr_pre_get(idr, GFP_KERNEL))
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return -ENOMEM;
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spin_lock_irq(&rhp->lock);
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ret = idr_get_new_above(idr, handle, id, &newid);
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BUG_ON(newid != id);
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spin_unlock_irq(&rhp->lock);
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} while (ret == -EAGAIN);
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return ret;
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}
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static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
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{
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spin_lock_irq(&rhp->lock);
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idr_remove(idr, id);
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spin_unlock_irq(&rhp->lock);
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}
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struct c4iw_pd {
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struct ib_pd ibpd;
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u32 pdid;
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struct c4iw_dev *rhp;
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};
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static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
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{
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return container_of(ibpd, struct c4iw_pd, ibpd);
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}
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struct tpt_attributes {
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u64 len;
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u64 va_fbo;
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enum fw_ri_mem_perms perms;
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u32 stag;
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u32 pdid;
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u32 qpid;
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u32 pbl_addr;
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u32 pbl_size;
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u32 state:1;
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u32 type:2;
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u32 rsvd:1;
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u32 remote_invaliate_disable:1;
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u32 zbva:1;
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u32 mw_bind_enable:1;
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u32 page_size:5;
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};
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struct c4iw_mr {
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struct ib_mr ibmr;
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struct ib_umem *umem;
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struct c4iw_dev *rhp;
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u64 kva;
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struct tpt_attributes attr;
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};
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static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
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{
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return container_of(ibmr, struct c4iw_mr, ibmr);
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}
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struct c4iw_mw {
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struct ib_mw ibmw;
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struct c4iw_dev *rhp;
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u64 kva;
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struct tpt_attributes attr;
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};
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static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
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{
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return container_of(ibmw, struct c4iw_mw, ibmw);
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}
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struct c4iw_fr_page_list {
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struct ib_fast_reg_page_list ibpl;
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DEFINE_DMA_UNMAP_ADDR(mapping);
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dma_addr_t dma_addr;
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struct c4iw_dev *dev;
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int size;
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};
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static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
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struct ib_fast_reg_page_list *ibpl)
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{
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return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
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}
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struct c4iw_cq {
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struct ib_cq ibcq;
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struct c4iw_dev *rhp;
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struct t4_cq cq;
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spinlock_t lock;
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atomic_t refcnt;
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wait_queue_head_t wait;
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};
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static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
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{
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return container_of(ibcq, struct c4iw_cq, ibcq);
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}
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struct c4iw_mpa_attributes {
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u8 initiator;
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u8 recv_marker_enabled;
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u8 xmit_marker_enabled;
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u8 crc_enabled;
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u8 version;
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u8 p2p_type;
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};
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struct c4iw_qp_attributes {
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u32 scq;
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u32 rcq;
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u32 sq_num_entries;
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u32 rq_num_entries;
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u32 sq_max_sges;
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u32 sq_max_sges_rdma_write;
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u32 rq_max_sges;
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u32 state;
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u8 enable_rdma_read;
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u8 enable_rdma_write;
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u8 enable_bind;
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u8 enable_mmid0_fastreg;
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u32 max_ord;
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u32 max_ird;
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u32 pd;
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u32 next_state;
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char terminate_buffer[52];
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u32 terminate_msg_len;
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u8 is_terminate_local;
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struct c4iw_mpa_attributes mpa_attr;
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struct c4iw_ep *llp_stream_handle;
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};
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struct c4iw_qp {
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struct ib_qp ibqp;
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struct c4iw_dev *rhp;
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struct c4iw_ep *ep;
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struct c4iw_qp_attributes attr;
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struct t4_wq wq;
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spinlock_t lock;
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struct mutex mutex;
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atomic_t refcnt;
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wait_queue_head_t wait;
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struct timer_list timer;
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};
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static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
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{
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return container_of(ibqp, struct c4iw_qp, ibqp);
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}
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struct c4iw_ucontext {
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struct ib_ucontext ibucontext;
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struct c4iw_dev_ucontext uctx;
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u32 key;
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spinlock_t mmap_lock;
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struct list_head mmaps;
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};
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static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
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{
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return container_of(c, struct c4iw_ucontext, ibucontext);
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}
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struct c4iw_mm_entry {
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struct list_head entry;
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u64 addr;
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u32 key;
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unsigned len;
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};
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static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
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u32 key, unsigned len)
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{
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struct list_head *pos, *nxt;
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struct c4iw_mm_entry *mm;
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spin_lock(&ucontext->mmap_lock);
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list_for_each_safe(pos, nxt, &ucontext->mmaps) {
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mm = list_entry(pos, struct c4iw_mm_entry, entry);
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if (mm->key == key && mm->len == len) {
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list_del_init(&mm->entry);
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spin_unlock(&ucontext->mmap_lock);
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PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
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key, (unsigned long long) mm->addr, mm->len);
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return mm;
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}
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}
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spin_unlock(&ucontext->mmap_lock);
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return NULL;
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}
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static inline void insert_mmap(struct c4iw_ucontext *ucontext,
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struct c4iw_mm_entry *mm)
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{
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spin_lock(&ucontext->mmap_lock);
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PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
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mm->key, (unsigned long long) mm->addr, mm->len);
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list_add_tail(&mm->entry, &ucontext->mmaps);
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spin_unlock(&ucontext->mmap_lock);
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}
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enum c4iw_qp_attr_mask {
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C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
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C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
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C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
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C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
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C4IW_QP_ATTR_MAX_ORD = 1 << 11,
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C4IW_QP_ATTR_MAX_IRD = 1 << 12,
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C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
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C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
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C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
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C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
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C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
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C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
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C4IW_QP_ATTR_MAX_ORD |
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C4IW_QP_ATTR_MAX_IRD |
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C4IW_QP_ATTR_LLP_STREAM_HANDLE |
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C4IW_QP_ATTR_STREAM_MSG_BUFFER |
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C4IW_QP_ATTR_MPA_ATTR |
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C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
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};
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int c4iw_modify_qp(struct c4iw_dev *rhp,
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struct c4iw_qp *qhp,
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enum c4iw_qp_attr_mask mask,
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struct c4iw_qp_attributes *attrs,
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int internal);
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enum c4iw_qp_state {
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C4IW_QP_STATE_IDLE,
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C4IW_QP_STATE_RTS,
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C4IW_QP_STATE_ERROR,
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C4IW_QP_STATE_TERMINATE,
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C4IW_QP_STATE_CLOSING,
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C4IW_QP_STATE_TOT
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};
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static inline int c4iw_convert_state(enum ib_qp_state ib_state)
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{
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switch (ib_state) {
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case IB_QPS_RESET:
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case IB_QPS_INIT:
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return C4IW_QP_STATE_IDLE;
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case IB_QPS_RTS:
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return C4IW_QP_STATE_RTS;
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case IB_QPS_SQD:
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return C4IW_QP_STATE_CLOSING;
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case IB_QPS_SQE:
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return C4IW_QP_STATE_TERMINATE;
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case IB_QPS_ERR:
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return C4IW_QP_STATE_ERROR;
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default:
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return -1;
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}
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}
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static inline u32 c4iw_ib_to_tpt_access(int a)
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{
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return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
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(a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
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(a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
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FW_RI_MEM_ACCESS_LOCAL_READ;
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}
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static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
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{
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return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
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(acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
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}
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enum c4iw_mmid_state {
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C4IW_STAG_STATE_VALID,
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C4IW_STAG_STATE_INVALID
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};
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#define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
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#define MPA_KEY_REQ "MPA ID Req Frame"
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#define MPA_KEY_REP "MPA ID Rep Frame"
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#define MPA_MAX_PRIVATE_DATA 256
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#define MPA_REJECT 0x20
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#define MPA_CRC 0x40
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#define MPA_MARKERS 0x80
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#define MPA_FLAGS_MASK 0xE0
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#define c4iw_put_ep(ep) { \
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PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \
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ep, atomic_read(&((ep)->kref.refcount))); \
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WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
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kref_put(&((ep)->kref), _c4iw_free_ep); \
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}
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#define c4iw_get_ep(ep) { \
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PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
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ep, atomic_read(&((ep)->kref.refcount))); \
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kref_get(&((ep)->kref)); \
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}
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void _c4iw_free_ep(struct kref *kref);
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struct mpa_message {
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u8 key[16];
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u8 flags;
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u8 revision;
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__be16 private_data_size;
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u8 private_data[0];
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};
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struct terminate_message {
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u8 layer_etype;
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u8 ecode;
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__be16 hdrct_rsvd;
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u8 len_hdrs[0];
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};
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#define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
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|
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enum c4iw_layers_types {
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LAYER_RDMAP = 0x00,
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LAYER_DDP = 0x10,
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LAYER_MPA = 0x20,
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RDMAP_LOCAL_CATA = 0x00,
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RDMAP_REMOTE_PROT = 0x01,
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RDMAP_REMOTE_OP = 0x02,
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DDP_LOCAL_CATA = 0x00,
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DDP_TAGGED_ERR = 0x01,
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DDP_UNTAGGED_ERR = 0x02,
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DDP_LLP = 0x03
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};
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enum c4iw_rdma_ecodes {
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RDMAP_INV_STAG = 0x00,
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RDMAP_BASE_BOUNDS = 0x01,
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RDMAP_ACC_VIOL = 0x02,
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RDMAP_STAG_NOT_ASSOC = 0x03,
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RDMAP_TO_WRAP = 0x04,
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RDMAP_INV_VERS = 0x05,
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RDMAP_INV_OPCODE = 0x06,
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RDMAP_STREAM_CATA = 0x07,
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RDMAP_GLOBAL_CATA = 0x08,
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RDMAP_CANT_INV_STAG = 0x09,
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RDMAP_UNSPECIFIED = 0xff
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};
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enum c4iw_ddp_ecodes {
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DDPT_INV_STAG = 0x00,
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DDPT_BASE_BOUNDS = 0x01,
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DDPT_STAG_NOT_ASSOC = 0x02,
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DDPT_TO_WRAP = 0x03,
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DDPT_INV_VERS = 0x04,
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DDPU_INV_QN = 0x01,
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DDPU_INV_MSN_NOBUF = 0x02,
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DDPU_INV_MSN_RANGE = 0x03,
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DDPU_INV_MO = 0x04,
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DDPU_MSG_TOOBIG = 0x05,
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DDPU_INV_VERS = 0x06
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};
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enum c4iw_mpa_ecodes {
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MPA_CRC_ERR = 0x02,
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MPA_MARKER_ERR = 0x03
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};
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enum c4iw_ep_state {
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IDLE = 0,
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LISTEN,
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CONNECTING,
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MPA_REQ_WAIT,
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MPA_REQ_SENT,
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MPA_REQ_RCVD,
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MPA_REP_SENT,
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FPDU_MODE,
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ABORTING,
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CLOSING,
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MORIBUND,
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DEAD,
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|
};
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|
|
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enum c4iw_ep_flags {
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|
PEER_ABORT_IN_PROGRESS = 0,
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|
ABORT_REQ_IN_PROGRESS = 1,
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RELEASE_RESOURCES = 2,
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CLOSE_SENT = 3,
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|
};
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|
|
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struct c4iw_ep_common {
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struct iw_cm_id *cm_id;
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|
struct c4iw_qp *qp;
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|
struct c4iw_dev *dev;
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|
enum c4iw_ep_state state;
|
|
struct kref kref;
|
|
struct mutex mutex;
|
|
struct sockaddr_in local_addr;
|
|
struct sockaddr_in remote_addr;
|
|
struct c4iw_wr_wait wr_wait;
|
|
unsigned long flags;
|
|
};
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|
|
|
struct c4iw_listen_ep {
|
|
struct c4iw_ep_common com;
|
|
unsigned int stid;
|
|
int backlog;
|
|
};
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|
|
|
struct c4iw_ep {
|
|
struct c4iw_ep_common com;
|
|
struct c4iw_ep *parent_ep;
|
|
struct timer_list timer;
|
|
struct list_head entry;
|
|
unsigned int atid;
|
|
u32 hwtid;
|
|
u32 snd_seq;
|
|
u32 rcv_seq;
|
|
struct l2t_entry *l2t;
|
|
struct dst_entry *dst;
|
|
struct sk_buff *mpa_skb;
|
|
struct c4iw_mpa_attributes mpa_attr;
|
|
u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
|
|
unsigned int mpa_pkt_len;
|
|
u32 ird;
|
|
u32 ord;
|
|
u32 smac_idx;
|
|
u32 tx_chan;
|
|
u32 mtu;
|
|
u16 mss;
|
|
u16 emss;
|
|
u16 plen;
|
|
u16 rss_qid;
|
|
u16 txq_idx;
|
|
u16 ctrlq_idx;
|
|
u8 tos;
|
|
};
|
|
|
|
static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
|
|
{
|
|
return cm_id->provider_data;
|
|
}
|
|
|
|
static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
|
|
{
|
|
return cm_id->provider_data;
|
|
}
|
|
|
|
static inline int compute_wscale(int win)
|
|
{
|
|
int wscale = 0;
|
|
|
|
while (wscale < 14 && (65535<<wscale) < win)
|
|
wscale++;
|
|
return wscale;
|
|
}
|
|
|
|
typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
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|
|
|
int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
|
|
struct l2t_entry *l2t);
|
|
void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
|
|
struct c4iw_dev_ucontext *uctx);
|
|
u32 c4iw_get_resource(struct kfifo *fifo, spinlock_t *lock);
|
|
void c4iw_put_resource(struct kfifo *fifo, u32 entry, spinlock_t *lock);
|
|
int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
|
|
int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
|
|
int c4iw_pblpool_create(struct c4iw_rdev *rdev);
|
|
int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
|
|
int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
|
|
void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
|
|
void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
|
|
void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
|
|
void c4iw_destroy_resource(struct c4iw_resource *rscp);
|
|
int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
|
|
int c4iw_register_device(struct c4iw_dev *dev);
|
|
void c4iw_unregister_device(struct c4iw_dev *dev);
|
|
int __init c4iw_cm_init(void);
|
|
void __exit c4iw_cm_term(void);
|
|
void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
|
|
struct c4iw_dev_ucontext *uctx);
|
|
void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
|
|
struct c4iw_dev_ucontext *uctx);
|
|
int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
|
|
int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
|
|
struct ib_send_wr **bad_wr);
|
|
int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
|
|
struct ib_recv_wr **bad_wr);
|
|
int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
|
|
struct ib_mw_bind *mw_bind);
|
|
int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
|
|
int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
|
|
int c4iw_destroy_listen(struct iw_cm_id *cm_id);
|
|
int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
|
|
int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
|
|
void c4iw_qp_add_ref(struct ib_qp *qp);
|
|
void c4iw_qp_rem_ref(struct ib_qp *qp);
|
|
void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
|
|
struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
|
|
struct ib_device *device,
|
|
int page_list_len);
|
|
struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
|
|
int c4iw_dealloc_mw(struct ib_mw *mw);
|
|
struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd);
|
|
struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
|
|
u64 length, u64 virt, int acc,
|
|
struct ib_udata *udata);
|
|
struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
|
|
struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
|
|
struct ib_phys_buf *buffer_list,
|
|
int num_phys_buf,
|
|
int acc,
|
|
u64 *iova_start);
|
|
int c4iw_reregister_phys_mem(struct ib_mr *mr,
|
|
int mr_rereg_mask,
|
|
struct ib_pd *pd,
|
|
struct ib_phys_buf *buffer_list,
|
|
int num_phys_buf,
|
|
int acc, u64 *iova_start);
|
|
int c4iw_dereg_mr(struct ib_mr *ib_mr);
|
|
int c4iw_destroy_cq(struct ib_cq *ib_cq);
|
|
struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
|
|
int vector,
|
|
struct ib_ucontext *ib_context,
|
|
struct ib_udata *udata);
|
|
int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
|
|
int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
|
|
int c4iw_destroy_qp(struct ib_qp *ib_qp);
|
|
struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
|
|
struct ib_qp_init_attr *attrs,
|
|
struct ib_udata *udata);
|
|
int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
|
|
int attr_mask, struct ib_udata *udata);
|
|
struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
|
|
u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
|
|
void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
|
|
u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
|
|
void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
|
|
u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
|
|
void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
|
|
int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
|
|
void c4iw_flush_hw_cq(struct t4_cq *cq);
|
|
void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
|
|
void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
|
|
int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
|
|
int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
|
|
int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
|
|
int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
|
|
u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
|
|
int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
|
|
u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
|
|
void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
|
|
struct c4iw_dev_ucontext *uctx);
|
|
u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
|
|
void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
|
|
struct c4iw_dev_ucontext *uctx);
|
|
void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
|
|
|
|
extern struct cxgb4_client t4c_client;
|
|
extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
|
|
extern int c4iw_max_read_depth;
|
|
|
|
#endif
|