mirror of https://gitee.com/openkylin/linux.git
508 lines
14 KiB
C
508 lines
14 KiB
C
/*
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* FPGA Manager Driver for Altera Arria/Cyclone/Stratix CvP
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*
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* Copyright (C) 2017 DENX Software Engineering
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*
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* Anatolij Gustschin <agust@denx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Manage Altera FPGA firmware using PCIe CvP.
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* Firmware must be in binary "rbf" format.
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/fpga/fpga-mgr.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/sizes.h>
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#define CVP_BAR 0 /* BAR used for data transfer in memory mode */
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#define CVP_DUMMY_WR 244 /* dummy writes to clear CvP state machine */
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#define TIMEOUT_US 2000 /* CVP STATUS timeout for USERMODE polling */
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/* Vendor Specific Extended Capability Registers */
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#define VSE_PCIE_EXT_CAP_ID 0x200
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#define VSE_PCIE_EXT_CAP_ID_VAL 0x000b /* 16bit */
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#define VSE_CVP_STATUS 0x21c /* 32bit */
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#define VSE_CVP_STATUS_CFG_RDY BIT(18) /* CVP_CONFIG_READY */
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#define VSE_CVP_STATUS_CFG_ERR BIT(19) /* CVP_CONFIG_ERROR */
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#define VSE_CVP_STATUS_CVP_EN BIT(20) /* ctrl block is enabling CVP */
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#define VSE_CVP_STATUS_USERMODE BIT(21) /* USERMODE */
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#define VSE_CVP_STATUS_CFG_DONE BIT(23) /* CVP_CONFIG_DONE */
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#define VSE_CVP_STATUS_PLD_CLK_IN_USE BIT(24) /* PLD_CLK_IN_USE */
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#define VSE_CVP_MODE_CTRL 0x220 /* 32bit */
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#define VSE_CVP_MODE_CTRL_CVP_MODE BIT(0) /* CVP (1) or normal mode (0) */
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#define VSE_CVP_MODE_CTRL_HIP_CLK_SEL BIT(1) /* PMA (1) or fabric clock (0) */
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#define VSE_CVP_MODE_CTRL_NUMCLKS_OFF 8 /* NUMCLKS bits offset */
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#define VSE_CVP_MODE_CTRL_NUMCLKS_MASK GENMASK(15, 8)
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#define VSE_CVP_DATA 0x228 /* 32bit */
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#define VSE_CVP_PROG_CTRL 0x22c /* 32bit */
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#define VSE_CVP_PROG_CTRL_CONFIG BIT(0)
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#define VSE_CVP_PROG_CTRL_START_XFER BIT(1)
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#define VSE_UNCOR_ERR_STATUS 0x234 /* 32bit */
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#define VSE_UNCOR_ERR_CVP_CFG_ERR BIT(5) /* CVP_CONFIG_ERROR_LATCHED */
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#define DRV_NAME "altera-cvp"
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#define ALTERA_CVP_MGR_NAME "Altera CvP FPGA Manager"
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/* Optional CvP config error status check for debugging */
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static bool altera_cvp_chkcfg;
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struct altera_cvp_conf {
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struct fpga_manager *mgr;
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struct pci_dev *pci_dev;
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void __iomem *map;
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void (*write_data)(struct altera_cvp_conf *, u32);
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char mgr_name[64];
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u8 numclks;
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};
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static enum fpga_mgr_states altera_cvp_state(struct fpga_manager *mgr)
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{
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struct altera_cvp_conf *conf = mgr->priv;
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u32 status;
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pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &status);
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if (status & VSE_CVP_STATUS_CFG_DONE)
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return FPGA_MGR_STATE_OPERATING;
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if (status & VSE_CVP_STATUS_CVP_EN)
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return FPGA_MGR_STATE_POWER_UP;
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return FPGA_MGR_STATE_UNKNOWN;
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}
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static void altera_cvp_write_data_iomem(struct altera_cvp_conf *conf, u32 val)
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{
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writel(val, conf->map);
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}
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static void altera_cvp_write_data_config(struct altera_cvp_conf *conf, u32 val)
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{
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pci_write_config_dword(conf->pci_dev, VSE_CVP_DATA, val);
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}
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/* switches between CvP clock and internal clock */
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static void altera_cvp_dummy_write(struct altera_cvp_conf *conf)
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{
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unsigned int i;
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u32 val;
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/* set 1 CVP clock cycle for every CVP Data Register Write */
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pci_read_config_dword(conf->pci_dev, VSE_CVP_MODE_CTRL, &val);
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val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
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val |= 1 << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
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pci_write_config_dword(conf->pci_dev, VSE_CVP_MODE_CTRL, val);
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for (i = 0; i < CVP_DUMMY_WR; i++)
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conf->write_data(conf, 0); /* dummy data, could be any value */
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}
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static int altera_cvp_wait_status(struct altera_cvp_conf *conf, u32 status_mask,
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u32 status_val, int timeout_us)
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{
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unsigned int retries;
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u32 val;
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retries = timeout_us / 10;
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if (timeout_us % 10)
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retries++;
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do {
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pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &val);
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if ((val & status_mask) == status_val)
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return 0;
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/* use small usleep value to re-check and break early */
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usleep_range(10, 11);
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} while (--retries);
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return -ETIMEDOUT;
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}
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static int altera_cvp_teardown(struct fpga_manager *mgr,
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struct fpga_image_info *info)
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{
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struct altera_cvp_conf *conf = mgr->priv;
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struct pci_dev *pdev = conf->pci_dev;
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int ret;
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u32 val;
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/* STEP 12 - reset START_XFER bit */
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pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val);
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val &= ~VSE_CVP_PROG_CTRL_START_XFER;
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pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val);
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/* STEP 13 - reset CVP_CONFIG bit */
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val &= ~VSE_CVP_PROG_CTRL_CONFIG;
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pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val);
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/*
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* STEP 14
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* - set CVP_NUMCLKS to 1 and then issue CVP_DUMMY_WR dummy
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* writes to the HIP
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*/
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altera_cvp_dummy_write(conf); /* from CVP clock to internal clock */
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/* STEP 15 - poll CVP_CONFIG_READY bit for 0 with 10us timeout */
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ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0, 10);
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if (ret)
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dev_err(&mgr->dev, "CFG_RDY == 0 timeout\n");
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return ret;
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}
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static int altera_cvp_write_init(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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struct altera_cvp_conf *conf = mgr->priv;
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struct pci_dev *pdev = conf->pci_dev;
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u32 iflags, val;
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int ret;
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iflags = info ? info->flags : 0;
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if (iflags & FPGA_MGR_PARTIAL_RECONFIG) {
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dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
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return -EINVAL;
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}
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/* Determine allowed clock to data ratio */
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if (iflags & FPGA_MGR_COMPRESSED_BITSTREAM)
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conf->numclks = 8; /* ratio for all compressed images */
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else if (iflags & FPGA_MGR_ENCRYPTED_BITSTREAM)
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conf->numclks = 4; /* for uncompressed and encrypted images */
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else
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conf->numclks = 1; /* for uncompressed and unencrypted images */
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/* STEP 1 - read CVP status and check CVP_EN flag */
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pci_read_config_dword(pdev, VSE_CVP_STATUS, &val);
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if (!(val & VSE_CVP_STATUS_CVP_EN)) {
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dev_err(&mgr->dev, "CVP mode off: 0x%04x\n", val);
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return -ENODEV;
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}
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if (val & VSE_CVP_STATUS_CFG_RDY) {
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dev_warn(&mgr->dev, "CvP already started, teardown first\n");
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ret = altera_cvp_teardown(mgr, info);
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if (ret)
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return ret;
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}
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/*
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* STEP 2
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* - set HIP_CLK_SEL and CVP_MODE (must be set in the order mentioned)
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*/
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/* switch from fabric to PMA clock */
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pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val);
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val |= VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
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pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val);
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/* set CVP mode */
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pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val);
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val |= VSE_CVP_MODE_CTRL_CVP_MODE;
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pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val);
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/*
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* STEP 3
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* - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
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*/
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altera_cvp_dummy_write(conf);
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/* STEP 4 - set CVP_CONFIG bit */
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pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val);
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/* request control block to begin transfer using CVP */
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val |= VSE_CVP_PROG_CTRL_CONFIG;
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pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val);
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/* STEP 5 - poll CVP_CONFIG READY for 1 with 10us timeout */
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ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY,
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VSE_CVP_STATUS_CFG_RDY, 10);
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if (ret) {
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dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n");
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return ret;
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}
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/*
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* STEP 6
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* - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
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*/
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altera_cvp_dummy_write(conf);
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/* STEP 7 - set START_XFER */
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pci_read_config_dword(pdev, VSE_CVP_PROG_CTRL, &val);
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val |= VSE_CVP_PROG_CTRL_START_XFER;
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pci_write_config_dword(pdev, VSE_CVP_PROG_CTRL, val);
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/* STEP 8 - start transfer (set CVP_NUMCLKS for bitstream) */
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pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val);
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val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
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val |= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
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pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val);
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return 0;
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}
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static inline int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes)
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{
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struct altera_cvp_conf *conf = mgr->priv;
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u32 val;
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/* STEP 10 (optional) - check CVP_CONFIG_ERROR flag */
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pci_read_config_dword(conf->pci_dev, VSE_CVP_STATUS, &val);
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if (val & VSE_CVP_STATUS_CFG_ERR) {
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dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n",
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bytes);
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return -EPROTO;
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}
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return 0;
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}
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static int altera_cvp_write(struct fpga_manager *mgr, const char *buf,
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size_t count)
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{
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struct altera_cvp_conf *conf = mgr->priv;
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const u32 *data;
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size_t done, remaining;
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int status = 0;
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u32 mask;
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/* STEP 9 - write 32-bit data from RBF file to CVP data register */
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data = (u32 *)buf;
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remaining = count;
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done = 0;
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while (remaining >= 4) {
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conf->write_data(conf, *data++);
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done += 4;
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remaining -= 4;
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/*
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* STEP 10 (optional) and STEP 11
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* - check error flag
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* - loop until data transfer completed
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* Config images can be huge (more than 40 MiB), so
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* only check after a new 4k data block has been written.
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* This reduces the number of checks and speeds up the
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* configuration process.
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*/
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if (altera_cvp_chkcfg && !(done % SZ_4K)) {
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status = altera_cvp_chk_error(mgr, done);
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if (status < 0)
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return status;
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}
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}
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/* write up to 3 trailing bytes, if any */
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mask = BIT(remaining * 8) - 1;
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if (mask)
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conf->write_data(conf, *data & mask);
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if (altera_cvp_chkcfg)
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status = altera_cvp_chk_error(mgr, count);
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return status;
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}
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static int altera_cvp_write_complete(struct fpga_manager *mgr,
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struct fpga_image_info *info)
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{
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struct altera_cvp_conf *conf = mgr->priv;
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struct pci_dev *pdev = conf->pci_dev;
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int ret;
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u32 mask;
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u32 val;
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ret = altera_cvp_teardown(mgr, info);
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if (ret)
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return ret;
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/* STEP 16 - check CVP_CONFIG_ERROR_LATCHED bit */
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pci_read_config_dword(pdev, VSE_UNCOR_ERR_STATUS, &val);
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if (val & VSE_UNCOR_ERR_CVP_CFG_ERR) {
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dev_err(&mgr->dev, "detected CVP_CONFIG_ERROR_LATCHED!\n");
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return -EPROTO;
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}
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/* STEP 17 - reset CVP_MODE and HIP_CLK_SEL bit */
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pci_read_config_dword(pdev, VSE_CVP_MODE_CTRL, &val);
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val &= ~VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
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val &= ~VSE_CVP_MODE_CTRL_CVP_MODE;
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pci_write_config_dword(pdev, VSE_CVP_MODE_CTRL, val);
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/* STEP 18 - poll PLD_CLK_IN_USE and USER_MODE bits */
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mask = VSE_CVP_STATUS_PLD_CLK_IN_USE | VSE_CVP_STATUS_USERMODE;
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ret = altera_cvp_wait_status(conf, mask, mask, TIMEOUT_US);
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if (ret)
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dev_err(&mgr->dev, "PLD_CLK_IN_USE|USERMODE timeout\n");
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return ret;
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}
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static const struct fpga_manager_ops altera_cvp_ops = {
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.state = altera_cvp_state,
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.write_init = altera_cvp_write_init,
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.write = altera_cvp_write,
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.write_complete = altera_cvp_write_complete,
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};
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static ssize_t chkcfg_show(struct device_driver *dev, char *buf)
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{
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return snprintf(buf, 3, "%d\n", altera_cvp_chkcfg);
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}
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static ssize_t chkcfg_store(struct device_driver *drv, const char *buf,
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size_t count)
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{
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int ret;
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ret = kstrtobool(buf, &altera_cvp_chkcfg);
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if (ret)
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return ret;
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return count;
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}
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static DRIVER_ATTR_RW(chkcfg);
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static int altera_cvp_probe(struct pci_dev *pdev,
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const struct pci_device_id *dev_id);
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static void altera_cvp_remove(struct pci_dev *pdev);
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static struct pci_device_id altera_cvp_id_tbl[] = {
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{ PCI_VDEVICE(ALTERA, PCI_ANY_ID) },
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{ }
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};
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MODULE_DEVICE_TABLE(pci, altera_cvp_id_tbl);
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static struct pci_driver altera_cvp_driver = {
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.name = DRV_NAME,
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.id_table = altera_cvp_id_tbl,
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.probe = altera_cvp_probe,
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.remove = altera_cvp_remove,
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};
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static int altera_cvp_probe(struct pci_dev *pdev,
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const struct pci_device_id *dev_id)
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{
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struct altera_cvp_conf *conf;
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struct fpga_manager *mgr;
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u16 cmd, val;
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int ret;
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/*
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* First check if this is the expected FPGA device. PCI config
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* space access works without enabling the PCI device, memory
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* space access is enabled further down.
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*/
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pci_read_config_word(pdev, VSE_PCIE_EXT_CAP_ID, &val);
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if (val != VSE_PCIE_EXT_CAP_ID_VAL) {
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dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val);
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return -ENODEV;
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}
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conf = devm_kzalloc(&pdev->dev, sizeof(*conf), GFP_KERNEL);
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if (!conf)
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return -ENOMEM;
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/*
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* Enable memory BAR access. We cannot use pci_enable_device() here
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* because it will make the driver unusable with FPGA devices that
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* have additional big IOMEM resources (e.g. 4GiB BARs) on 32-bit
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* platform. Such BARs will not have an assigned address range and
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* pci_enable_device() will fail, complaining about not claimed BAR,
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* even if the concerned BAR is not needed for FPGA configuration
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* at all. Thus, enable the device via PCI config space command.
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*/
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pci_read_config_word(pdev, PCI_COMMAND, &cmd);
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if (!(cmd & PCI_COMMAND_MEMORY)) {
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cmd |= PCI_COMMAND_MEMORY;
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pci_write_config_word(pdev, PCI_COMMAND, cmd);
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}
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ret = pci_request_region(pdev, CVP_BAR, "CVP");
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if (ret) {
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dev_err(&pdev->dev, "Requesting CVP BAR region failed\n");
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goto err_disable;
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}
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conf->pci_dev = pdev;
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conf->write_data = altera_cvp_write_data_iomem;
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conf->map = pci_iomap(pdev, CVP_BAR, 0);
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if (!conf->map) {
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dev_warn(&pdev->dev, "Mapping CVP BAR failed\n");
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conf->write_data = altera_cvp_write_data_config;
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}
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snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s @%s",
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ALTERA_CVP_MGR_NAME, pci_name(pdev));
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mgr = devm_fpga_mgr_create(&pdev->dev, conf->mgr_name,
|
|
&altera_cvp_ops, conf);
|
|
if (!mgr) {
|
|
ret = -ENOMEM;
|
|
goto err_unmap;
|
|
}
|
|
|
|
pci_set_drvdata(pdev, mgr);
|
|
|
|
ret = fpga_mgr_register(mgr);
|
|
if (ret)
|
|
goto err_unmap;
|
|
|
|
ret = driver_create_file(&altera_cvp_driver.driver,
|
|
&driver_attr_chkcfg);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Can't create sysfs chkcfg file\n");
|
|
fpga_mgr_unregister(mgr);
|
|
goto err_unmap;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_unmap:
|
|
pci_iounmap(pdev, conf->map);
|
|
pci_release_region(pdev, CVP_BAR);
|
|
err_disable:
|
|
cmd &= ~PCI_COMMAND_MEMORY;
|
|
pci_write_config_word(pdev, PCI_COMMAND, cmd);
|
|
return ret;
|
|
}
|
|
|
|
static void altera_cvp_remove(struct pci_dev *pdev)
|
|
{
|
|
struct fpga_manager *mgr = pci_get_drvdata(pdev);
|
|
struct altera_cvp_conf *conf = mgr->priv;
|
|
u16 cmd;
|
|
|
|
driver_remove_file(&altera_cvp_driver.driver, &driver_attr_chkcfg);
|
|
fpga_mgr_unregister(mgr);
|
|
pci_iounmap(pdev, conf->map);
|
|
pci_release_region(pdev, CVP_BAR);
|
|
pci_read_config_word(pdev, PCI_COMMAND, &cmd);
|
|
cmd &= ~PCI_COMMAND_MEMORY;
|
|
pci_write_config_word(pdev, PCI_COMMAND, cmd);
|
|
}
|
|
|
|
module_pci_driver(altera_cvp_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
|
|
MODULE_DESCRIPTION("Module to load Altera FPGA over CvP");
|