mirror of https://gitee.com/openkylin/linux.git
673 lines
18 KiB
C
673 lines
18 KiB
C
/*
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* Copyright (c) 2011-2015 Xilinx Inc.
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* Copyright (c) 2015, National Instruments Corp.
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*
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* FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
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* in their vendor tree.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/fpga/fpga-mgr.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/pm.h>
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#include <linux/regmap.h>
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#include <linux/string.h>
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#include <linux/scatterlist.h>
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/* Offsets into SLCR regmap */
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/* FPGA Software Reset Control */
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#define SLCR_FPGA_RST_CTRL_OFFSET 0x240
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/* Level Shifters Enable */
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#define SLCR_LVL_SHFTR_EN_OFFSET 0x900
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/* Constant Definitions */
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/* Control Register */
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#define CTRL_OFFSET 0x00
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/* Lock Register */
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#define LOCK_OFFSET 0x04
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/* Interrupt Status Register */
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#define INT_STS_OFFSET 0x0c
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/* Interrupt Mask Register */
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#define INT_MASK_OFFSET 0x10
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/* Status Register */
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#define STATUS_OFFSET 0x14
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/* DMA Source Address Register */
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#define DMA_SRC_ADDR_OFFSET 0x18
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/* DMA Destination Address Reg */
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#define DMA_DST_ADDR_OFFSET 0x1c
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/* DMA Source Transfer Length */
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#define DMA_SRC_LEN_OFFSET 0x20
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/* DMA Destination Transfer */
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#define DMA_DEST_LEN_OFFSET 0x24
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/* Unlock Register */
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#define UNLOCK_OFFSET 0x34
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/* Misc. Control Register */
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#define MCTRL_OFFSET 0x80
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/* Control Register Bit definitions */
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/* Signal to reset FPGA */
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#define CTRL_PCFG_PROG_B_MASK BIT(30)
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/* Enable PCAP for PR */
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#define CTRL_PCAP_PR_MASK BIT(27)
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/* Enable PCAP */
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#define CTRL_PCAP_MODE_MASK BIT(26)
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/* Lower rate to allow decrypt on the fly */
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#define CTRL_PCAP_RATE_EN_MASK BIT(25)
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/* System booted in secure mode */
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#define CTRL_SEC_EN_MASK BIT(7)
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/* Miscellaneous Control Register bit definitions */
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/* Internal PCAP loopback */
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#define MCTRL_PCAP_LPBK_MASK BIT(4)
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/* Status register bit definitions */
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/* FPGA init status */
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#define STATUS_DMA_Q_F BIT(31)
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#define STATUS_DMA_Q_E BIT(30)
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#define STATUS_PCFG_INIT_MASK BIT(4)
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/* Interrupt Status/Mask Register Bit definitions */
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/* DMA command done */
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#define IXR_DMA_DONE_MASK BIT(13)
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/* DMA and PCAP cmd done */
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#define IXR_D_P_DONE_MASK BIT(12)
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/* FPGA programmed */
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#define IXR_PCFG_DONE_MASK BIT(2)
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#define IXR_ERROR_FLAGS_MASK 0x00F0C860
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#define IXR_ALL_MASK 0xF8F7F87F
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/* Miscellaneous constant values */
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/* Invalid DMA addr */
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#define DMA_INVALID_ADDRESS GENMASK(31, 0)
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/* Used to unlock the dev */
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#define UNLOCK_MASK 0x757bdf0d
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/* Timeout for polling reset bits */
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#define INIT_POLL_TIMEOUT 2500000
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/* Delay for polling reset bits */
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#define INIT_POLL_DELAY 20
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/* Signal this is the last DMA transfer, wait for the AXI and PCAP before
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* interrupting
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*/
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#define DMA_SRC_LAST_TRANSFER 1
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/* Timeout for DMA completion */
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#define DMA_TIMEOUT_MS 5000
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/* Masks for controlling stuff in SLCR */
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/* Disable all Level shifters */
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#define LVL_SHFTR_DISABLE_ALL_MASK 0x0
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/* Enable Level shifters from PS to PL */
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#define LVL_SHFTR_ENABLE_PS_TO_PL 0xa
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/* Enable Level shifters from PL to PS */
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#define LVL_SHFTR_ENABLE_PL_TO_PS 0xf
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/* Enable global resets */
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#define FPGA_RST_ALL_MASK 0xf
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/* Disable global resets */
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#define FPGA_RST_NONE_MASK 0x0
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struct zynq_fpga_priv {
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int irq;
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struct clk *clk;
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void __iomem *io_base;
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struct regmap *slcr;
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spinlock_t dma_lock;
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unsigned int dma_elm;
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unsigned int dma_nelms;
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struct scatterlist *cur_sg;
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struct completion dma_done;
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};
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static inline void zynq_fpga_write(struct zynq_fpga_priv *priv, u32 offset,
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u32 val)
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{
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writel(val, priv->io_base + offset);
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}
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static inline u32 zynq_fpga_read(const struct zynq_fpga_priv *priv,
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u32 offset)
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{
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return readl(priv->io_base + offset);
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}
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#define zynq_fpga_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
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readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
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timeout_us)
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/* Cause the specified irq mask bits to generate IRQs */
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static inline void zynq_fpga_set_irq(struct zynq_fpga_priv *priv, u32 enable)
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{
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zynq_fpga_write(priv, INT_MASK_OFFSET, ~enable);
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}
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/* Must be called with dma_lock held */
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static void zynq_step_dma(struct zynq_fpga_priv *priv)
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{
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u32 addr;
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u32 len;
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bool first;
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first = priv->dma_elm == 0;
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while (priv->cur_sg) {
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/* Feed the DMA queue until it is full. */
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if (zynq_fpga_read(priv, STATUS_OFFSET) & STATUS_DMA_Q_F)
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break;
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addr = sg_dma_address(priv->cur_sg);
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len = sg_dma_len(priv->cur_sg);
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if (priv->dma_elm + 1 == priv->dma_nelms) {
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/* The last transfer waits for the PCAP to finish too,
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* notice this also changes the irq_mask to ignore
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* IXR_DMA_DONE_MASK which ensures we do not trigger
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* the completion too early.
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*/
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addr |= DMA_SRC_LAST_TRANSFER;
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priv->cur_sg = NULL;
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} else {
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priv->cur_sg = sg_next(priv->cur_sg);
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priv->dma_elm++;
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}
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zynq_fpga_write(priv, DMA_SRC_ADDR_OFFSET, addr);
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zynq_fpga_write(priv, DMA_DST_ADDR_OFFSET, DMA_INVALID_ADDRESS);
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zynq_fpga_write(priv, DMA_SRC_LEN_OFFSET, len / 4);
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zynq_fpga_write(priv, DMA_DEST_LEN_OFFSET, 0);
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}
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/* Once the first transfer is queued we can turn on the ISR, future
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* calls to zynq_step_dma will happen from the ISR context. The
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* dma_lock spinlock guarentees this handover is done coherently, the
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* ISR enable is put at the end to avoid another CPU spinning in the
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* ISR on this lock.
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*/
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if (first && priv->cur_sg) {
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zynq_fpga_set_irq(priv,
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IXR_DMA_DONE_MASK | IXR_ERROR_FLAGS_MASK);
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} else if (!priv->cur_sg) {
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/* The last transfer changes to DMA & PCAP mode since we do
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* not want to continue until everything has been flushed into
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* the PCAP.
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*/
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zynq_fpga_set_irq(priv,
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IXR_D_P_DONE_MASK | IXR_ERROR_FLAGS_MASK);
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}
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}
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static irqreturn_t zynq_fpga_isr(int irq, void *data)
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{
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struct zynq_fpga_priv *priv = data;
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u32 intr_status;
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/* If anything other than DMA completion is reported stop and hand
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* control back to zynq_fpga_ops_write, something went wrong,
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* otherwise progress the DMA.
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*/
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spin_lock(&priv->dma_lock);
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intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
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if (!(intr_status & IXR_ERROR_FLAGS_MASK) &&
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(intr_status & IXR_DMA_DONE_MASK) && priv->cur_sg) {
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zynq_fpga_write(priv, INT_STS_OFFSET, IXR_DMA_DONE_MASK);
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zynq_step_dma(priv);
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spin_unlock(&priv->dma_lock);
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return IRQ_HANDLED;
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}
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spin_unlock(&priv->dma_lock);
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zynq_fpga_set_irq(priv, 0);
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complete(&priv->dma_done);
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return IRQ_HANDLED;
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}
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/* Sanity check the proposed bitstream. It must start with the sync word in
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* the correct byte order, and be dword aligned. The input is a Xilinx .bin
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* file with every 32 bit quantity swapped.
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*/
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static bool zynq_fpga_has_sync(const u8 *buf, size_t count)
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{
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for (; count >= 4; buf += 4, count -= 4)
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if (buf[0] == 0x66 && buf[1] == 0x55 && buf[2] == 0x99 &&
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buf[3] == 0xaa)
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return true;
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return false;
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}
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static int zynq_fpga_ops_write_init(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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struct zynq_fpga_priv *priv;
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u32 ctrl, status;
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int err;
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priv = mgr->priv;
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err = clk_enable(priv->clk);
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if (err)
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return err;
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/* check if bitstream is encrypted & and system's still secure */
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if (info->flags & FPGA_MGR_ENCRYPTED_BITSTREAM) {
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ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
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if (!(ctrl & CTRL_SEC_EN_MASK)) {
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dev_err(&mgr->dev,
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"System not secure, can't use crypted bitstreams\n");
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err = -EINVAL;
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goto out_err;
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}
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}
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/* don't globally reset PL if we're doing partial reconfig */
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if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
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if (!zynq_fpga_has_sync(buf, count)) {
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dev_err(&mgr->dev,
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"Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file\n");
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err = -EINVAL;
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goto out_err;
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}
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/* assert AXI interface resets */
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regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
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FPGA_RST_ALL_MASK);
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/* disable all level shifters */
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regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
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LVL_SHFTR_DISABLE_ALL_MASK);
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/* enable level shifters from PS to PL */
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regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
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LVL_SHFTR_ENABLE_PS_TO_PL);
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/* create a rising edge on PCFG_INIT. PCFG_INIT follows
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* PCFG_PROG_B, so we need to poll it after setting PCFG_PROG_B
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* to make sure the rising edge actually happens.
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* Note: PCFG_PROG_B is low active, sequence as described in
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* UG585 v1.10 page 211
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*/
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ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
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ctrl |= CTRL_PCFG_PROG_B_MASK;
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zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
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err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
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status & STATUS_PCFG_INIT_MASK,
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INIT_POLL_DELAY,
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INIT_POLL_TIMEOUT);
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if (err) {
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dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
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goto out_err;
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}
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ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
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ctrl &= ~CTRL_PCFG_PROG_B_MASK;
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zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
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err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
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!(status & STATUS_PCFG_INIT_MASK),
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INIT_POLL_DELAY,
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INIT_POLL_TIMEOUT);
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if (err) {
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dev_err(&mgr->dev, "Timeout waiting for !PCFG_INIT\n");
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goto out_err;
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}
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ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
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ctrl |= CTRL_PCFG_PROG_B_MASK;
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zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
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err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
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status & STATUS_PCFG_INIT_MASK,
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INIT_POLL_DELAY,
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INIT_POLL_TIMEOUT);
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if (err) {
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dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
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goto out_err;
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}
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}
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/* set configuration register with following options:
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* - enable PCAP interface
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* - set throughput for maximum speed (if bistream not crypted)
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* - set CPU in user mode
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*/
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ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
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if (info->flags & FPGA_MGR_ENCRYPTED_BITSTREAM)
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zynq_fpga_write(priv, CTRL_OFFSET,
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(CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK
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| CTRL_PCAP_RATE_EN_MASK | ctrl));
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else
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zynq_fpga_write(priv, CTRL_OFFSET,
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(CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK
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| ctrl));
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/* We expect that the command queue is empty right now. */
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status = zynq_fpga_read(priv, STATUS_OFFSET);
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if ((status & STATUS_DMA_Q_F) ||
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(status & STATUS_DMA_Q_E) != STATUS_DMA_Q_E) {
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dev_err(&mgr->dev, "DMA command queue not right\n");
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err = -EBUSY;
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goto out_err;
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}
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/* ensure internal PCAP loopback is disabled */
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ctrl = zynq_fpga_read(priv, MCTRL_OFFSET);
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zynq_fpga_write(priv, MCTRL_OFFSET, (~MCTRL_PCAP_LPBK_MASK & ctrl));
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clk_disable(priv->clk);
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return 0;
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out_err:
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clk_disable(priv->clk);
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return err;
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}
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static int zynq_fpga_ops_write(struct fpga_manager *mgr, struct sg_table *sgt)
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{
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struct zynq_fpga_priv *priv;
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const char *why;
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int err;
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u32 intr_status;
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unsigned long timeout;
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unsigned long flags;
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struct scatterlist *sg;
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int i;
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priv = mgr->priv;
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/* The hardware can only DMA multiples of 4 bytes, and it requires the
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* starting addresses to be aligned to 64 bits (UG585 pg 212).
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*/
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for_each_sg(sgt->sgl, sg, sgt->nents, i) {
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if ((sg->offset % 8) || (sg->length % 4)) {
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dev_err(&mgr->dev,
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"Invalid bitstream, chunks must be aligned\n");
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return -EINVAL;
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}
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}
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priv->dma_nelms =
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dma_map_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE);
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if (priv->dma_nelms == 0) {
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dev_err(&mgr->dev, "Unable to DMA map (TO_DEVICE)\n");
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return -ENOMEM;
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}
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/* enable clock */
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err = clk_enable(priv->clk);
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if (err)
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goto out_free;
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zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
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reinit_completion(&priv->dma_done);
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/* zynq_step_dma will turn on interrupts */
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spin_lock_irqsave(&priv->dma_lock, flags);
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priv->dma_elm = 0;
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priv->cur_sg = sgt->sgl;
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zynq_step_dma(priv);
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spin_unlock_irqrestore(&priv->dma_lock, flags);
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timeout = wait_for_completion_timeout(&priv->dma_done,
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msecs_to_jiffies(DMA_TIMEOUT_MS));
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spin_lock_irqsave(&priv->dma_lock, flags);
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zynq_fpga_set_irq(priv, 0);
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priv->cur_sg = NULL;
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spin_unlock_irqrestore(&priv->dma_lock, flags);
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intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
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zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
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/* There doesn't seem to be a way to force cancel any DMA, so if
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* something went wrong we are relying on the hardware to have halted
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* the DMA before we get here, if there was we could use
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* wait_for_completion_interruptible too.
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*/
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if (intr_status & IXR_ERROR_FLAGS_MASK) {
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why = "DMA reported error";
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err = -EIO;
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goto out_report;
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}
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if (priv->cur_sg ||
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!((intr_status & IXR_D_P_DONE_MASK) == IXR_D_P_DONE_MASK)) {
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if (timeout == 0)
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why = "DMA timed out";
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else
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why = "DMA did not complete";
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err = -EIO;
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goto out_report;
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}
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err = 0;
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goto out_clk;
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out_report:
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dev_err(&mgr->dev,
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"%s: INT_STS:0x%x CTRL:0x%x LOCK:0x%x INT_MASK:0x%x STATUS:0x%x MCTRL:0x%x\n",
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why,
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intr_status,
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zynq_fpga_read(priv, CTRL_OFFSET),
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zynq_fpga_read(priv, LOCK_OFFSET),
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zynq_fpga_read(priv, INT_MASK_OFFSET),
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zynq_fpga_read(priv, STATUS_OFFSET),
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zynq_fpga_read(priv, MCTRL_OFFSET));
|
|
|
|
out_clk:
|
|
clk_disable(priv->clk);
|
|
|
|
out_free:
|
|
dma_unmap_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE);
|
|
return err;
|
|
}
|
|
|
|
static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
|
|
struct fpga_image_info *info)
|
|
{
|
|
struct zynq_fpga_priv *priv = mgr->priv;
|
|
int err;
|
|
u32 intr_status;
|
|
|
|
err = clk_enable(priv->clk);
|
|
if (err)
|
|
return err;
|
|
|
|
err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status,
|
|
intr_status & IXR_PCFG_DONE_MASK,
|
|
INIT_POLL_DELAY,
|
|
INIT_POLL_TIMEOUT);
|
|
|
|
clk_disable(priv->clk);
|
|
|
|
if (err)
|
|
return err;
|
|
|
|
/* for the partial reconfig case we didn't touch the level shifters */
|
|
if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
|
|
/* enable level shifters from PL to PS */
|
|
regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
|
|
LVL_SHFTR_ENABLE_PL_TO_PS);
|
|
|
|
/* deassert AXI interface resets */
|
|
regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
|
|
FPGA_RST_NONE_MASK);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr)
|
|
{
|
|
int err;
|
|
u32 intr_status;
|
|
struct zynq_fpga_priv *priv;
|
|
|
|
priv = mgr->priv;
|
|
|
|
err = clk_enable(priv->clk);
|
|
if (err)
|
|
return FPGA_MGR_STATE_UNKNOWN;
|
|
|
|
intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
|
|
clk_disable(priv->clk);
|
|
|
|
if (intr_status & IXR_PCFG_DONE_MASK)
|
|
return FPGA_MGR_STATE_OPERATING;
|
|
|
|
return FPGA_MGR_STATE_UNKNOWN;
|
|
}
|
|
|
|
static const struct fpga_manager_ops zynq_fpga_ops = {
|
|
.initial_header_size = 128,
|
|
.state = zynq_fpga_ops_state,
|
|
.write_init = zynq_fpga_ops_write_init,
|
|
.write_sg = zynq_fpga_ops_write,
|
|
.write_complete = zynq_fpga_ops_write_complete,
|
|
};
|
|
|
|
static int zynq_fpga_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct zynq_fpga_priv *priv;
|
|
struct fpga_manager *mgr;
|
|
struct resource *res;
|
|
int err;
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
spin_lock_init(&priv->dma_lock);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
priv->io_base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(priv->io_base))
|
|
return PTR_ERR(priv->io_base);
|
|
|
|
priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node,
|
|
"syscon");
|
|
if (IS_ERR(priv->slcr)) {
|
|
dev_err(dev, "unable to get zynq-slcr regmap\n");
|
|
return PTR_ERR(priv->slcr);
|
|
}
|
|
|
|
init_completion(&priv->dma_done);
|
|
|
|
priv->irq = platform_get_irq(pdev, 0);
|
|
if (priv->irq < 0) {
|
|
dev_err(dev, "No IRQ available\n");
|
|
return priv->irq;
|
|
}
|
|
|
|
priv->clk = devm_clk_get(dev, "ref_clk");
|
|
if (IS_ERR(priv->clk)) {
|
|
dev_err(dev, "input clock not found\n");
|
|
return PTR_ERR(priv->clk);
|
|
}
|
|
|
|
err = clk_prepare_enable(priv->clk);
|
|
if (err) {
|
|
dev_err(dev, "unable to enable clock\n");
|
|
return err;
|
|
}
|
|
|
|
/* unlock the device */
|
|
zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK);
|
|
|
|
zynq_fpga_set_irq(priv, 0);
|
|
zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
|
|
err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev),
|
|
priv);
|
|
if (err) {
|
|
dev_err(dev, "unable to request IRQ\n");
|
|
clk_disable_unprepare(priv->clk);
|
|
return err;
|
|
}
|
|
|
|
clk_disable(priv->clk);
|
|
|
|
mgr = devm_fpga_mgr_create(dev, "Xilinx Zynq FPGA Manager",
|
|
&zynq_fpga_ops, priv);
|
|
if (!mgr)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, mgr);
|
|
|
|
err = fpga_mgr_register(mgr);
|
|
if (err) {
|
|
dev_err(dev, "unable to register FPGA manager\n");
|
|
clk_unprepare(priv->clk);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int zynq_fpga_remove(struct platform_device *pdev)
|
|
{
|
|
struct zynq_fpga_priv *priv;
|
|
struct fpga_manager *mgr;
|
|
|
|
mgr = platform_get_drvdata(pdev);
|
|
priv = mgr->priv;
|
|
|
|
fpga_mgr_unregister(mgr);
|
|
|
|
clk_unprepare(priv->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_OF
|
|
static const struct of_device_id zynq_fpga_of_match[] = {
|
|
{ .compatible = "xlnx,zynq-devcfg-1.0", },
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, zynq_fpga_of_match);
|
|
#endif
|
|
|
|
static struct platform_driver zynq_fpga_driver = {
|
|
.probe = zynq_fpga_probe,
|
|
.remove = zynq_fpga_remove,
|
|
.driver = {
|
|
.name = "zynq_fpga_manager",
|
|
.of_match_table = of_match_ptr(zynq_fpga_of_match),
|
|
},
|
|
};
|
|
|
|
module_platform_driver(zynq_fpga_driver);
|
|
|
|
MODULE_AUTHOR("Moritz Fischer <moritz.fischer@ettus.com>");
|
|
MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
|
|
MODULE_DESCRIPTION("Xilinx Zynq FPGA Manager");
|
|
MODULE_LICENSE("GPL v2");
|