mirror of https://gitee.com/openkylin/linux.git
623 lines
16 KiB
C
623 lines
16 KiB
C
/*
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* SPI driver for Nvidia's Tegra20 Serial Flash Controller.
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*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* Author: Laxman Dewangan <ldewangan@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/kthread.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/reset.h>
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#include <linux/spi/spi.h>
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#define SPI_COMMAND 0x000
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#define SPI_GO BIT(30)
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#define SPI_M_S BIT(28)
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#define SPI_ACTIVE_SCLK_MASK (0x3 << 26)
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#define SPI_ACTIVE_SCLK_DRIVE_LOW (0 << 26)
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#define SPI_ACTIVE_SCLK_DRIVE_HIGH (1 << 26)
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#define SPI_ACTIVE_SCLK_PULL_LOW (2 << 26)
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#define SPI_ACTIVE_SCLK_PULL_HIGH (3 << 26)
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#define SPI_CK_SDA_FALLING (1 << 21)
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#define SPI_CK_SDA_RISING (0 << 21)
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#define SPI_CK_SDA_MASK (1 << 21)
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#define SPI_ACTIVE_SDA (0x3 << 18)
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#define SPI_ACTIVE_SDA_DRIVE_LOW (0 << 18)
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#define SPI_ACTIVE_SDA_DRIVE_HIGH (1 << 18)
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#define SPI_ACTIVE_SDA_PULL_LOW (2 << 18)
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#define SPI_ACTIVE_SDA_PULL_HIGH (3 << 18)
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#define SPI_CS_POL_INVERT BIT(16)
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#define SPI_TX_EN BIT(15)
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#define SPI_RX_EN BIT(14)
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#define SPI_CS_VAL_HIGH BIT(13)
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#define SPI_CS_VAL_LOW 0x0
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#define SPI_CS_SW BIT(12)
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#define SPI_CS_HW 0x0
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#define SPI_CS_DELAY_MASK (7 << 9)
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#define SPI_CS3_EN BIT(8)
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#define SPI_CS2_EN BIT(7)
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#define SPI_CS1_EN BIT(6)
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#define SPI_CS0_EN BIT(5)
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#define SPI_CS_MASK (SPI_CS3_EN | SPI_CS2_EN | \
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SPI_CS1_EN | SPI_CS0_EN)
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#define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
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#define SPI_MODES (SPI_ACTIVE_SCLK_MASK | SPI_CK_SDA_MASK)
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#define SPI_STATUS 0x004
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#define SPI_BSY BIT(31)
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#define SPI_RDY BIT(30)
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#define SPI_TXF_FLUSH BIT(29)
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#define SPI_RXF_FLUSH BIT(28)
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#define SPI_RX_UNF BIT(27)
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#define SPI_TX_OVF BIT(26)
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#define SPI_RXF_EMPTY BIT(25)
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#define SPI_RXF_FULL BIT(24)
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#define SPI_TXF_EMPTY BIT(23)
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#define SPI_TXF_FULL BIT(22)
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#define SPI_BLK_CNT(count) (((count) & 0xffff) + 1)
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#define SPI_FIFO_ERROR (SPI_RX_UNF | SPI_TX_OVF)
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#define SPI_FIFO_EMPTY (SPI_TX_EMPTY | SPI_RX_EMPTY)
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#define SPI_RX_CMP 0x8
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#define SPI_DMA_CTL 0x0C
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#define SPI_DMA_EN BIT(31)
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#define SPI_IE_RXC BIT(27)
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#define SPI_IE_TXC BIT(26)
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#define SPI_PACKED BIT(20)
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#define SPI_RX_TRIG_MASK (0x3 << 18)
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#define SPI_RX_TRIG_1W (0x0 << 18)
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#define SPI_RX_TRIG_4W (0x1 << 18)
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#define SPI_TX_TRIG_MASK (0x3 << 16)
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#define SPI_TX_TRIG_1W (0x0 << 16)
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#define SPI_TX_TRIG_4W (0x1 << 16)
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#define SPI_DMA_BLK_COUNT(count) (((count) - 1) & 0xFFFF);
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#define SPI_TX_FIFO 0x10
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#define SPI_RX_FIFO 0x20
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#define DATA_DIR_TX (1 << 0)
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#define DATA_DIR_RX (1 << 1)
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#define MAX_CHIP_SELECT 4
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#define SPI_FIFO_DEPTH 4
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#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
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struct tegra_sflash_data {
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struct device *dev;
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struct spi_master *master;
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spinlock_t lock;
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struct clk *clk;
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struct reset_control *rst;
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void __iomem *base;
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unsigned irq;
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u32 cur_speed;
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struct spi_device *cur_spi;
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unsigned cur_pos;
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unsigned cur_len;
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unsigned bytes_per_word;
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unsigned cur_direction;
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unsigned curr_xfer_words;
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unsigned cur_rx_pos;
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unsigned cur_tx_pos;
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u32 tx_status;
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u32 rx_status;
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u32 status_reg;
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u32 def_command_reg;
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u32 command_reg;
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u32 dma_control_reg;
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struct completion xfer_completion;
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struct spi_transfer *curr_xfer;
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};
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static int tegra_sflash_runtime_suspend(struct device *dev);
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static int tegra_sflash_runtime_resume(struct device *dev);
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static inline u32 tegra_sflash_readl(struct tegra_sflash_data *tsd,
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unsigned long reg)
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{
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return readl(tsd->base + reg);
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}
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static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd,
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u32 val, unsigned long reg)
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{
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writel(val, tsd->base + reg);
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}
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static void tegra_sflash_clear_status(struct tegra_sflash_data *tsd)
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{
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/* Write 1 to clear status register */
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tegra_sflash_writel(tsd, SPI_RDY | SPI_FIFO_ERROR, SPI_STATUS);
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}
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static unsigned tegra_sflash_calculate_curr_xfer_param(
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struct spi_device *spi, struct tegra_sflash_data *tsd,
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struct spi_transfer *t)
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{
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unsigned remain_len = t->len - tsd->cur_pos;
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unsigned max_word;
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tsd->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8);
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max_word = remain_len / tsd->bytes_per_word;
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if (max_word > SPI_FIFO_DEPTH)
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max_word = SPI_FIFO_DEPTH;
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tsd->curr_xfer_words = max_word;
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return max_word;
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}
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static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf(
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struct tegra_sflash_data *tsd, struct spi_transfer *t)
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{
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unsigned nbytes;
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u32 status;
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unsigned max_n_32bit = tsd->curr_xfer_words;
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u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos;
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if (max_n_32bit > SPI_FIFO_DEPTH)
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max_n_32bit = SPI_FIFO_DEPTH;
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nbytes = max_n_32bit * tsd->bytes_per_word;
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status = tegra_sflash_readl(tsd, SPI_STATUS);
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while (!(status & SPI_TXF_FULL)) {
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int i;
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u32 x = 0;
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for (i = 0; nbytes && (i < tsd->bytes_per_word);
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i++, nbytes--)
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x |= (u32)(*tx_buf++) << (i * 8);
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tegra_sflash_writel(tsd, x, SPI_TX_FIFO);
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if (!nbytes)
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break;
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status = tegra_sflash_readl(tsd, SPI_STATUS);
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}
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tsd->cur_tx_pos += max_n_32bit * tsd->bytes_per_word;
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return max_n_32bit;
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}
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static int tegra_sflash_read_rx_fifo_to_client_rxbuf(
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struct tegra_sflash_data *tsd, struct spi_transfer *t)
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{
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u32 status;
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unsigned int read_words = 0;
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u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos;
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status = tegra_sflash_readl(tsd, SPI_STATUS);
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while (!(status & SPI_RXF_EMPTY)) {
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int i;
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u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO);
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for (i = 0; (i < tsd->bytes_per_word); i++)
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*rx_buf++ = (x >> (i*8)) & 0xFF;
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read_words++;
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status = tegra_sflash_readl(tsd, SPI_STATUS);
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}
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tsd->cur_rx_pos += read_words * tsd->bytes_per_word;
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return 0;
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}
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static int tegra_sflash_start_cpu_based_transfer(
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struct tegra_sflash_data *tsd, struct spi_transfer *t)
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{
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u32 val = 0;
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unsigned cur_words;
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if (tsd->cur_direction & DATA_DIR_TX)
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val |= SPI_IE_TXC;
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if (tsd->cur_direction & DATA_DIR_RX)
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val |= SPI_IE_RXC;
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tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
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tsd->dma_control_reg = val;
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if (tsd->cur_direction & DATA_DIR_TX)
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cur_words = tegra_sflash_fill_tx_fifo_from_client_txbuf(tsd, t);
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else
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cur_words = tsd->curr_xfer_words;
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val |= SPI_DMA_BLK_COUNT(cur_words);
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tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
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tsd->dma_control_reg = val;
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val |= SPI_DMA_EN;
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tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
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return 0;
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}
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static int tegra_sflash_start_transfer_one(struct spi_device *spi,
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struct spi_transfer *t, bool is_first_of_msg,
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bool is_single_xfer)
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{
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struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);
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u32 speed;
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u32 command;
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speed = t->speed_hz;
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if (speed != tsd->cur_speed) {
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clk_set_rate(tsd->clk, speed);
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tsd->cur_speed = speed;
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}
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tsd->cur_spi = spi;
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tsd->cur_pos = 0;
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tsd->cur_rx_pos = 0;
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tsd->cur_tx_pos = 0;
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tsd->curr_xfer = t;
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tegra_sflash_calculate_curr_xfer_param(spi, tsd, t);
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if (is_first_of_msg) {
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command = tsd->def_command_reg;
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command |= SPI_BIT_LENGTH(t->bits_per_word - 1);
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command |= SPI_CS_VAL_HIGH;
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command &= ~SPI_MODES;
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if (spi->mode & SPI_CPHA)
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command |= SPI_CK_SDA_FALLING;
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if (spi->mode & SPI_CPOL)
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command |= SPI_ACTIVE_SCLK_DRIVE_HIGH;
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else
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command |= SPI_ACTIVE_SCLK_DRIVE_LOW;
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command |= SPI_CS0_EN << spi->chip_select;
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} else {
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command = tsd->command_reg;
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command &= ~SPI_BIT_LENGTH(~0);
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command |= SPI_BIT_LENGTH(t->bits_per_word - 1);
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command &= ~(SPI_RX_EN | SPI_TX_EN);
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}
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tsd->cur_direction = 0;
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if (t->rx_buf) {
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command |= SPI_RX_EN;
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tsd->cur_direction |= DATA_DIR_RX;
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}
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if (t->tx_buf) {
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command |= SPI_TX_EN;
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tsd->cur_direction |= DATA_DIR_TX;
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}
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tegra_sflash_writel(tsd, command, SPI_COMMAND);
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tsd->command_reg = command;
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return tegra_sflash_start_cpu_based_transfer(tsd, t);
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}
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static int tegra_sflash_transfer_one_message(struct spi_master *master,
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struct spi_message *msg)
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{
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bool is_first_msg = true;
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int single_xfer;
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struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
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struct spi_transfer *xfer;
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struct spi_device *spi = msg->spi;
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int ret;
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msg->status = 0;
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msg->actual_length = 0;
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single_xfer = list_is_singular(&msg->transfers);
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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reinit_completion(&tsd->xfer_completion);
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ret = tegra_sflash_start_transfer_one(spi, xfer,
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is_first_msg, single_xfer);
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if (ret < 0) {
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dev_err(tsd->dev,
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"spi can not start transfer, err %d\n", ret);
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goto exit;
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}
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is_first_msg = false;
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ret = wait_for_completion_timeout(&tsd->xfer_completion,
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SPI_DMA_TIMEOUT);
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if (WARN_ON(ret == 0)) {
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dev_err(tsd->dev,
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"spi trasfer timeout, err %d\n", ret);
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ret = -EIO;
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goto exit;
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}
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if (tsd->tx_status || tsd->rx_status) {
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dev_err(tsd->dev, "Error in Transfer\n");
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ret = -EIO;
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goto exit;
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}
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msg->actual_length += xfer->len;
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if (xfer->cs_change && xfer->delay_usecs) {
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tegra_sflash_writel(tsd, tsd->def_command_reg,
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SPI_COMMAND);
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udelay(xfer->delay_usecs);
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}
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}
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ret = 0;
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exit:
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tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
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msg->status = ret;
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spi_finalize_current_message(master);
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return ret;
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}
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static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)
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{
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struct spi_transfer *t = tsd->curr_xfer;
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unsigned long flags;
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spin_lock_irqsave(&tsd->lock, flags);
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if (tsd->tx_status || tsd->rx_status || (tsd->status_reg & SPI_BSY)) {
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dev_err(tsd->dev,
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"CpuXfer ERROR bit set 0x%x\n", tsd->status_reg);
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dev_err(tsd->dev,
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"CpuXfer 0x%08x:0x%08x\n", tsd->command_reg,
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tsd->dma_control_reg);
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reset_control_assert(tsd->rst);
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udelay(2);
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reset_control_deassert(tsd->rst);
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complete(&tsd->xfer_completion);
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goto exit;
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}
|
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|
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if (tsd->cur_direction & DATA_DIR_RX)
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tegra_sflash_read_rx_fifo_to_client_rxbuf(tsd, t);
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|
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if (tsd->cur_direction & DATA_DIR_TX)
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tsd->cur_pos = tsd->cur_tx_pos;
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else
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tsd->cur_pos = tsd->cur_rx_pos;
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|
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if (tsd->cur_pos == t->len) {
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complete(&tsd->xfer_completion);
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goto exit;
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}
|
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|
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tegra_sflash_calculate_curr_xfer_param(tsd->cur_spi, tsd, t);
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tegra_sflash_start_cpu_based_transfer(tsd, t);
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exit:
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spin_unlock_irqrestore(&tsd->lock, flags);
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return IRQ_HANDLED;
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}
|
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|
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static irqreturn_t tegra_sflash_isr(int irq, void *context_data)
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{
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struct tegra_sflash_data *tsd = context_data;
|
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|
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tsd->status_reg = tegra_sflash_readl(tsd, SPI_STATUS);
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if (tsd->cur_direction & DATA_DIR_TX)
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tsd->tx_status = tsd->status_reg & SPI_TX_OVF;
|
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|
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if (tsd->cur_direction & DATA_DIR_RX)
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tsd->rx_status = tsd->status_reg & SPI_RX_UNF;
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tegra_sflash_clear_status(tsd);
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|
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return handle_cpu_based_xfer(tsd);
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}
|
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|
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static struct of_device_id tegra_sflash_of_match[] = {
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{ .compatible = "nvidia,tegra20-sflash", },
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{}
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};
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MODULE_DEVICE_TABLE(of, tegra_sflash_of_match);
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|
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static int tegra_sflash_probe(struct platform_device *pdev)
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{
|
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struct spi_master *master;
|
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struct tegra_sflash_data *tsd;
|
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struct resource *r;
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int ret;
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const struct of_device_id *match;
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|
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match = of_match_device(tegra_sflash_of_match, &pdev->dev);
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if (!match) {
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dev_err(&pdev->dev, "Error: No device match found\n");
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return -ENODEV;
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}
|
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|
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master = spi_alloc_master(&pdev->dev, sizeof(*tsd));
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if (!master) {
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dev_err(&pdev->dev, "master allocation failed\n");
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return -ENOMEM;
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}
|
|
|
|
/* the spi->mode bits understood by this driver: */
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA;
|
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master->transfer_one_message = tegra_sflash_transfer_one_message;
|
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master->auto_runtime_pm = true;
|
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master->num_chipselect = MAX_CHIP_SELECT;
|
|
|
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platform_set_drvdata(pdev, master);
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tsd = spi_master_get_devdata(master);
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tsd->master = master;
|
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tsd->dev = &pdev->dev;
|
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spin_lock_init(&tsd->lock);
|
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|
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if (of_property_read_u32(tsd->dev->of_node, "spi-max-frequency",
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&master->max_speed_hz))
|
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master->max_speed_hz = 25000000; /* 25MHz */
|
|
|
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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tsd->base = devm_ioremap_resource(&pdev->dev, r);
|
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if (IS_ERR(tsd->base)) {
|
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ret = PTR_ERR(tsd->base);
|
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goto exit_free_master;
|
|
}
|
|
|
|
tsd->irq = platform_get_irq(pdev, 0);
|
|
ret = request_irq(tsd->irq, tegra_sflash_isr, 0,
|
|
dev_name(&pdev->dev), tsd);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
|
|
tsd->irq);
|
|
goto exit_free_master;
|
|
}
|
|
|
|
tsd->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(tsd->clk)) {
|
|
dev_err(&pdev->dev, "can not get clock\n");
|
|
ret = PTR_ERR(tsd->clk);
|
|
goto exit_free_irq;
|
|
}
|
|
|
|
tsd->rst = devm_reset_control_get(&pdev->dev, "spi");
|
|
if (IS_ERR(tsd->rst)) {
|
|
dev_err(&pdev->dev, "can not get reset\n");
|
|
ret = PTR_ERR(tsd->rst);
|
|
goto exit_free_irq;
|
|
}
|
|
|
|
init_completion(&tsd->xfer_completion);
|
|
pm_runtime_enable(&pdev->dev);
|
|
if (!pm_runtime_enabled(&pdev->dev)) {
|
|
ret = tegra_sflash_runtime_resume(&pdev->dev);
|
|
if (ret)
|
|
goto exit_pm_disable;
|
|
}
|
|
|
|
ret = pm_runtime_get_sync(&pdev->dev);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
|
|
goto exit_pm_disable;
|
|
}
|
|
|
|
/* Reset controller */
|
|
reset_control_assert(tsd->rst);
|
|
udelay(2);
|
|
reset_control_deassert(tsd->rst);
|
|
|
|
tsd->def_command_reg = SPI_M_S | SPI_CS_SW;
|
|
tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
|
|
pm_runtime_put(&pdev->dev);
|
|
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
ret = devm_spi_register_master(&pdev->dev, master);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "can not register to master err %d\n", ret);
|
|
goto exit_pm_disable;
|
|
}
|
|
return ret;
|
|
|
|
exit_pm_disable:
|
|
pm_runtime_disable(&pdev->dev);
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
tegra_sflash_runtime_suspend(&pdev->dev);
|
|
exit_free_irq:
|
|
free_irq(tsd->irq, tsd);
|
|
exit_free_master:
|
|
spi_master_put(master);
|
|
return ret;
|
|
}
|
|
|
|
static int tegra_sflash_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
|
|
|
|
free_irq(tsd->irq, tsd);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
if (!pm_runtime_status_suspended(&pdev->dev))
|
|
tegra_sflash_runtime_suspend(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int tegra_sflash_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
|
|
return spi_master_suspend(master);
|
|
}
|
|
|
|
static int tegra_sflash_resume(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
|
|
int ret;
|
|
|
|
ret = pm_runtime_get_sync(dev);
|
|
if (ret < 0) {
|
|
dev_err(dev, "pm runtime failed, e = %d\n", ret);
|
|
return ret;
|
|
}
|
|
tegra_sflash_writel(tsd, tsd->command_reg, SPI_COMMAND);
|
|
pm_runtime_put(dev);
|
|
|
|
return spi_master_resume(master);
|
|
}
|
|
#endif
|
|
|
|
static int tegra_sflash_runtime_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
|
|
|
|
/* Flush all write which are in PPSB queue by reading back */
|
|
tegra_sflash_readl(tsd, SPI_COMMAND);
|
|
|
|
clk_disable_unprepare(tsd->clk);
|
|
return 0;
|
|
}
|
|
|
|
static int tegra_sflash_runtime_resume(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(tsd->clk);
|
|
if (ret < 0) {
|
|
dev_err(tsd->dev, "clk_prepare failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops slink_pm_ops = {
|
|
SET_RUNTIME_PM_OPS(tegra_sflash_runtime_suspend,
|
|
tegra_sflash_runtime_resume, NULL)
|
|
SET_SYSTEM_SLEEP_PM_OPS(tegra_sflash_suspend, tegra_sflash_resume)
|
|
};
|
|
static struct platform_driver tegra_sflash_driver = {
|
|
.driver = {
|
|
.name = "spi-tegra-sflash",
|
|
.owner = THIS_MODULE,
|
|
.pm = &slink_pm_ops,
|
|
.of_match_table = tegra_sflash_of_match,
|
|
},
|
|
.probe = tegra_sflash_probe,
|
|
.remove = tegra_sflash_remove,
|
|
};
|
|
module_platform_driver(tegra_sflash_driver);
|
|
|
|
MODULE_ALIAS("platform:spi-tegra-sflash");
|
|
MODULE_DESCRIPTION("NVIDIA Tegra20 Serial Flash Controller Driver");
|
|
MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
|
|
MODULE_LICENSE("GPL v2");
|