mirror of https://gitee.com/openkylin/linux.git
1802 lines
46 KiB
C
1802 lines
46 KiB
C
/*
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* intel_pstate.c: Native P state management for Intel processors
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*
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* (C) Copyright 2012 Intel Corporation
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* Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/ktime.h>
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#include <linux/hrtimer.h>
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#include <linux/tick.h>
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#include <linux/slab.h>
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#include <linux/sched.h>
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#include <linux/list.h>
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#include <linux/cpu.h>
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#include <linux/cpufreq.h>
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#include <linux/sysfs.h>
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#include <linux/types.h>
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#include <linux/fs.h>
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#include <linux/debugfs.h>
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#include <linux/acpi.h>
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#include <linux/vmalloc.h>
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#include <trace/events/power.h>
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#include <asm/div64.h>
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#include <asm/msr.h>
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#include <asm/cpu_device_id.h>
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#include <asm/cpufeature.h>
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#define ATOM_RATIOS 0x66a
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#define ATOM_VIDS 0x66b
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#define ATOM_TURBO_RATIOS 0x66c
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#define ATOM_TURBO_VIDS 0x66d
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#ifdef CONFIG_ACPI
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#include <acpi/processor.h>
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#endif
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#define FRAC_BITS 8
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#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
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#define fp_toint(X) ((X) >> FRAC_BITS)
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static inline int32_t mul_fp(int32_t x, int32_t y)
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{
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return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
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}
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static inline int32_t div_fp(s64 x, s64 y)
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{
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return div64_s64((int64_t)x << FRAC_BITS, y);
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}
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static inline int ceiling_fp(int32_t x)
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{
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int mask, ret;
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ret = fp_toint(x);
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mask = (1 << FRAC_BITS) - 1;
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if (x & mask)
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ret += 1;
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return ret;
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}
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/**
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* struct sample - Store performance sample
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* @core_pct_busy: Ratio of APERF/MPERF in percent, which is actual
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* performance during last sample period
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* @busy_scaled: Scaled busy value which is used to calculate next
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* P state. This can be different than core_pct_busy
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* to account for cpu idle period
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* @aperf: Difference of actual performance frequency clock count
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* read from APERF MSR between last and current sample
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* @mperf: Difference of maximum performance frequency clock count
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* read from MPERF MSR between last and current sample
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* @tsc: Difference of time stamp counter between last and
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* current sample
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* @freq: Effective frequency calculated from APERF/MPERF
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* @time: Current time from scheduler
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*
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* This structure is used in the cpudata structure to store performance sample
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* data for choosing next P State.
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*/
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struct sample {
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int32_t core_pct_busy;
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int32_t busy_scaled;
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u64 aperf;
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u64 mperf;
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u64 tsc;
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int freq;
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u64 time;
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};
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/**
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* struct pstate_data - Store P state data
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* @current_pstate: Current requested P state
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* @min_pstate: Min P state possible for this platform
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* @max_pstate: Max P state possible for this platform
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* @max_pstate_physical:This is physical Max P state for a processor
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* This can be higher than the max_pstate which can
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* be limited by platform thermal design power limits
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* @scaling: Scaling factor to convert frequency to cpufreq
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* frequency units
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* @turbo_pstate: Max Turbo P state possible for this platform
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*
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* Stores the per cpu model P state limits and current P state.
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*/
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struct pstate_data {
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int current_pstate;
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int min_pstate;
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int max_pstate;
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int max_pstate_physical;
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int scaling;
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int turbo_pstate;
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};
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/**
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* struct vid_data - Stores voltage information data
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* @min: VID data for this platform corresponding to
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* the lowest P state
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* @max: VID data corresponding to the highest P State.
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* @turbo: VID data for turbo P state
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* @ratio: Ratio of (vid max - vid min) /
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* (max P state - Min P State)
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*
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* Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
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* This data is used in Atom platforms, where in addition to target P state,
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* the voltage data needs to be specified to select next P State.
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*/
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struct vid_data {
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int min;
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int max;
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int turbo;
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int32_t ratio;
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};
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/**
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* struct _pid - Stores PID data
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* @setpoint: Target set point for busyness or performance
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* @integral: Storage for accumulated error values
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* @p_gain: PID proportional gain
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* @i_gain: PID integral gain
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* @d_gain: PID derivative gain
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* @deadband: PID deadband
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* @last_err: Last error storage for integral part of PID calculation
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*
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* Stores PID coefficients and last error for PID controller.
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*/
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struct _pid {
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int setpoint;
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int32_t integral;
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int32_t p_gain;
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int32_t i_gain;
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int32_t d_gain;
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int deadband;
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int32_t last_err;
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};
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/**
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* struct cpudata - Per CPU instance data storage
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* @cpu: CPU number for this instance data
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* @update_util: CPUFreq utility callback information
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* @pstate: Stores P state limits for this CPU
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* @vid: Stores VID limits for this CPU
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* @pid: Stores PID parameters for this CPU
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* @last_sample_time: Last Sample time
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* @prev_aperf: Last APERF value read from APERF MSR
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* @prev_mperf: Last MPERF value read from MPERF MSR
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* @prev_tsc: Last timestamp counter (TSC) value
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* @prev_cummulative_iowait: IO Wait time difference from last and
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* current sample
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* @sample: Storage for storing last Sample data
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* @acpi_perf_data: Stores ACPI perf information read from _PSS
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* @valid_pss_table: Set to true for valid ACPI _PSS entries found
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*
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* This structure stores per CPU instance data for all CPUs.
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*/
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struct cpudata {
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int cpu;
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struct update_util_data update_util;
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struct pstate_data pstate;
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struct vid_data vid;
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struct _pid pid;
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u64 last_sample_time;
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u64 prev_aperf;
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u64 prev_mperf;
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u64 prev_tsc;
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u64 prev_cummulative_iowait;
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struct sample sample;
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#ifdef CONFIG_ACPI
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struct acpi_processor_performance acpi_perf_data;
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bool valid_pss_table;
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#endif
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};
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static struct cpudata **all_cpu_data;
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/**
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* struct pid_adjust_policy - Stores static PID configuration data
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* @sample_rate_ms: PID calculation sample rate in ms
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* @sample_rate_ns: Sample rate calculation in ns
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* @deadband: PID deadband
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* @setpoint: PID Setpoint
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* @p_gain_pct: PID proportional gain
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* @i_gain_pct: PID integral gain
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* @d_gain_pct: PID derivative gain
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*
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* Stores per CPU model static PID configuration data.
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*/
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struct pstate_adjust_policy {
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int sample_rate_ms;
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s64 sample_rate_ns;
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int deadband;
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int setpoint;
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int p_gain_pct;
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int d_gain_pct;
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int i_gain_pct;
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};
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/**
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* struct pstate_funcs - Per CPU model specific callbacks
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* @get_max: Callback to get maximum non turbo effective P state
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* @get_max_physical: Callback to get maximum non turbo physical P state
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* @get_min: Callback to get minimum P state
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* @get_turbo: Callback to get turbo P state
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* @get_scaling: Callback to get frequency scaling factor
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* @get_val: Callback to convert P state to actual MSR write value
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* @get_vid: Callback to get VID data for Atom platforms
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* @get_target_pstate: Callback to a function to calculate next P state to use
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*
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* Core and Atom CPU models have different way to get P State limits. This
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* structure is used to store those callbacks.
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*/
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struct pstate_funcs {
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int (*get_max)(void);
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int (*get_max_physical)(void);
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int (*get_min)(void);
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int (*get_turbo)(void);
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int (*get_scaling)(void);
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u64 (*get_val)(struct cpudata*, int pstate);
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void (*get_vid)(struct cpudata *);
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int32_t (*get_target_pstate)(struct cpudata *);
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};
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/**
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* struct cpu_defaults- Per CPU model default config data
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* @pid_policy: PID config data
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* @funcs: Callback function data
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*/
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struct cpu_defaults {
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struct pstate_adjust_policy pid_policy;
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struct pstate_funcs funcs;
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};
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static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
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static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
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static struct pstate_adjust_policy pid_params;
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static struct pstate_funcs pstate_funcs;
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static int hwp_active;
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#ifdef CONFIG_ACPI
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static bool acpi_ppc;
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#endif
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/**
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* struct perf_limits - Store user and policy limits
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* @no_turbo: User requested turbo state from intel_pstate sysfs
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* @turbo_disabled: Platform turbo status either from msr
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* MSR_IA32_MISC_ENABLE or when maximum available pstate
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* matches the maximum turbo pstate
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* @max_perf_pct: Effective maximum performance limit in percentage, this
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* is minimum of either limits enforced by cpufreq policy
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* or limits from user set limits via intel_pstate sysfs
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* @min_perf_pct: Effective minimum performance limit in percentage, this
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* is maximum of either limits enforced by cpufreq policy
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* or limits from user set limits via intel_pstate sysfs
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* @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
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* This value is used to limit max pstate
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* @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
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* This value is used to limit min pstate
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* @max_policy_pct: The maximum performance in percentage enforced by
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* cpufreq setpolicy interface
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* @max_sysfs_pct: The maximum performance in percentage enforced by
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* intel pstate sysfs interface
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* @min_policy_pct: The minimum performance in percentage enforced by
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* cpufreq setpolicy interface
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* @min_sysfs_pct: The minimum performance in percentage enforced by
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* intel pstate sysfs interface
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*
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* Storage for user and policy defined limits.
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*/
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struct perf_limits {
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int no_turbo;
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int turbo_disabled;
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int max_perf_pct;
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int min_perf_pct;
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int32_t max_perf;
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int32_t min_perf;
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int max_policy_pct;
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int max_sysfs_pct;
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int min_policy_pct;
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int min_sysfs_pct;
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};
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static struct perf_limits performance_limits = {
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.no_turbo = 0,
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.turbo_disabled = 0,
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.max_perf_pct = 100,
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.max_perf = int_tofp(1),
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.min_perf_pct = 100,
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.min_perf = int_tofp(1),
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.max_policy_pct = 100,
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.max_sysfs_pct = 100,
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.min_policy_pct = 0,
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.min_sysfs_pct = 0,
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};
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static struct perf_limits powersave_limits = {
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.no_turbo = 0,
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.turbo_disabled = 0,
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.max_perf_pct = 100,
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.max_perf = int_tofp(1),
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.min_perf_pct = 0,
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.min_perf = 0,
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.max_policy_pct = 100,
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.max_sysfs_pct = 100,
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.min_policy_pct = 0,
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.min_sysfs_pct = 0,
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};
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#ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
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static struct perf_limits *limits = &performance_limits;
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#else
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static struct perf_limits *limits = &powersave_limits;
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#endif
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#ifdef CONFIG_ACPI
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/*
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* The max target pstate ratio is a 8 bit value in both PLATFORM_INFO MSR and
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* in TURBO_RATIO_LIMIT MSR, which pstate driver stores in max_pstate and
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* max_turbo_pstate fields. The PERF_CTL MSR contains 16 bit value for P state
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* ratio, out of it only high 8 bits are used. For example 0x1700 is setting
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* target ratio 0x17. The _PSS control value stores in a format which can be
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* directly written to PERF_CTL MSR. But in intel_pstate driver this shift
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* occurs during write to PERF_CTL (E.g. for cores core_set_pstate()).
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* This function converts the _PSS control value to intel pstate driver format
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* for comparison and assignment.
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*/
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static int convert_to_native_pstate_format(struct cpudata *cpu, int index)
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{
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return cpu->acpi_perf_data.states[index].control >> 8;
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}
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static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
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{
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struct cpudata *cpu;
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int turbo_pss_ctl;
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int ret;
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int i;
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if (!acpi_ppc)
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return;
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cpu = all_cpu_data[policy->cpu];
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ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
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policy->cpu);
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if (ret)
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return;
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/*
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* Check if the control value in _PSS is for PERF_CTL MSR, which should
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* guarantee that the states returned by it map to the states in our
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* list directly.
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*/
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if (cpu->acpi_perf_data.control_register.space_id !=
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ACPI_ADR_SPACE_FIXED_HARDWARE)
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goto err;
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/*
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* If there is only one entry _PSS, simply ignore _PSS and continue as
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* usual without taking _PSS into account
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*/
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if (cpu->acpi_perf_data.state_count < 2)
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goto err;
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pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
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for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
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pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
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(i == cpu->acpi_perf_data.state ? '*' : ' '), i,
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(u32) cpu->acpi_perf_data.states[i].core_frequency,
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(u32) cpu->acpi_perf_data.states[i].power,
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(u32) cpu->acpi_perf_data.states[i].control);
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}
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/*
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* The _PSS table doesn't contain whole turbo frequency range.
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* This just contains +1 MHZ above the max non turbo frequency,
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* with control value corresponding to max turbo ratio. But
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* when cpufreq set policy is called, it will call with this
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* max frequency, which will cause a reduced performance as
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* this driver uses real max turbo frequency as the max
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* frequency. So correct this frequency in _PSS table to
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* correct max turbo frequency based on the turbo ratio.
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* Also need to convert to MHz as _PSS freq is in MHz.
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*/
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turbo_pss_ctl = convert_to_native_pstate_format(cpu, 0);
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if (turbo_pss_ctl > cpu->pstate.max_pstate)
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cpu->acpi_perf_data.states[0].core_frequency =
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policy->cpuinfo.max_freq / 1000;
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cpu->valid_pss_table = true;
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pr_info("_PPC limits will be enforced\n");
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return;
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err:
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cpu->valid_pss_table = false;
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acpi_processor_unregister_performance(policy->cpu);
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}
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static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
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{
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struct cpudata *cpu;
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cpu = all_cpu_data[policy->cpu];
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if (!cpu->valid_pss_table)
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return;
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acpi_processor_unregister_performance(policy->cpu);
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}
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#else
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static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
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{
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}
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static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
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{
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}
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#endif
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static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
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int deadband, int integral) {
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pid->setpoint = int_tofp(setpoint);
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pid->deadband = int_tofp(deadband);
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pid->integral = int_tofp(integral);
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pid->last_err = int_tofp(setpoint) - int_tofp(busy);
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}
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static inline void pid_p_gain_set(struct _pid *pid, int percent)
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{
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pid->p_gain = div_fp(percent, 100);
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}
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static inline void pid_i_gain_set(struct _pid *pid, int percent)
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{
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pid->i_gain = div_fp(percent, 100);
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}
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static inline void pid_d_gain_set(struct _pid *pid, int percent)
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{
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pid->d_gain = div_fp(percent, 100);
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}
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static signed int pid_calc(struct _pid *pid, int32_t busy)
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{
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signed int result;
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int32_t pterm, dterm, fp_error;
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int32_t integral_limit;
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fp_error = pid->setpoint - busy;
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if (abs(fp_error) <= pid->deadband)
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return 0;
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pterm = mul_fp(pid->p_gain, fp_error);
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pid->integral += fp_error;
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/*
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* We limit the integral here so that it will never
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* get higher than 30. This prevents it from becoming
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* too large an input over long periods of time and allows
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* it to get factored out sooner.
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*
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* The value of 30 was chosen through experimentation.
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*/
|
|
integral_limit = int_tofp(30);
|
|
if (pid->integral > integral_limit)
|
|
pid->integral = integral_limit;
|
|
if (pid->integral < -integral_limit)
|
|
pid->integral = -integral_limit;
|
|
|
|
dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
|
|
pid->last_err = fp_error;
|
|
|
|
result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
|
|
result = result + (1 << (FRAC_BITS-1));
|
|
return (signed int)fp_toint(result);
|
|
}
|
|
|
|
static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
|
|
{
|
|
pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
|
|
pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
|
|
pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
|
|
|
|
pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
|
|
}
|
|
|
|
static inline void intel_pstate_reset_all_pid(void)
|
|
{
|
|
unsigned int cpu;
|
|
|
|
for_each_online_cpu(cpu) {
|
|
if (all_cpu_data[cpu])
|
|
intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
|
|
}
|
|
}
|
|
|
|
static inline void update_turbo_state(void)
|
|
{
|
|
u64 misc_en;
|
|
struct cpudata *cpu;
|
|
|
|
cpu = all_cpu_data[0];
|
|
rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
|
|
limits->turbo_disabled =
|
|
(misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
|
|
cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
|
|
}
|
|
|
|
static void intel_pstate_hwp_set(const struct cpumask *cpumask)
|
|
{
|
|
int min, hw_min, max, hw_max, cpu, range, adj_range;
|
|
u64 value, cap;
|
|
|
|
rdmsrl(MSR_HWP_CAPABILITIES, cap);
|
|
hw_min = HWP_LOWEST_PERF(cap);
|
|
hw_max = HWP_HIGHEST_PERF(cap);
|
|
range = hw_max - hw_min;
|
|
|
|
for_each_cpu(cpu, cpumask) {
|
|
rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
|
|
adj_range = limits->min_perf_pct * range / 100;
|
|
min = hw_min + adj_range;
|
|
value &= ~HWP_MIN_PERF(~0L);
|
|
value |= HWP_MIN_PERF(min);
|
|
|
|
adj_range = limits->max_perf_pct * range / 100;
|
|
max = hw_min + adj_range;
|
|
if (limits->no_turbo) {
|
|
hw_max = HWP_GUARANTEED_PERF(cap);
|
|
if (hw_max < max)
|
|
max = hw_max;
|
|
}
|
|
|
|
value &= ~HWP_MAX_PERF(~0L);
|
|
value |= HWP_MAX_PERF(max);
|
|
wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
|
|
}
|
|
}
|
|
|
|
static void intel_pstate_hwp_set_online_cpus(void)
|
|
{
|
|
get_online_cpus();
|
|
intel_pstate_hwp_set(cpu_online_mask);
|
|
put_online_cpus();
|
|
}
|
|
|
|
/************************** debugfs begin ************************/
|
|
static int pid_param_set(void *data, u64 val)
|
|
{
|
|
*(u32 *)data = val;
|
|
intel_pstate_reset_all_pid();
|
|
return 0;
|
|
}
|
|
|
|
static int pid_param_get(void *data, u64 *val)
|
|
{
|
|
*val = *(u32 *)data;
|
|
return 0;
|
|
}
|
|
DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
|
|
|
|
struct pid_param {
|
|
char *name;
|
|
void *value;
|
|
};
|
|
|
|
static struct pid_param pid_files[] = {
|
|
{"sample_rate_ms", &pid_params.sample_rate_ms},
|
|
{"d_gain_pct", &pid_params.d_gain_pct},
|
|
{"i_gain_pct", &pid_params.i_gain_pct},
|
|
{"deadband", &pid_params.deadband},
|
|
{"setpoint", &pid_params.setpoint},
|
|
{"p_gain_pct", &pid_params.p_gain_pct},
|
|
{NULL, NULL}
|
|
};
|
|
|
|
static void __init intel_pstate_debug_expose_params(void)
|
|
{
|
|
struct dentry *debugfs_parent;
|
|
int i = 0;
|
|
|
|
if (hwp_active)
|
|
return;
|
|
debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
|
|
if (IS_ERR_OR_NULL(debugfs_parent))
|
|
return;
|
|
while (pid_files[i].name) {
|
|
debugfs_create_file(pid_files[i].name, 0660,
|
|
debugfs_parent, pid_files[i].value,
|
|
&fops_pid_param);
|
|
i++;
|
|
}
|
|
}
|
|
|
|
/************************** debugfs end ************************/
|
|
|
|
/************************** sysfs begin ************************/
|
|
#define show_one(file_name, object) \
|
|
static ssize_t show_##file_name \
|
|
(struct kobject *kobj, struct attribute *attr, char *buf) \
|
|
{ \
|
|
return sprintf(buf, "%u\n", limits->object); \
|
|
}
|
|
|
|
static ssize_t show_turbo_pct(struct kobject *kobj,
|
|
struct attribute *attr, char *buf)
|
|
{
|
|
struct cpudata *cpu;
|
|
int total, no_turbo, turbo_pct;
|
|
uint32_t turbo_fp;
|
|
|
|
cpu = all_cpu_data[0];
|
|
|
|
total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
|
|
no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
|
|
turbo_fp = div_fp(no_turbo, total);
|
|
turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
|
|
return sprintf(buf, "%u\n", turbo_pct);
|
|
}
|
|
|
|
static ssize_t show_num_pstates(struct kobject *kobj,
|
|
struct attribute *attr, char *buf)
|
|
{
|
|
struct cpudata *cpu;
|
|
int total;
|
|
|
|
cpu = all_cpu_data[0];
|
|
total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
|
|
return sprintf(buf, "%u\n", total);
|
|
}
|
|
|
|
static ssize_t show_no_turbo(struct kobject *kobj,
|
|
struct attribute *attr, char *buf)
|
|
{
|
|
ssize_t ret;
|
|
|
|
update_turbo_state();
|
|
if (limits->turbo_disabled)
|
|
ret = sprintf(buf, "%u\n", limits->turbo_disabled);
|
|
else
|
|
ret = sprintf(buf, "%u\n", limits->no_turbo);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
|
|
const char *buf, size_t count)
|
|
{
|
|
unsigned int input;
|
|
int ret;
|
|
|
|
ret = sscanf(buf, "%u", &input);
|
|
if (ret != 1)
|
|
return -EINVAL;
|
|
|
|
update_turbo_state();
|
|
if (limits->turbo_disabled) {
|
|
pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
|
|
return -EPERM;
|
|
}
|
|
|
|
limits->no_turbo = clamp_t(int, input, 0, 1);
|
|
|
|
if (hwp_active)
|
|
intel_pstate_hwp_set_online_cpus();
|
|
|
|
return count;
|
|
}
|
|
|
|
static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
|
|
const char *buf, size_t count)
|
|
{
|
|
unsigned int input;
|
|
int ret;
|
|
|
|
ret = sscanf(buf, "%u", &input);
|
|
if (ret != 1)
|
|
return -EINVAL;
|
|
|
|
limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
|
|
limits->max_perf_pct = min(limits->max_policy_pct,
|
|
limits->max_sysfs_pct);
|
|
limits->max_perf_pct = max(limits->min_policy_pct,
|
|
limits->max_perf_pct);
|
|
limits->max_perf_pct = max(limits->min_perf_pct,
|
|
limits->max_perf_pct);
|
|
limits->max_perf = div_fp(limits->max_perf_pct, 100);
|
|
|
|
if (hwp_active)
|
|
intel_pstate_hwp_set_online_cpus();
|
|
return count;
|
|
}
|
|
|
|
static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
|
|
const char *buf, size_t count)
|
|
{
|
|
unsigned int input;
|
|
int ret;
|
|
|
|
ret = sscanf(buf, "%u", &input);
|
|
if (ret != 1)
|
|
return -EINVAL;
|
|
|
|
limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
|
|
limits->min_perf_pct = max(limits->min_policy_pct,
|
|
limits->min_sysfs_pct);
|
|
limits->min_perf_pct = min(limits->max_policy_pct,
|
|
limits->min_perf_pct);
|
|
limits->min_perf_pct = min(limits->max_perf_pct,
|
|
limits->min_perf_pct);
|
|
limits->min_perf = div_fp(limits->min_perf_pct, 100);
|
|
|
|
if (hwp_active)
|
|
intel_pstate_hwp_set_online_cpus();
|
|
return count;
|
|
}
|
|
|
|
show_one(max_perf_pct, max_perf_pct);
|
|
show_one(min_perf_pct, min_perf_pct);
|
|
|
|
define_one_global_rw(no_turbo);
|
|
define_one_global_rw(max_perf_pct);
|
|
define_one_global_rw(min_perf_pct);
|
|
define_one_global_ro(turbo_pct);
|
|
define_one_global_ro(num_pstates);
|
|
|
|
static struct attribute *intel_pstate_attributes[] = {
|
|
&no_turbo.attr,
|
|
&max_perf_pct.attr,
|
|
&min_perf_pct.attr,
|
|
&turbo_pct.attr,
|
|
&num_pstates.attr,
|
|
NULL
|
|
};
|
|
|
|
static struct attribute_group intel_pstate_attr_group = {
|
|
.attrs = intel_pstate_attributes,
|
|
};
|
|
|
|
static void __init intel_pstate_sysfs_expose_params(void)
|
|
{
|
|
struct kobject *intel_pstate_kobject;
|
|
int rc;
|
|
|
|
intel_pstate_kobject = kobject_create_and_add("intel_pstate",
|
|
&cpu_subsys.dev_root->kobj);
|
|
BUG_ON(!intel_pstate_kobject);
|
|
rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
|
|
BUG_ON(rc);
|
|
}
|
|
/************************** sysfs end ************************/
|
|
|
|
static void intel_pstate_hwp_enable(struct cpudata *cpudata)
|
|
{
|
|
/* First disable HWP notification interrupt as we don't process them */
|
|
wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
|
|
|
|
wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
|
|
}
|
|
|
|
static int atom_get_min_pstate(void)
|
|
{
|
|
u64 value;
|
|
|
|
rdmsrl(ATOM_RATIOS, value);
|
|
return (value >> 8) & 0x7F;
|
|
}
|
|
|
|
static int atom_get_max_pstate(void)
|
|
{
|
|
u64 value;
|
|
|
|
rdmsrl(ATOM_RATIOS, value);
|
|
return (value >> 16) & 0x7F;
|
|
}
|
|
|
|
static int atom_get_turbo_pstate(void)
|
|
{
|
|
u64 value;
|
|
|
|
rdmsrl(ATOM_TURBO_RATIOS, value);
|
|
return value & 0x7F;
|
|
}
|
|
|
|
static u64 atom_get_val(struct cpudata *cpudata, int pstate)
|
|
{
|
|
u64 val;
|
|
int32_t vid_fp;
|
|
u32 vid;
|
|
|
|
val = (u64)pstate << 8;
|
|
if (limits->no_turbo && !limits->turbo_disabled)
|
|
val |= (u64)1 << 32;
|
|
|
|
vid_fp = cpudata->vid.min + mul_fp(
|
|
int_tofp(pstate - cpudata->pstate.min_pstate),
|
|
cpudata->vid.ratio);
|
|
|
|
vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
|
|
vid = ceiling_fp(vid_fp);
|
|
|
|
if (pstate > cpudata->pstate.max_pstate)
|
|
vid = cpudata->vid.turbo;
|
|
|
|
return val | vid;
|
|
}
|
|
|
|
static int silvermont_get_scaling(void)
|
|
{
|
|
u64 value;
|
|
int i;
|
|
/* Defined in Table 35-6 from SDM (Sept 2015) */
|
|
static int silvermont_freq_table[] = {
|
|
83300, 100000, 133300, 116700, 80000};
|
|
|
|
rdmsrl(MSR_FSB_FREQ, value);
|
|
i = value & 0x7;
|
|
WARN_ON(i > 4);
|
|
|
|
return silvermont_freq_table[i];
|
|
}
|
|
|
|
static int airmont_get_scaling(void)
|
|
{
|
|
u64 value;
|
|
int i;
|
|
/* Defined in Table 35-10 from SDM (Sept 2015) */
|
|
static int airmont_freq_table[] = {
|
|
83300, 100000, 133300, 116700, 80000,
|
|
93300, 90000, 88900, 87500};
|
|
|
|
rdmsrl(MSR_FSB_FREQ, value);
|
|
i = value & 0xF;
|
|
WARN_ON(i > 8);
|
|
|
|
return airmont_freq_table[i];
|
|
}
|
|
|
|
static void atom_get_vid(struct cpudata *cpudata)
|
|
{
|
|
u64 value;
|
|
|
|
rdmsrl(ATOM_VIDS, value);
|
|
cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
|
|
cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
|
|
cpudata->vid.ratio = div_fp(
|
|
cpudata->vid.max - cpudata->vid.min,
|
|
int_tofp(cpudata->pstate.max_pstate -
|
|
cpudata->pstate.min_pstate));
|
|
|
|
rdmsrl(ATOM_TURBO_VIDS, value);
|
|
cpudata->vid.turbo = value & 0x7f;
|
|
}
|
|
|
|
static int core_get_min_pstate(void)
|
|
{
|
|
u64 value;
|
|
|
|
rdmsrl(MSR_PLATFORM_INFO, value);
|
|
return (value >> 40) & 0xFF;
|
|
}
|
|
|
|
static int core_get_max_pstate_physical(void)
|
|
{
|
|
u64 value;
|
|
|
|
rdmsrl(MSR_PLATFORM_INFO, value);
|
|
return (value >> 8) & 0xFF;
|
|
}
|
|
|
|
static int core_get_max_pstate(void)
|
|
{
|
|
u64 tar;
|
|
u64 plat_info;
|
|
int max_pstate;
|
|
int err;
|
|
|
|
rdmsrl(MSR_PLATFORM_INFO, plat_info);
|
|
max_pstate = (plat_info >> 8) & 0xFF;
|
|
|
|
err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
|
|
if (!err) {
|
|
/* Do some sanity checking for safety */
|
|
if (plat_info & 0x600000000) {
|
|
u64 tdp_ctrl;
|
|
u64 tdp_ratio;
|
|
int tdp_msr;
|
|
|
|
err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
|
|
if (err)
|
|
goto skip_tar;
|
|
|
|
tdp_msr = MSR_CONFIG_TDP_NOMINAL + tdp_ctrl;
|
|
err = rdmsrl_safe(tdp_msr, &tdp_ratio);
|
|
if (err)
|
|
goto skip_tar;
|
|
|
|
if (tdp_ratio - 1 == tar) {
|
|
max_pstate = tar;
|
|
pr_debug("max_pstate=TAC %x\n", max_pstate);
|
|
} else {
|
|
goto skip_tar;
|
|
}
|
|
}
|
|
}
|
|
|
|
skip_tar:
|
|
return max_pstate;
|
|
}
|
|
|
|
static int core_get_turbo_pstate(void)
|
|
{
|
|
u64 value;
|
|
int nont, ret;
|
|
|
|
rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
|
|
nont = core_get_max_pstate();
|
|
ret = (value) & 255;
|
|
if (ret <= nont)
|
|
ret = nont;
|
|
return ret;
|
|
}
|
|
|
|
static inline int core_get_scaling(void)
|
|
{
|
|
return 100000;
|
|
}
|
|
|
|
static u64 core_get_val(struct cpudata *cpudata, int pstate)
|
|
{
|
|
u64 val;
|
|
|
|
val = (u64)pstate << 8;
|
|
if (limits->no_turbo && !limits->turbo_disabled)
|
|
val |= (u64)1 << 32;
|
|
|
|
return val;
|
|
}
|
|
|
|
static int knl_get_turbo_pstate(void)
|
|
{
|
|
u64 value;
|
|
int nont, ret;
|
|
|
|
rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
|
|
nont = core_get_max_pstate();
|
|
ret = (((value) >> 8) & 0xFF);
|
|
if (ret <= nont)
|
|
ret = nont;
|
|
return ret;
|
|
}
|
|
|
|
static struct cpu_defaults core_params = {
|
|
.pid_policy = {
|
|
.sample_rate_ms = 10,
|
|
.deadband = 0,
|
|
.setpoint = 97,
|
|
.p_gain_pct = 20,
|
|
.d_gain_pct = 0,
|
|
.i_gain_pct = 0,
|
|
},
|
|
.funcs = {
|
|
.get_max = core_get_max_pstate,
|
|
.get_max_physical = core_get_max_pstate_physical,
|
|
.get_min = core_get_min_pstate,
|
|
.get_turbo = core_get_turbo_pstate,
|
|
.get_scaling = core_get_scaling,
|
|
.get_val = core_get_val,
|
|
.get_target_pstate = get_target_pstate_use_performance,
|
|
},
|
|
};
|
|
|
|
static struct cpu_defaults silvermont_params = {
|
|
.pid_policy = {
|
|
.sample_rate_ms = 10,
|
|
.deadband = 0,
|
|
.setpoint = 60,
|
|
.p_gain_pct = 14,
|
|
.d_gain_pct = 0,
|
|
.i_gain_pct = 4,
|
|
},
|
|
.funcs = {
|
|
.get_max = atom_get_max_pstate,
|
|
.get_max_physical = atom_get_max_pstate,
|
|
.get_min = atom_get_min_pstate,
|
|
.get_turbo = atom_get_turbo_pstate,
|
|
.get_val = atom_get_val,
|
|
.get_scaling = silvermont_get_scaling,
|
|
.get_vid = atom_get_vid,
|
|
.get_target_pstate = get_target_pstate_use_cpu_load,
|
|
},
|
|
};
|
|
|
|
static struct cpu_defaults airmont_params = {
|
|
.pid_policy = {
|
|
.sample_rate_ms = 10,
|
|
.deadband = 0,
|
|
.setpoint = 60,
|
|
.p_gain_pct = 14,
|
|
.d_gain_pct = 0,
|
|
.i_gain_pct = 4,
|
|
},
|
|
.funcs = {
|
|
.get_max = atom_get_max_pstate,
|
|
.get_max_physical = atom_get_max_pstate,
|
|
.get_min = atom_get_min_pstate,
|
|
.get_turbo = atom_get_turbo_pstate,
|
|
.get_val = atom_get_val,
|
|
.get_scaling = airmont_get_scaling,
|
|
.get_vid = atom_get_vid,
|
|
.get_target_pstate = get_target_pstate_use_cpu_load,
|
|
},
|
|
};
|
|
|
|
static struct cpu_defaults knl_params = {
|
|
.pid_policy = {
|
|
.sample_rate_ms = 10,
|
|
.deadband = 0,
|
|
.setpoint = 97,
|
|
.p_gain_pct = 20,
|
|
.d_gain_pct = 0,
|
|
.i_gain_pct = 0,
|
|
},
|
|
.funcs = {
|
|
.get_max = core_get_max_pstate,
|
|
.get_max_physical = core_get_max_pstate_physical,
|
|
.get_min = core_get_min_pstate,
|
|
.get_turbo = knl_get_turbo_pstate,
|
|
.get_scaling = core_get_scaling,
|
|
.get_val = core_get_val,
|
|
.get_target_pstate = get_target_pstate_use_performance,
|
|
},
|
|
};
|
|
|
|
static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
|
|
{
|
|
int max_perf = cpu->pstate.turbo_pstate;
|
|
int max_perf_adj;
|
|
int min_perf;
|
|
|
|
if (limits->no_turbo || limits->turbo_disabled)
|
|
max_perf = cpu->pstate.max_pstate;
|
|
|
|
/*
|
|
* performance can be limited by user through sysfs, by cpufreq
|
|
* policy, or by cpu specific default values determined through
|
|
* experimentation.
|
|
*/
|
|
max_perf_adj = fp_toint(max_perf * limits->max_perf);
|
|
*max = clamp_t(int, max_perf_adj,
|
|
cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
|
|
|
|
min_perf = fp_toint(max_perf * limits->min_perf);
|
|
*min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
|
|
}
|
|
|
|
static inline void intel_pstate_record_pstate(struct cpudata *cpu, int pstate)
|
|
{
|
|
trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
|
|
cpu->pstate.current_pstate = pstate;
|
|
}
|
|
|
|
static void intel_pstate_set_min_pstate(struct cpudata *cpu)
|
|
{
|
|
int pstate = cpu->pstate.min_pstate;
|
|
|
|
intel_pstate_record_pstate(cpu, pstate);
|
|
/*
|
|
* Generally, there is no guarantee that this code will always run on
|
|
* the CPU being updated, so force the register update to run on the
|
|
* right CPU.
|
|
*/
|
|
wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
|
|
pstate_funcs.get_val(cpu, pstate));
|
|
}
|
|
|
|
static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
|
|
{
|
|
cpu->pstate.min_pstate = pstate_funcs.get_min();
|
|
cpu->pstate.max_pstate = pstate_funcs.get_max();
|
|
cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
|
|
cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
|
|
cpu->pstate.scaling = pstate_funcs.get_scaling();
|
|
|
|
if (pstate_funcs.get_vid)
|
|
pstate_funcs.get_vid(cpu);
|
|
|
|
intel_pstate_set_min_pstate(cpu);
|
|
}
|
|
|
|
static inline void intel_pstate_calc_busy(struct cpudata *cpu)
|
|
{
|
|
struct sample *sample = &cpu->sample;
|
|
int64_t core_pct;
|
|
|
|
core_pct = sample->aperf * int_tofp(100);
|
|
core_pct = div64_u64(core_pct, sample->mperf);
|
|
|
|
sample->core_pct_busy = (int32_t)core_pct;
|
|
}
|
|
|
|
static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
|
|
{
|
|
u64 aperf, mperf;
|
|
unsigned long flags;
|
|
u64 tsc;
|
|
|
|
local_irq_save(flags);
|
|
rdmsrl(MSR_IA32_APERF, aperf);
|
|
rdmsrl(MSR_IA32_MPERF, mperf);
|
|
tsc = rdtsc();
|
|
if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
|
|
local_irq_restore(flags);
|
|
return false;
|
|
}
|
|
local_irq_restore(flags);
|
|
|
|
cpu->last_sample_time = cpu->sample.time;
|
|
cpu->sample.time = time;
|
|
cpu->sample.aperf = aperf;
|
|
cpu->sample.mperf = mperf;
|
|
cpu->sample.tsc = tsc;
|
|
cpu->sample.aperf -= cpu->prev_aperf;
|
|
cpu->sample.mperf -= cpu->prev_mperf;
|
|
cpu->sample.tsc -= cpu->prev_tsc;
|
|
|
|
cpu->prev_aperf = aperf;
|
|
cpu->prev_mperf = mperf;
|
|
cpu->prev_tsc = tsc;
|
|
/*
|
|
* First time this function is invoked in a given cycle, all of the
|
|
* previous sample data fields are equal to zero or stale and they must
|
|
* be populated with meaningful numbers for things to work, so assume
|
|
* that sample.time will always be reset before setting the utilization
|
|
* update hook and make the caller skip the sample then.
|
|
*/
|
|
return !!cpu->last_sample_time;
|
|
}
|
|
|
|
static inline int32_t get_avg_frequency(struct cpudata *cpu)
|
|
{
|
|
return div64_u64(cpu->pstate.max_pstate_physical * cpu->sample.aperf *
|
|
cpu->pstate.scaling, cpu->sample.mperf);
|
|
}
|
|
|
|
static inline int32_t get_avg_pstate(struct cpudata *cpu)
|
|
{
|
|
return div64_u64(cpu->pstate.max_pstate_physical * cpu->sample.aperf,
|
|
cpu->sample.mperf);
|
|
}
|
|
|
|
static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
|
|
{
|
|
struct sample *sample = &cpu->sample;
|
|
u64 cummulative_iowait, delta_iowait_us;
|
|
u64 delta_iowait_mperf;
|
|
u64 mperf, now;
|
|
int32_t cpu_load;
|
|
|
|
cummulative_iowait = get_cpu_iowait_time_us(cpu->cpu, &now);
|
|
|
|
/*
|
|
* Convert iowait time into number of IO cycles spent at max_freq.
|
|
* IO is considered as busy only for the cpu_load algorithm. For
|
|
* performance this is not needed since we always try to reach the
|
|
* maximum P-State, so we are already boosting the IOs.
|
|
*/
|
|
delta_iowait_us = cummulative_iowait - cpu->prev_cummulative_iowait;
|
|
delta_iowait_mperf = div64_u64(delta_iowait_us * cpu->pstate.scaling *
|
|
cpu->pstate.max_pstate, MSEC_PER_SEC);
|
|
|
|
mperf = cpu->sample.mperf + delta_iowait_mperf;
|
|
cpu->prev_cummulative_iowait = cummulative_iowait;
|
|
|
|
/*
|
|
* The load can be estimated as the ratio of the mperf counter
|
|
* running at a constant frequency during active periods
|
|
* (C0) and the time stamp counter running at the same frequency
|
|
* also during C-states.
|
|
*/
|
|
cpu_load = div64_u64(int_tofp(100) * mperf, sample->tsc);
|
|
cpu->sample.busy_scaled = cpu_load;
|
|
|
|
return get_avg_pstate(cpu) - pid_calc(&cpu->pid, cpu_load);
|
|
}
|
|
|
|
static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
|
|
{
|
|
int32_t core_busy, max_pstate, current_pstate, sample_ratio;
|
|
u64 duration_ns;
|
|
|
|
intel_pstate_calc_busy(cpu);
|
|
|
|
/*
|
|
* core_busy is the ratio of actual performance to max
|
|
* max_pstate is the max non turbo pstate available
|
|
* current_pstate was the pstate that was requested during
|
|
* the last sample period.
|
|
*
|
|
* We normalize core_busy, which was our actual percent
|
|
* performance to what we requested during the last sample
|
|
* period. The result will be a percentage of busy at a
|
|
* specified pstate.
|
|
*/
|
|
core_busy = cpu->sample.core_pct_busy;
|
|
max_pstate = cpu->pstate.max_pstate_physical;
|
|
current_pstate = cpu->pstate.current_pstate;
|
|
core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate));
|
|
|
|
/*
|
|
* Since our utilization update callback will not run unless we are
|
|
* in C0, check if the actual elapsed time is significantly greater (3x)
|
|
* than our sample interval. If it is, then we were idle for a long
|
|
* enough period of time to adjust our busyness.
|
|
*/
|
|
duration_ns = cpu->sample.time - cpu->last_sample_time;
|
|
if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
|
|
sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
|
|
core_busy = mul_fp(core_busy, sample_ratio);
|
|
} else {
|
|
sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
|
|
if (sample_ratio < int_tofp(1))
|
|
core_busy = 0;
|
|
}
|
|
|
|
cpu->sample.busy_scaled = core_busy;
|
|
return cpu->pstate.current_pstate - pid_calc(&cpu->pid, core_busy);
|
|
}
|
|
|
|
static inline void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
|
|
{
|
|
int max_perf, min_perf;
|
|
|
|
update_turbo_state();
|
|
|
|
intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
|
|
pstate = clamp_t(int, pstate, min_perf, max_perf);
|
|
if (pstate == cpu->pstate.current_pstate)
|
|
return;
|
|
|
|
intel_pstate_record_pstate(cpu, pstate);
|
|
wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
|
|
}
|
|
|
|
static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
|
|
{
|
|
int from, target_pstate;
|
|
struct sample *sample;
|
|
|
|
from = cpu->pstate.current_pstate;
|
|
|
|
target_pstate = pstate_funcs.get_target_pstate(cpu);
|
|
|
|
intel_pstate_update_pstate(cpu, target_pstate);
|
|
|
|
sample = &cpu->sample;
|
|
trace_pstate_sample(fp_toint(sample->core_pct_busy),
|
|
fp_toint(sample->busy_scaled),
|
|
from,
|
|
cpu->pstate.current_pstate,
|
|
sample->mperf,
|
|
sample->aperf,
|
|
sample->tsc,
|
|
get_avg_frequency(cpu));
|
|
}
|
|
|
|
static void intel_pstate_update_util(struct update_util_data *data, u64 time,
|
|
unsigned long util, unsigned long max)
|
|
{
|
|
struct cpudata *cpu = container_of(data, struct cpudata, update_util);
|
|
u64 delta_ns = time - cpu->sample.time;
|
|
|
|
if ((s64)delta_ns >= pid_params.sample_rate_ns) {
|
|
bool sample_taken = intel_pstate_sample(cpu, time);
|
|
|
|
if (sample_taken && !hwp_active)
|
|
intel_pstate_adjust_busy_pstate(cpu);
|
|
}
|
|
}
|
|
|
|
#define ICPU(model, policy) \
|
|
{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
|
|
(unsigned long)&policy }
|
|
|
|
static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
|
|
ICPU(0x2a, core_params),
|
|
ICPU(0x2d, core_params),
|
|
ICPU(0x37, silvermont_params),
|
|
ICPU(0x3a, core_params),
|
|
ICPU(0x3c, core_params),
|
|
ICPU(0x3d, core_params),
|
|
ICPU(0x3e, core_params),
|
|
ICPU(0x3f, core_params),
|
|
ICPU(0x45, core_params),
|
|
ICPU(0x46, core_params),
|
|
ICPU(0x47, core_params),
|
|
ICPU(0x4c, airmont_params),
|
|
ICPU(0x4e, core_params),
|
|
ICPU(0x4f, core_params),
|
|
ICPU(0x5e, core_params),
|
|
ICPU(0x56, core_params),
|
|
ICPU(0x57, knl_params),
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
|
|
|
|
static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = {
|
|
ICPU(0x56, core_params),
|
|
{}
|
|
};
|
|
|
|
static int intel_pstate_init_cpu(unsigned int cpunum)
|
|
{
|
|
struct cpudata *cpu;
|
|
|
|
if (!all_cpu_data[cpunum])
|
|
all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata),
|
|
GFP_KERNEL);
|
|
if (!all_cpu_data[cpunum])
|
|
return -ENOMEM;
|
|
|
|
cpu = all_cpu_data[cpunum];
|
|
|
|
cpu->cpu = cpunum;
|
|
|
|
if (hwp_active) {
|
|
intel_pstate_hwp_enable(cpu);
|
|
pid_params.sample_rate_ms = 50;
|
|
pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
|
|
}
|
|
|
|
intel_pstate_get_cpu_pstates(cpu);
|
|
|
|
intel_pstate_busy_pid_reset(cpu);
|
|
|
|
pr_debug("controlling: cpu %d\n", cpunum);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned int intel_pstate_get(unsigned int cpu_num)
|
|
{
|
|
struct sample *sample;
|
|
struct cpudata *cpu;
|
|
|
|
cpu = all_cpu_data[cpu_num];
|
|
if (!cpu)
|
|
return 0;
|
|
sample = &cpu->sample;
|
|
return get_avg_frequency(cpu);
|
|
}
|
|
|
|
static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
|
|
{
|
|
struct cpudata *cpu = all_cpu_data[cpu_num];
|
|
|
|
/* Prevent intel_pstate_update_util() from using stale data. */
|
|
cpu->sample.time = 0;
|
|
cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
|
|
intel_pstate_update_util);
|
|
}
|
|
|
|
static void intel_pstate_clear_update_util_hook(unsigned int cpu)
|
|
{
|
|
cpufreq_remove_update_util_hook(cpu);
|
|
synchronize_sched();
|
|
}
|
|
|
|
static void intel_pstate_set_performance_limits(struct perf_limits *limits)
|
|
{
|
|
limits->no_turbo = 0;
|
|
limits->turbo_disabled = 0;
|
|
limits->max_perf_pct = 100;
|
|
limits->max_perf = int_tofp(1);
|
|
limits->min_perf_pct = 100;
|
|
limits->min_perf = int_tofp(1);
|
|
limits->max_policy_pct = 100;
|
|
limits->max_sysfs_pct = 100;
|
|
limits->min_policy_pct = 0;
|
|
limits->min_sysfs_pct = 0;
|
|
}
|
|
|
|
static int intel_pstate_set_policy(struct cpufreq_policy *policy)
|
|
{
|
|
if (!policy->cpuinfo.max_freq)
|
|
return -ENODEV;
|
|
|
|
intel_pstate_clear_update_util_hook(policy->cpu);
|
|
|
|
if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
|
|
limits = &performance_limits;
|
|
if (policy->max >= policy->cpuinfo.max_freq) {
|
|
pr_debug("set performance\n");
|
|
intel_pstate_set_performance_limits(limits);
|
|
goto out;
|
|
}
|
|
} else {
|
|
pr_debug("set powersave\n");
|
|
limits = &powersave_limits;
|
|
}
|
|
|
|
limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
|
|
limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0 , 100);
|
|
limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
|
|
policy->cpuinfo.max_freq);
|
|
limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0 , 100);
|
|
|
|
/* Normalize user input to [min_policy_pct, max_policy_pct] */
|
|
limits->min_perf_pct = max(limits->min_policy_pct,
|
|
limits->min_sysfs_pct);
|
|
limits->min_perf_pct = min(limits->max_policy_pct,
|
|
limits->min_perf_pct);
|
|
limits->max_perf_pct = min(limits->max_policy_pct,
|
|
limits->max_sysfs_pct);
|
|
limits->max_perf_pct = max(limits->min_policy_pct,
|
|
limits->max_perf_pct);
|
|
limits->max_perf = round_up(limits->max_perf, FRAC_BITS);
|
|
|
|
/* Make sure min_perf_pct <= max_perf_pct */
|
|
limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
|
|
|
|
limits->min_perf = div_fp(limits->min_perf_pct, 100);
|
|
limits->max_perf = div_fp(limits->max_perf_pct, 100);
|
|
|
|
out:
|
|
intel_pstate_set_update_util_hook(policy->cpu);
|
|
|
|
if (hwp_active)
|
|
intel_pstate_hwp_set(policy->cpus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
|
|
{
|
|
cpufreq_verify_within_cpu_limits(policy);
|
|
|
|
if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
|
|
policy->policy != CPUFREQ_POLICY_PERFORMANCE)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
|
|
{
|
|
int cpu_num = policy->cpu;
|
|
struct cpudata *cpu = all_cpu_data[cpu_num];
|
|
|
|
pr_debug("CPU %d exiting\n", cpu_num);
|
|
|
|
intel_pstate_clear_update_util_hook(cpu_num);
|
|
|
|
if (hwp_active)
|
|
return;
|
|
|
|
intel_pstate_set_min_pstate(cpu);
|
|
}
|
|
|
|
static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
|
|
{
|
|
struct cpudata *cpu;
|
|
int rc;
|
|
|
|
rc = intel_pstate_init_cpu(policy->cpu);
|
|
if (rc)
|
|
return rc;
|
|
|
|
cpu = all_cpu_data[policy->cpu];
|
|
|
|
if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
|
|
policy->policy = CPUFREQ_POLICY_PERFORMANCE;
|
|
else
|
|
policy->policy = CPUFREQ_POLICY_POWERSAVE;
|
|
|
|
policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
|
|
policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
|
|
|
|
/* cpuinfo and default policy values */
|
|
policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
|
|
policy->cpuinfo.max_freq =
|
|
cpu->pstate.turbo_pstate * cpu->pstate.scaling;
|
|
intel_pstate_init_acpi_perf_limits(policy);
|
|
policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
|
|
cpumask_set_cpu(policy->cpu, policy->cpus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
|
|
{
|
|
intel_pstate_exit_perf_limits(policy);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct cpufreq_driver intel_pstate_driver = {
|
|
.flags = CPUFREQ_CONST_LOOPS,
|
|
.verify = intel_pstate_verify_policy,
|
|
.setpolicy = intel_pstate_set_policy,
|
|
.get = intel_pstate_get,
|
|
.init = intel_pstate_cpu_init,
|
|
.exit = intel_pstate_cpu_exit,
|
|
.stop_cpu = intel_pstate_stop_cpu,
|
|
.name = "intel_pstate",
|
|
};
|
|
|
|
static int __initdata no_load;
|
|
static int __initdata no_hwp;
|
|
static int __initdata hwp_only;
|
|
static unsigned int force_load;
|
|
|
|
static int intel_pstate_msrs_not_valid(void)
|
|
{
|
|
if (!pstate_funcs.get_max() ||
|
|
!pstate_funcs.get_min() ||
|
|
!pstate_funcs.get_turbo())
|
|
return -ENODEV;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void copy_pid_params(struct pstate_adjust_policy *policy)
|
|
{
|
|
pid_params.sample_rate_ms = policy->sample_rate_ms;
|
|
pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
|
|
pid_params.p_gain_pct = policy->p_gain_pct;
|
|
pid_params.i_gain_pct = policy->i_gain_pct;
|
|
pid_params.d_gain_pct = policy->d_gain_pct;
|
|
pid_params.deadband = policy->deadband;
|
|
pid_params.setpoint = policy->setpoint;
|
|
}
|
|
|
|
static void copy_cpu_funcs(struct pstate_funcs *funcs)
|
|
{
|
|
pstate_funcs.get_max = funcs->get_max;
|
|
pstate_funcs.get_max_physical = funcs->get_max_physical;
|
|
pstate_funcs.get_min = funcs->get_min;
|
|
pstate_funcs.get_turbo = funcs->get_turbo;
|
|
pstate_funcs.get_scaling = funcs->get_scaling;
|
|
pstate_funcs.get_val = funcs->get_val;
|
|
pstate_funcs.get_vid = funcs->get_vid;
|
|
pstate_funcs.get_target_pstate = funcs->get_target_pstate;
|
|
|
|
}
|
|
|
|
#ifdef CONFIG_ACPI
|
|
|
|
static bool intel_pstate_no_acpi_pss(void)
|
|
{
|
|
int i;
|
|
|
|
for_each_possible_cpu(i) {
|
|
acpi_status status;
|
|
union acpi_object *pss;
|
|
struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
|
|
struct acpi_processor *pr = per_cpu(processors, i);
|
|
|
|
if (!pr)
|
|
continue;
|
|
|
|
status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
|
|
if (ACPI_FAILURE(status))
|
|
continue;
|
|
|
|
pss = buffer.pointer;
|
|
if (pss && pss->type == ACPI_TYPE_PACKAGE) {
|
|
kfree(pss);
|
|
return false;
|
|
}
|
|
|
|
kfree(pss);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool intel_pstate_has_acpi_ppc(void)
|
|
{
|
|
int i;
|
|
|
|
for_each_possible_cpu(i) {
|
|
struct acpi_processor *pr = per_cpu(processors, i);
|
|
|
|
if (!pr)
|
|
continue;
|
|
if (acpi_has_method(pr->handle, "_PPC"))
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
enum {
|
|
PSS,
|
|
PPC,
|
|
};
|
|
|
|
struct hw_vendor_info {
|
|
u16 valid;
|
|
char oem_id[ACPI_OEM_ID_SIZE];
|
|
char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
|
|
int oem_pwr_table;
|
|
};
|
|
|
|
/* Hardware vendor-specific info that has its own power management modes */
|
|
static struct hw_vendor_info vendor_info[] = {
|
|
{1, "HP ", "ProLiant", PSS},
|
|
{1, "ORACLE", "X4-2 ", PPC},
|
|
{1, "ORACLE", "X4-2L ", PPC},
|
|
{1, "ORACLE", "X4-2B ", PPC},
|
|
{1, "ORACLE", "X3-2 ", PPC},
|
|
{1, "ORACLE", "X3-2L ", PPC},
|
|
{1, "ORACLE", "X3-2B ", PPC},
|
|
{1, "ORACLE", "X4470M2 ", PPC},
|
|
{1, "ORACLE", "X4270M3 ", PPC},
|
|
{1, "ORACLE", "X4270M2 ", PPC},
|
|
{1, "ORACLE", "X4170M2 ", PPC},
|
|
{1, "ORACLE", "X4170 M3", PPC},
|
|
{1, "ORACLE", "X4275 M3", PPC},
|
|
{1, "ORACLE", "X6-2 ", PPC},
|
|
{1, "ORACLE", "Sudbury ", PPC},
|
|
{0, "", ""},
|
|
};
|
|
|
|
static bool intel_pstate_platform_pwr_mgmt_exists(void)
|
|
{
|
|
struct acpi_table_header hdr;
|
|
struct hw_vendor_info *v_info;
|
|
const struct x86_cpu_id *id;
|
|
u64 misc_pwr;
|
|
|
|
id = x86_match_cpu(intel_pstate_cpu_oob_ids);
|
|
if (id) {
|
|
rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
|
|
if ( misc_pwr & (1 << 8))
|
|
return true;
|
|
}
|
|
|
|
if (acpi_disabled ||
|
|
ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
|
|
return false;
|
|
|
|
for (v_info = vendor_info; v_info->valid; v_info++) {
|
|
if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
|
|
!strncmp(hdr.oem_table_id, v_info->oem_table_id,
|
|
ACPI_OEM_TABLE_ID_SIZE))
|
|
switch (v_info->oem_pwr_table) {
|
|
case PSS:
|
|
return intel_pstate_no_acpi_pss();
|
|
case PPC:
|
|
return intel_pstate_has_acpi_ppc() &&
|
|
(!force_load);
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
#else /* CONFIG_ACPI not enabled */
|
|
static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
|
|
static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
|
|
#endif /* CONFIG_ACPI */
|
|
|
|
static const struct x86_cpu_id hwp_support_ids[] __initconst = {
|
|
{ X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
|
|
{}
|
|
};
|
|
|
|
static int __init intel_pstate_init(void)
|
|
{
|
|
int cpu, rc = 0;
|
|
const struct x86_cpu_id *id;
|
|
struct cpu_defaults *cpu_def;
|
|
|
|
if (no_load)
|
|
return -ENODEV;
|
|
|
|
if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
|
|
copy_cpu_funcs(&core_params.funcs);
|
|
hwp_active++;
|
|
goto hwp_cpu_matched;
|
|
}
|
|
|
|
id = x86_match_cpu(intel_pstate_cpu_ids);
|
|
if (!id)
|
|
return -ENODEV;
|
|
|
|
cpu_def = (struct cpu_defaults *)id->driver_data;
|
|
|
|
copy_pid_params(&cpu_def->pid_policy);
|
|
copy_cpu_funcs(&cpu_def->funcs);
|
|
|
|
if (intel_pstate_msrs_not_valid())
|
|
return -ENODEV;
|
|
|
|
hwp_cpu_matched:
|
|
/*
|
|
* The Intel pstate driver will be ignored if the platform
|
|
* firmware has its own power management modes.
|
|
*/
|
|
if (intel_pstate_platform_pwr_mgmt_exists())
|
|
return -ENODEV;
|
|
|
|
pr_info("Intel P-state driver initializing\n");
|
|
|
|
all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
|
|
if (!all_cpu_data)
|
|
return -ENOMEM;
|
|
|
|
if (!hwp_active && hwp_only)
|
|
goto out;
|
|
|
|
rc = cpufreq_register_driver(&intel_pstate_driver);
|
|
if (rc)
|
|
goto out;
|
|
|
|
intel_pstate_debug_expose_params();
|
|
intel_pstate_sysfs_expose_params();
|
|
|
|
if (hwp_active)
|
|
pr_info("HWP enabled\n");
|
|
|
|
return rc;
|
|
out:
|
|
get_online_cpus();
|
|
for_each_online_cpu(cpu) {
|
|
if (all_cpu_data[cpu]) {
|
|
intel_pstate_clear_update_util_hook(cpu);
|
|
kfree(all_cpu_data[cpu]);
|
|
}
|
|
}
|
|
|
|
put_online_cpus();
|
|
vfree(all_cpu_data);
|
|
return -ENODEV;
|
|
}
|
|
device_initcall(intel_pstate_init);
|
|
|
|
static int __init intel_pstate_setup(char *str)
|
|
{
|
|
if (!str)
|
|
return -EINVAL;
|
|
|
|
if (!strcmp(str, "disable"))
|
|
no_load = 1;
|
|
if (!strcmp(str, "no_hwp")) {
|
|
pr_info("HWP disabled\n");
|
|
no_hwp = 1;
|
|
}
|
|
if (!strcmp(str, "force"))
|
|
force_load = 1;
|
|
if (!strcmp(str, "hwp_only"))
|
|
hwp_only = 1;
|
|
|
|
#ifdef CONFIG_ACPI
|
|
if (!strcmp(str, "support_acpi_ppc"))
|
|
acpi_ppc = true;
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
early_param("intel_pstate", intel_pstate_setup);
|
|
|
|
MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
|
|
MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
|
|
MODULE_LICENSE("GPL");
|