linux/arch/arm/mach-tegra
Joseph Lo 95872f427e ARM: tegra: add common LP1 suspend support
The LP1 suspending mode on Tegra means CPU rail off, devices and PLLs are
clock gated and SDRAM in self-refresh mode. That means the low level LP1
suspending and resuming code couldn't be run on DRAM and the CPU must
switch to the always on clock domain (a.k.a. CLK_M 12MHz oscillator). And
the system clock (SCLK) would be switched to CLK_S, a 32KHz oscillator.
The LP1 low level handling code need to be moved to IRAM area first. And
marking the LP1 mask for indicating the Tegra device is in LP1. The CPU
power timer needs to be re-calculated based on 32KHz that was originally
based on PCLK.

When resuming from LP1, the LP1 reset handler will resume PLLs and then
put DRAM to normal mode. Then jumping to the "tegra_resume" that will
restore full context before back to kernel. The "tegra_resume" handler
was expected to be found in PMC_SCRATCH41 register.

This is common LP1 procedures for Tegra, so we do these jobs mainly in
this patch:
* moving LP1 low level handling code to IRAM
* marking LP1 mask
* copying the physical address of "tegra_resume" to PMC_SCRATCH41
* re-calculate the CPU power timer based on 32KHz

Signed-off-by: Joseph Lo <josephl@nvidia.com>
[swarren, replaced IRAM_CODE macro with IO_ADDRESS(TEGRA_IRAM_CODE_AREA)]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 13:29:24 -06:00
..
Kconfig ARM: tegra: unify Tegra's Kconfig a bit more 2013-08-08 11:45:13 -06:00
Makefile ARM: tegra114: add CPU hotplug support 2013-05-22 15:19:22 -06:00
apbio.c ARM: tegra: Make variables static 2013-01-28 10:21:28 -07:00
apbio.h ARM: tegra: apbio access using dma for tegra20 only 2012-07-06 11:48:56 -06:00
board-harmony-pcie.c Merge branch 'for-linus' of git://git.linaro.org/people/rmk/linux-arm 2013-05-03 09:13:19 -07:00
board-paz00.c Merge branch 'multiplatform/platform-data' into next/multiplatform 2012-09-22 01:07:21 -07:00
board-paz00.h ARM: tegra: remove board (but not DT) support for Paz00 2012-09-14 11:31:36 -06:00
board.h reboot: arm: change reboot_mode to use enum reboot_mode 2013-07-09 10:33:29 -07:00
common.c reboot: arm: change reboot_mode to use enum reboot_mode 2013-07-09 10:33:29 -07:00
common.h Revert "ARM: tegra: add cpu_disable for hotplug" 2013-07-19 10:00:37 -06:00
cpuidle-tegra20.c ARM: tegra: don't pass CPU ID to tegra_{set,clear}_cpu_in_lp2 2013-06-05 11:44:58 -06:00
cpuidle-tegra30.c ARM: tegra: don't pass CPU ID to tegra_{set,clear}_cpu_in_lp2 2013-06-05 11:44:58 -06:00
cpuidle-tegra114.c ARM: tegra114: cpuidle: add powered-down state 2013-07-19 10:07:14 -06:00
cpuidle.c ARM: tegra: cpuidle: using IS_ENABLED for multi SoCs management in init func 2013-06-05 11:44:54 -06:00
cpuidle.h ARM: tegra: cpuidle: using IS_ENABLED for multi SoCs management in init func 2013-06-05 11:44:54 -06:00
flowctrl.c ARM: tegra: flowctrl: add support for cpu_suspend_enter/exit 2013-07-19 10:08:08 -06:00
flowctrl.h ARM: tegra: shut off the CPU rail when the last CPU in suspend 2013-07-19 10:08:07 -06:00
fuse.c ARM: tegra: add speedo-based process id for Tegra114 2013-03-19 11:52:06 -06:00
fuse.h ARM: tegra: add an assembly marco to check Tegra SoC ID 2013-05-22 15:19:21 -06:00
gpio-names.h [ARM] tegra: add GPIO support 2010-08-05 14:57:02 -07:00
headsmp.S ARM: tegra: do v7_invalidate_l1 only when CPU is Cortex-A9 2013-07-19 10:08:04 -06:00
hotplug.c ARM: tegra: add a flag for tegra_disable_clean_inv_dcache to do LoUIS or ALL 2013-07-19 10:08:05 -06:00
io.c ARM: tegra: don't include iomap.h from debug-macro.S 2012-11-16 12:22:17 -07:00
iomap.h ARM: tegra: add common resume handling code for LP1 resuming 2013-08-12 12:22:38 -06:00
irammap.h ARM: tegra: decouple uncompress.h and debug-macro.S 2012-11-16 12:22:17 -07:00
irq.c ARM: tegra114: Reprogram GIC CPU interface to bypass IRQ on CPU PM entry 2013-07-19 10:07:14 -06:00
irq.h ARM: tegra: irq: add wake up handling 2013-04-03 14:31:32 -06:00
pcie.c ARM: tegra: move <mach/powergate.h> to <linux/tegra-powergate.h> 2013-03-29 18:10:22 -06:00
platsmp.c Revert "ARM: tegra: add cpu_disable for hotplug" 2013-07-19 10:00:37 -06:00
pm.c ARM: tegra: add common LP1 suspend support 2013-08-12 13:29:24 -06:00
pm.h ARM: tegra: add common LP1 suspend support 2013-08-12 13:29:24 -06:00
pmc.c ARM: tegra: add common LP1 suspend support 2013-08-12 13:29:24 -06:00
pmc.h ARM: tegra: add common LP1 suspend support 2013-08-12 13:29:24 -06:00
powergate.c ARM: arm-soc multiplatform updates for 3.10 2013-05-02 09:38:16 -07:00
reset-handler.S ARM: tegra: add common resume handling code for LP1 resuming 2013-08-12 12:22:38 -06:00
reset.c ARM: tegra: add common resume handling code for LP1 resuming 2013-08-12 12:22:38 -06:00
reset.h ARM: tegra: add common LP1 suspend support 2013-08-12 13:29:24 -06:00
sleep-tegra20.S ARM: tegra: add a flag for tegra_disable_clean_inv_dcache to do LoUIS or ALL 2013-07-19 10:08:05 -06:00
sleep-tegra30.S ARM: tegra: add low level code for Tegra114 cluster power down 2013-07-19 10:08:06 -06:00
sleep.S ARM: tegra: set up the correct L2 data RAM latency for Cortex-A15 2013-07-19 10:08:05 -06:00
sleep.h ARM: tegra: add a flag for tegra_disable_clean_inv_dcache to do LoUIS or ALL 2013-07-19 10:08:05 -06:00
tegra.c ARM: arm-soc driver changes for 3.10 2013-05-04 12:31:18 -07:00
tegra2_emc.c ARM: tegra: core SoC support enhancements 2013-06-14 18:11:31 -07:00
tegra2_emc.h ARM: tegra: emc: convert tegra2_emc to a platform driver 2012-02-06 18:24:59 -08:00
tegra20_speedo.c ARM: tegra: Add speedo-based process identification 2012-11-15 14:34:20 -07:00
tegra30_speedo.c ARM: tegra: Tegra30 speedo-based process identification 2012-11-15 14:36:59 -07:00
tegra114_speedo.c ARM: tegra: add speedo-based process id for Tegra114 2013-03-19 11:52:06 -06:00