mirror of https://gitee.com/openkylin/linux.git
841 lines
18 KiB
C
841 lines
18 KiB
C
/*
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Driver for Zarlink VP310/MT312/ZL10313 Satellite Channel Decoder
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Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
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Copyright (C) 2008 Matthias Schwarzott <zzam@gentoo.org>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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References:
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http://products.zarlink.com/product_profiles/MT312.htm
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http://products.zarlink.com/product_profiles/SL1935.htm
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*/
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include "dvb_frontend.h"
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#include "mt312_priv.h"
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#include "mt312.h"
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struct mt312_state {
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struct i2c_adapter *i2c;
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/* configuration settings */
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const struct mt312_config *config;
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struct dvb_frontend frontend;
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u8 id;
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unsigned long xtal;
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u8 freq_mult;
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};
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static int debug;
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#define dprintk(args...) \
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do { \
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if (debug) \
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printk(KERN_DEBUG "mt312: " args); \
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} while (0)
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#define MT312_PLL_CLK 10000000UL /* 10 MHz */
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#define MT312_PLL_CLK_10_111 10111000UL /* 10.111 MHz */
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static int mt312_read(struct mt312_state *state, const enum mt312_reg_addr reg,
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u8 *buf, const size_t count)
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{
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int ret;
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struct i2c_msg msg[2];
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u8 regbuf[1] = { reg };
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msg[0].addr = state->config->demod_address;
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msg[0].flags = 0;
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msg[0].buf = regbuf;
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msg[0].len = 1;
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msg[1].addr = state->config->demod_address;
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msg[1].flags = I2C_M_RD;
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msg[1].buf = buf;
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msg[1].len = count;
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2) {
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printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret);
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return -EREMOTEIO;
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}
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if (debug) {
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int i;
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dprintk("R(%d):", reg & 0x7f);
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for (i = 0; i < count; i++)
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printk(KERN_CONT " %02x", buf[i]);
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printk("\n");
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}
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return 0;
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}
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static int mt312_write(struct mt312_state *state, const enum mt312_reg_addr reg,
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const u8 *src, const size_t count)
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{
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int ret;
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u8 buf[count + 1];
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struct i2c_msg msg;
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if (debug) {
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int i;
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dprintk("W(%d):", reg & 0x7f);
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for (i = 0; i < count; i++)
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printk(KERN_CONT " %02x", src[i]);
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printk("\n");
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}
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buf[0] = reg;
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memcpy(&buf[1], src, count);
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msg.addr = state->config->demod_address;
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msg.flags = 0;
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msg.buf = buf;
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msg.len = count + 1;
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ret = i2c_transfer(state->i2c, &msg, 1);
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if (ret != 1) {
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dprintk("%s: ret == %d\n", __func__, ret);
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return -EREMOTEIO;
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}
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return 0;
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}
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static inline int mt312_readreg(struct mt312_state *state,
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const enum mt312_reg_addr reg, u8 *val)
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{
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return mt312_read(state, reg, val, 1);
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}
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static inline int mt312_writereg(struct mt312_state *state,
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const enum mt312_reg_addr reg, const u8 val)
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{
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return mt312_write(state, reg, &val, 1);
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}
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static inline u32 mt312_div(u32 a, u32 b)
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{
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return (a + (b / 2)) / b;
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}
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static int mt312_reset(struct mt312_state *state, const u8 full)
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{
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return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
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}
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static int mt312_get_inversion(struct mt312_state *state,
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fe_spectral_inversion_t *i)
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{
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int ret;
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u8 vit_mode;
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ret = mt312_readreg(state, VIT_MODE, &vit_mode);
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if (ret < 0)
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return ret;
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if (vit_mode & 0x80) /* auto inversion was used */
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*i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
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return 0;
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}
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static int mt312_get_symbol_rate(struct mt312_state *state, u32 *sr)
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{
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int ret;
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u8 sym_rate_h;
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u8 dec_ratio;
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u16 sym_rat_op;
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u16 monitor;
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u8 buf[2];
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ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
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if (ret < 0)
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return ret;
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if (sym_rate_h & 0x80) {
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/* symbol rate search was used */
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ret = mt312_writereg(state, MON_CTRL, 0x03);
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if (ret < 0)
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return ret;
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ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
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if (ret < 0)
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return ret;
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monitor = (buf[0] << 8) | buf[1];
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dprintk("sr(auto) = %u\n",
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mt312_div(monitor * 15625, 4));
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} else {
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ret = mt312_writereg(state, MON_CTRL, 0x05);
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if (ret < 0)
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return ret;
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ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
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if (ret < 0)
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return ret;
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dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
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ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
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if (ret < 0)
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return ret;
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sym_rat_op = (buf[0] << 8) | buf[1];
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dprintk("sym_rat_op=%d dec_ratio=%d\n",
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sym_rat_op, dec_ratio);
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dprintk("*sr(manual) = %lu\n",
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(((state->xtal * 8192) / (sym_rat_op + 8192)) *
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2) - dec_ratio);
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}
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return 0;
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}
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static int mt312_get_code_rate(struct mt312_state *state, fe_code_rate_t *cr)
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{
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const fe_code_rate_t fec_tab[8] =
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{ FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
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FEC_AUTO, FEC_AUTO };
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int ret;
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u8 fec_status;
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ret = mt312_readreg(state, FEC_STATUS, &fec_status);
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if (ret < 0)
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return ret;
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*cr = fec_tab[(fec_status >> 4) & 0x07];
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return 0;
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}
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static int mt312_initfe(struct dvb_frontend *fe)
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{
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struct mt312_state *state = fe->demodulator_priv;
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int ret;
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u8 buf[2];
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/* wake up */
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ret = mt312_writereg(state, CONFIG,
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(state->freq_mult == 6 ? 0x88 : 0x8c));
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if (ret < 0)
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return ret;
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/* wait at least 150 usec */
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udelay(150);
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/* full reset */
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ret = mt312_reset(state, 1);
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if (ret < 0)
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return ret;
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/* Per datasheet, write correct values. 09/28/03 ACCJr.
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* If we don't do this, we won't get FE_HAS_VITERBI in the VP310. */
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{
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u8 buf_def[8] = { 0x14, 0x12, 0x03, 0x02,
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0x01, 0x00, 0x00, 0x00 };
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ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
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if (ret < 0)
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return ret;
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}
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switch (state->id) {
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case ID_ZL10313:
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/* enable ADC */
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ret = mt312_writereg(state, GPP_CTRL, 0x80);
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if (ret < 0)
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return ret;
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/* configure ZL10313 for optimal ADC performance */
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buf[0] = 0x80;
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buf[1] = 0xB0;
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ret = mt312_write(state, HW_CTRL, buf, 2);
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if (ret < 0)
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return ret;
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/* enable MPEG output and ADCs */
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ret = mt312_writereg(state, HW_CTRL, 0x00);
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if (ret < 0)
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return ret;
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ret = mt312_writereg(state, MPEG_CTRL, 0x00);
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if (ret < 0)
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return ret;
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break;
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}
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/* SYS_CLK */
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buf[0] = mt312_div(state->xtal * state->freq_mult * 2, 1000000);
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/* DISEQC_RATIO */
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buf[1] = mt312_div(state->xtal, 22000 * 4);
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ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
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if (ret < 0)
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return ret;
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ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
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if (ret < 0)
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return ret;
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/* different MOCLK polarity */
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switch (state->id) {
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case ID_ZL10313:
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buf[0] = 0x33;
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break;
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default:
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buf[0] = 0x53;
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break;
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}
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ret = mt312_writereg(state, OP_CTRL, buf[0]);
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if (ret < 0)
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return ret;
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/* TS_SW_LIM */
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buf[0] = 0x8c;
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buf[1] = 0x98;
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ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
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if (ret < 0)
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return ret;
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ret = mt312_writereg(state, CS_SW_LIM, 0x69);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int mt312_send_master_cmd(struct dvb_frontend *fe,
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struct dvb_diseqc_master_cmd *c)
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{
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struct mt312_state *state = fe->demodulator_priv;
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int ret;
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u8 diseqc_mode;
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if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
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return -EINVAL;
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ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
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if (ret < 0)
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return ret;
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ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
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if (ret < 0)
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return ret;
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ret = mt312_writereg(state, DISEQC_MODE,
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(diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
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| 0x04);
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if (ret < 0)
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return ret;
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/* is there a better way to wait for message to be transmitted */
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msleep(100);
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/* set DISEQC_MODE[2:0] to zero if a return message is expected */
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if (c->msg[0] & 0x02) {
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ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int mt312_send_burst(struct dvb_frontend *fe, const fe_sec_mini_cmd_t c)
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{
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struct mt312_state *state = fe->demodulator_priv;
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const u8 mini_tab[2] = { 0x02, 0x03 };
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int ret;
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u8 diseqc_mode;
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if (c > SEC_MINI_B)
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return -EINVAL;
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ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
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if (ret < 0)
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return ret;
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ret = mt312_writereg(state, DISEQC_MODE,
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(diseqc_mode & 0x40) | mini_tab[c]);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int mt312_set_tone(struct dvb_frontend *fe, const fe_sec_tone_mode_t t)
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{
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struct mt312_state *state = fe->demodulator_priv;
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const u8 tone_tab[2] = { 0x01, 0x00 };
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int ret;
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u8 diseqc_mode;
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if (t > SEC_TONE_OFF)
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return -EINVAL;
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ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
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if (ret < 0)
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return ret;
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ret = mt312_writereg(state, DISEQC_MODE,
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(diseqc_mode & 0x40) | tone_tab[t]);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int mt312_set_voltage(struct dvb_frontend *fe, const fe_sec_voltage_t v)
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{
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struct mt312_state *state = fe->demodulator_priv;
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const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
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u8 val;
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if (v > SEC_VOLTAGE_OFF)
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return -EINVAL;
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val = volt_tab[v];
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if (state->config->voltage_inverted)
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val ^= 0x40;
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return mt312_writereg(state, DISEQC_MODE, val);
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}
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static int mt312_read_status(struct dvb_frontend *fe, fe_status_t *s)
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{
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struct mt312_state *state = fe->demodulator_priv;
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int ret;
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u8 status[3];
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*s = 0;
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ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
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if (ret < 0)
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return ret;
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dprintk("QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x,"
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" FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]);
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if (status[0] & 0xc0)
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*s |= FE_HAS_SIGNAL; /* signal noise ratio */
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if (status[0] & 0x04)
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*s |= FE_HAS_CARRIER; /* qpsk carrier lock */
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if (status[2] & 0x02)
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*s |= FE_HAS_VITERBI; /* viterbi lock */
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if (status[2] & 0x04)
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*s |= FE_HAS_SYNC; /* byte align lock */
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if (status[0] & 0x01)
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*s |= FE_HAS_LOCK; /* qpsk lock */
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return 0;
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}
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static int mt312_read_ber(struct dvb_frontend *fe, u32 *ber)
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{
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struct mt312_state *state = fe->demodulator_priv;
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int ret;
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u8 buf[3];
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ret = mt312_read(state, RS_BERCNT_H, buf, 3);
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if (ret < 0)
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return ret;
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*ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
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return 0;
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}
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static int mt312_read_signal_strength(struct dvb_frontend *fe,
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u16 *signal_strength)
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{
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struct mt312_state *state = fe->demodulator_priv;
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int ret;
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u8 buf[3];
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u16 agc;
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s16 err_db;
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ret = mt312_read(state, AGC_H, buf, sizeof(buf));
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if (ret < 0)
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return ret;
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agc = (buf[0] << 6) | (buf[1] >> 2);
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err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
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*signal_strength = agc;
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dprintk("agc=%08x err_db=%hd\n", agc, err_db);
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return 0;
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}
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static int mt312_read_snr(struct dvb_frontend *fe, u16 *snr)
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{
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struct mt312_state *state = fe->demodulator_priv;
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int ret;
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u8 buf[2];
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ret = mt312_read(state, M_SNR_H, buf, sizeof(buf));
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if (ret < 0)
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return ret;
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*snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
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return 0;
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}
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static int mt312_read_ucblocks(struct dvb_frontend *fe, u32 *ubc)
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{
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struct mt312_state *state = fe->demodulator_priv;
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int ret;
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u8 buf[2];
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ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf));
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if (ret < 0)
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return ret;
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*ubc = (buf[0] << 8) | buf[1];
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return 0;
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}
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static int mt312_set_frontend(struct dvb_frontend *fe,
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struct dvb_frontend_parameters *p)
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{
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|
struct mt312_state *state = fe->demodulator_priv;
|
|
int ret;
|
|
u8 buf[5], config_val;
|
|
u16 sr;
|
|
|
|
const u8 fec_tab[10] =
|
|
{ 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
|
|
const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
|
|
|
|
dprintk("%s: Freq %d\n", __func__, p->frequency);
|
|
|
|
if ((p->frequency < fe->ops.info.frequency_min)
|
|
|| (p->frequency > fe->ops.info.frequency_max))
|
|
return -EINVAL;
|
|
|
|
if ((p->inversion < INVERSION_OFF)
|
|
|| (p->inversion > INVERSION_ON))
|
|
return -EINVAL;
|
|
|
|
if ((p->u.qpsk.symbol_rate < fe->ops.info.symbol_rate_min)
|
|
|| (p->u.qpsk.symbol_rate > fe->ops.info.symbol_rate_max))
|
|
return -EINVAL;
|
|
|
|
if ((p->u.qpsk.fec_inner < FEC_NONE)
|
|
|| (p->u.qpsk.fec_inner > FEC_AUTO))
|
|
return -EINVAL;
|
|
|
|
if ((p->u.qpsk.fec_inner == FEC_4_5)
|
|
|| (p->u.qpsk.fec_inner == FEC_8_9))
|
|
return -EINVAL;
|
|
|
|
switch (state->id) {
|
|
case ID_VP310:
|
|
/* For now we will do this only for the VP310.
|
|
* It should be better for the mt312 as well,
|
|
* but tuning will be slower. ACCJr 09/29/03
|
|
*/
|
|
ret = mt312_readreg(state, CONFIG, &config_val);
|
|
if (ret < 0)
|
|
return ret;
|
|
if (p->u.qpsk.symbol_rate >= 30000000) {
|
|
/* Note that 30MS/s should use 90MHz */
|
|
if (state->freq_mult == 6) {
|
|
/* We are running 60MHz */
|
|
state->freq_mult = 9;
|
|
ret = mt312_initfe(fe);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
} else {
|
|
if (state->freq_mult == 9) {
|
|
/* We are running 90MHz */
|
|
state->freq_mult = 6;
|
|
ret = mt312_initfe(fe);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case ID_MT312:
|
|
case ID_ZL10313:
|
|
break;
|
|
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (fe->ops.tuner_ops.set_params) {
|
|
fe->ops.tuner_ops.set_params(fe, p);
|
|
if (fe->ops.i2c_gate_ctrl)
|
|
fe->ops.i2c_gate_ctrl(fe, 0);
|
|
}
|
|
|
|
/* sr = (u16)(sr * 256.0 / 1000000.0) */
|
|
sr = mt312_div(p->u.qpsk.symbol_rate * 4, 15625);
|
|
|
|
/* SYM_RATE */
|
|
buf[0] = (sr >> 8) & 0x3f;
|
|
buf[1] = (sr >> 0) & 0xff;
|
|
|
|
/* VIT_MODE */
|
|
buf[2] = inv_tab[p->inversion] | fec_tab[p->u.qpsk.fec_inner];
|
|
|
|
/* QPSK_CTRL */
|
|
buf[3] = 0x40; /* swap I and Q before QPSK demodulation */
|
|
|
|
if (p->u.qpsk.symbol_rate < 10000000)
|
|
buf[3] |= 0x04; /* use afc mode */
|
|
|
|
/* GO */
|
|
buf[4] = 0x01;
|
|
|
|
ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
mt312_reset(state, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mt312_get_frontend(struct dvb_frontend *fe,
|
|
struct dvb_frontend_parameters *p)
|
|
{
|
|
struct mt312_state *state = fe->demodulator_priv;
|
|
int ret;
|
|
|
|
ret = mt312_get_inversion(state, &p->inversion);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = mt312_get_symbol_rate(state, &p->u.qpsk.symbol_rate);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = mt312_get_code_rate(state, &p->u.qpsk.fec_inner);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mt312_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
|
|
{
|
|
struct mt312_state *state = fe->demodulator_priv;
|
|
|
|
u8 val = 0x00;
|
|
int ret;
|
|
|
|
switch (state->id) {
|
|
case ID_ZL10313:
|
|
ret = mt312_readreg(state, GPP_CTRL, &val);
|
|
if (ret < 0)
|
|
goto error;
|
|
|
|
/* preserve this bit to not accidently shutdown ADC */
|
|
val &= 0x80;
|
|
break;
|
|
}
|
|
|
|
if (enable)
|
|
val |= 0x40;
|
|
else
|
|
val &= ~0x40;
|
|
|
|
ret = mt312_writereg(state, GPP_CTRL, val);
|
|
|
|
error:
|
|
return ret;
|
|
}
|
|
|
|
static int mt312_sleep(struct dvb_frontend *fe)
|
|
{
|
|
struct mt312_state *state = fe->demodulator_priv;
|
|
int ret;
|
|
u8 config;
|
|
|
|
/* reset all registers to defaults */
|
|
ret = mt312_reset(state, 1);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (state->id == ID_ZL10313) {
|
|
/* reset ADC */
|
|
ret = mt312_writereg(state, GPP_CTRL, 0x00);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* full shutdown of ADCs, mpeg bus tristated */
|
|
ret = mt312_writereg(state, HW_CTRL, 0x0d);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
ret = mt312_readreg(state, CONFIG, &config);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
/* enter standby */
|
|
ret = mt312_writereg(state, CONFIG, config & 0x7f);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mt312_get_tune_settings(struct dvb_frontend *fe,
|
|
struct dvb_frontend_tune_settings *fesettings)
|
|
{
|
|
fesettings->min_delay_ms = 50;
|
|
fesettings->step_size = 0;
|
|
fesettings->max_drift = 0;
|
|
return 0;
|
|
}
|
|
|
|
static void mt312_release(struct dvb_frontend *fe)
|
|
{
|
|
struct mt312_state *state = fe->demodulator_priv;
|
|
kfree(state);
|
|
}
|
|
|
|
#define MT312_SYS_CLK 90000000UL /* 90 MHz */
|
|
static struct dvb_frontend_ops mt312_ops = {
|
|
|
|
.info = {
|
|
.name = "Zarlink ???? DVB-S",
|
|
.type = FE_QPSK,
|
|
.frequency_min = 950000,
|
|
.frequency_max = 2150000,
|
|
/* FIXME: adjust freq to real used xtal */
|
|
.frequency_stepsize = (MT312_PLL_CLK / 1000) / 128,
|
|
.symbol_rate_min = MT312_SYS_CLK / 128, /* FIXME as above */
|
|
.symbol_rate_max = MT312_SYS_CLK / 2,
|
|
.caps =
|
|
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
|
|
FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
|
|
FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
|
|
FE_CAN_RECOVER
|
|
},
|
|
|
|
.release = mt312_release,
|
|
|
|
.init = mt312_initfe,
|
|
.sleep = mt312_sleep,
|
|
.i2c_gate_ctrl = mt312_i2c_gate_ctrl,
|
|
|
|
.set_frontend = mt312_set_frontend,
|
|
.get_frontend = mt312_get_frontend,
|
|
.get_tune_settings = mt312_get_tune_settings,
|
|
|
|
.read_status = mt312_read_status,
|
|
.read_ber = mt312_read_ber,
|
|
.read_signal_strength = mt312_read_signal_strength,
|
|
.read_snr = mt312_read_snr,
|
|
.read_ucblocks = mt312_read_ucblocks,
|
|
|
|
.diseqc_send_master_cmd = mt312_send_master_cmd,
|
|
.diseqc_send_burst = mt312_send_burst,
|
|
.set_tone = mt312_set_tone,
|
|
.set_voltage = mt312_set_voltage,
|
|
};
|
|
|
|
struct dvb_frontend *mt312_attach(const struct mt312_config *config,
|
|
struct i2c_adapter *i2c)
|
|
{
|
|
struct mt312_state *state = NULL;
|
|
|
|
/* allocate memory for the internal state */
|
|
state = kzalloc(sizeof(struct mt312_state), GFP_KERNEL);
|
|
if (state == NULL)
|
|
goto error;
|
|
|
|
/* setup the state */
|
|
state->config = config;
|
|
state->i2c = i2c;
|
|
|
|
/* check if the demod is there */
|
|
if (mt312_readreg(state, ID, &state->id) < 0)
|
|
goto error;
|
|
|
|
/* create dvb_frontend */
|
|
memcpy(&state->frontend.ops, &mt312_ops,
|
|
sizeof(struct dvb_frontend_ops));
|
|
state->frontend.demodulator_priv = state;
|
|
|
|
switch (state->id) {
|
|
case ID_VP310:
|
|
strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S");
|
|
state->xtal = MT312_PLL_CLK;
|
|
state->freq_mult = 9;
|
|
break;
|
|
case ID_MT312:
|
|
strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S");
|
|
state->xtal = MT312_PLL_CLK;
|
|
state->freq_mult = 6;
|
|
break;
|
|
case ID_ZL10313:
|
|
strcpy(state->frontend.ops.info.name, "Zarlink ZL10313 DVB-S");
|
|
state->xtal = MT312_PLL_CLK_10_111;
|
|
state->freq_mult = 9;
|
|
break;
|
|
default:
|
|
printk(KERN_WARNING "Only Zarlink VP310/MT312/ZL10313"
|
|
" are supported chips.\n");
|
|
goto error;
|
|
}
|
|
|
|
return &state->frontend;
|
|
|
|
error:
|
|
kfree(state);
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL(mt312_attach);
|
|
|
|
module_param(debug, int, 0644);
|
|
MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
|
|
|
|
MODULE_DESCRIPTION("Zarlink VP310/MT312/ZL10313 DVB-S Demodulator driver");
|
|
MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
|
|
MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>");
|
|
MODULE_LICENSE("GPL");
|
|
|