mirror of https://gitee.com/openkylin/linux.git
6e7a9f0c4e
- Support dangerous debugfs actions on clks with dead code - Convert gpio, fixed-factor, mux, gate, divider basic clks to hw based APIs * clk-debugfs-danger: clk: Add support for setting clk_rate via debugfs * clk-basic-hw: clk: divider: Add support for specifying parents via DT/pointers clk: gate: Add support for specifying parents via DT/pointers clk: mux: Add support for specifying parents via DT/pointers clk: asm9260: Use parent accuracy in fixed rate clk clk: fixed-rate: Document that accuracy isn't a rate clk: fixed-rate: Add clk flags for parent accuracy clk: fixed-rate: Add support for specifying parents via DT/pointers clk: fixed-rate: Document accuracy member clk: fixed-rate: Move to_clk_fixed_rate() to C file clk: fixed-rate: Remove clk_register_fixed_rate_with_accuracy() clk: fixed-rate: Convert to clk_hw based APIs clk: gpio: Use DT way of specifying parents * clk-renesas: clk: renesas: Prepare for split of R-Car H3 config symbol dt-bindings: clock: renesas: cpg-mssr: Fix r8a774b1 typo clk: renesas: r7s9210: Add SPIBSC clock clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks clk: renesas: Remove use of ARCH_R8A7796 clk: renesas: rcar-gen2: Change multipliers and dividers to u8 * clk-amlogic: clk: clarify that clk_set_rate() does updates from top to bottom clk: meson: meson8b: make the CCF use the glitch-free mali mux clk: meson: pll: Fix by 0 division in __pll_params_to_rate() clk: meson: g12a: fix missing uart2 in regmap table clk: meson: meson8b: use of_clk_hw_register to register the clocks clk: meson: meson8b: don't register the XTAL clock when provided via OF clk: meson: meson8b: change references to the XTAL clock to use [fw_]name clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller dt-bindings: clock: meson8b: add the clock inputs dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding * clk-allwinner: clk: sunxi: a23/a33: Export the MIPI PLL clk: sunxi: a31: Export the MIPI PLL clk: sunxi-ng: a64: export CLK_CPUX clock for DVFS clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock clk: sunxi-ng: r40: Export MBUS clock clk: sunxi: use of_device_get_match_data |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| axg-aoclk.c | ||
| axg-aoclk.h | ||
| axg-audio.c | ||
| axg-audio.h | ||
| axg.c | ||
| axg.h | ||
| clk-cpu-dyndiv.c | ||
| clk-cpu-dyndiv.h | ||
| clk-dualdiv.c | ||
| clk-dualdiv.h | ||
| clk-mpll.c | ||
| clk-mpll.h | ||
| clk-phase.c | ||
| clk-phase.h | ||
| clk-pll.c | ||
| clk-pll.h | ||
| clk-regmap.c | ||
| clk-regmap.h | ||
| g12a-aoclk.c | ||
| g12a-aoclk.h | ||
| g12a.c | ||
| g12a.h | ||
| gxbb-aoclk.c | ||
| gxbb-aoclk.h | ||
| gxbb.c | ||
| gxbb.h | ||
| meson-aoclk.c | ||
| meson-aoclk.h | ||
| meson-eeclk.c | ||
| meson-eeclk.h | ||
| meson8-ddr.c | ||
| meson8b.c | ||
| meson8b.h | ||
| parm.h | ||
| sclk-div.c | ||
| sclk-div.h | ||
| vid-pll-div.c | ||
| vid-pll-div.h | ||