mirror of https://gitee.com/openkylin/linux.git
612 lines
13 KiB
Plaintext
612 lines
13 KiB
Plaintext
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8996.h>
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#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
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/ {
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model = "Qualcomm Technologies, Inc. MSM8996";
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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memory {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0 0 0>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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mba_region: mba@91500000 {
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reg = <0x0 0x91500000 0x0 0x200000>;
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no-map;
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};
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slpi_region: slpi@90b00000 {
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reg = <0x0 0x90b00000 0x0 0xa00000>;
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no-map;
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};
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venus_region: venus@90400000 {
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reg = <0x0 0x90400000 0x0 0x700000>;
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no-map;
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};
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adsp_region: adsp@8ea00000 {
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reg = <0x0 0x8ea00000 0x0 0x1a00000>;
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no-map;
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};
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mpss_region: mpss@88800000 {
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reg = <0x0 0x88800000 0x0 0x6200000>;
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no-map;
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};
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smem_mem: smem-mem@86000000 {
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reg = <0x0 0x86000000 0x0 0x200000>;
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no-map;
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};
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memory@85800000 {
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reg = <0x0 0x85800000 0x0 0x800000>;
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no-map;
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};
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memory@86200000 {
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reg = <0x0 0x86200000 0x0 0x2600000>;
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no-map;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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CPU3: cpu@101 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x101>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU2>;
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};
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core1 {
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cpu = <&CPU3>;
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};
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};
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};
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};
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thermal-zones {
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cpu-thermal0 {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens0 3>;
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trips {
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cpu_alert0: trip0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit0: trip1 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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cpu-thermal1 {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens0 5>;
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trips {
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cpu_alert1: trip0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit1: trip1 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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cpu-thermal2 {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens0 8>;
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trips {
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cpu_alert2: trip0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit2: trip1 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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cpu-thermal3 {
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polling-delay-passive = <250>;
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polling-delay = <1000>;
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thermal-sensors = <&tsens0 10>;
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trips {
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cpu_alert3: trip0 {
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temperature = <75000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit3: trip1 {
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temperature = <110000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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clocks {
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xo_board: xo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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clock-output-names = "xo_board";
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};
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32764>;
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clock-output-names = "sleep_clk";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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firmware {
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scm {
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compatible = "qcom,scm-msm8996";
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};
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_regs 0 0x1000>;
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#hwlock-cells = <1>;
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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tcsr_mutex_regs: syscon@740000 {
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compatible = "syscon";
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reg = <0x740000 0x20000>;
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};
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intc: interrupt-controller@9bc0000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x40000>;
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reg = <0x09bc0000 0x10000>,
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<0x09c00000 0x100000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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apcs: syscon@9820000 {
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compatible = "syscon";
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reg = <0x9820000 0x1000>;
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};
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gcc: clock-controller@300000 {
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compatible = "qcom,gcc-msm8996";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0x300000 0x90000>;
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};
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kryocc: clock-controller@6400000 {
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compatible = "qcom,apcc-msm8996";
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reg = <0x6400000 0x90000>;
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#clock-cells = <1>;
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};
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blsp1_spi0: spi@07575000 {
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x07575000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp1_spi0_default>;
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pinctrl-1 = <&blsp1_spi0_sleep>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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blsp2_i2c0: i2c@075b5000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x075b5000 0x1000>;
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interrupts = <GIC_SPI 101 0>;
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clocks = <&gcc GCC_BLSP2_AHB_CLK>,
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<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp2_i2c0_default>;
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pinctrl-1 = <&blsp2_i2c0_sleep>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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tsens0: thermal-sensor@4a8000 {
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compatible = "qcom,msm8996-tsens";
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reg = <0x4a8000 0x2000>;
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#thermal-sensor-cells = <1>;
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};
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blsp2_uart1: serial@75b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x75b0000 0x1000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
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<&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp2_i2c1: i2c@075b6000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x075b6000 0x1000>;
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interrupts = <GIC_SPI 102 0>;
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clocks = <&gcc GCC_BLSP2_AHB_CLK>,
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<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp2_i2c1_default>;
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pinctrl-1 = <&blsp2_i2c1_sleep>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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blsp2_uart2: serial@75b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x075b1000 0x1000>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
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<&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp1_i2c2: i2c@07577000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x07577000 0x1000>;
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interrupts = <GIC_SPI 97 0>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp1_i2c2_default>;
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pinctrl-1 = <&blsp1_i2c2_sleep>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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blsp2_spi5: spi@075ba000{
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x075ba000 0x600>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
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<&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&blsp2_spi5_default>;
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pinctrl-1 = <&blsp2_spi5_sleep>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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sdhc2: sdhci@74a4900 {
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status = "disabled";
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compatible = "qcom,sdhci-msm-v4";
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reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <0 125 0>, <0 221 0>;
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interrupt-names = "hc_irq", "pwr_irq";
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clock-names = "iface", "core", "xo";
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clocks = <&gcc GCC_SDCC2_AHB_CLK>,
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<&gcc GCC_SDCC2_APPS_CLK>,
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<&xo_board>;
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bus-width = <4>;
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};
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msmgpio: pinctrl@1010000 {
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compatible = "qcom,msm8996-pinctrl";
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reg = <0x01010000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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timer@09840000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x09840000 0x1000>;
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clock-frequency = <19200000>;
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frame@9850000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x09850000 0x1000>,
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<0x09860000 0x1000>;
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};
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frame@9870000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x09870000 0x1000>;
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status = "disabled";
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};
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frame@9880000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x09880000 0x1000>;
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status = "disabled";
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};
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frame@9890000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x09890000 0x1000>;
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status = "disabled";
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};
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frame@98a0000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x098a0000 0x1000>;
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status = "disabled";
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};
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frame@98b0000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x098b0000 0x1000>;
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status = "disabled";
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};
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frame@98c0000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x098c0000 0x1000>;
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status = "disabled";
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};
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};
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spmi_bus: qcom,spmi@400f000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x400f000 0x1000>,
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<0x4400000 0x800000>,
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<0x4c00000 0x800000>,
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<0x5800000 0x200000>,
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<0x400a000 0x002100>;
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reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
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interrupt-names = "periph_irq";
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interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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};
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mmcc: clock-controller@8c0000 {
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compatible = "qcom,mmcc-msm8996";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0x8c0000 0x40000>;
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assigned-clocks = <&mmcc MMPLL9_PLL>,
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|
<&mmcc MMPLL1_PLL>,
|
|
<&mmcc MMPLL3_PLL>,
|
|
<&mmcc MMPLL4_PLL>,
|
|
<&mmcc MMPLL5_PLL>;
|
|
assigned-clock-rates = <624000000>,
|
|
<810000000>,
|
|
<980000000>,
|
|
<960000000>,
|
|
<825000000>;
|
|
};
|
|
};
|
|
|
|
adsp-pil {
|
|
compatible = "qcom,msm8996-adsp-pil";
|
|
|
|
interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
|
|
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
|
|
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
|
|
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
|
|
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "wdog", "fatal", "ready",
|
|
"handover", "stop-ack";
|
|
|
|
clocks = <&xo_board>;
|
|
clock-names = "xo";
|
|
|
|
memory-region = <&adsp_region>;
|
|
|
|
qcom,smem-states = <&adsp_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
};
|
|
|
|
adsp-smp2p {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <443>, <429>;
|
|
|
|
interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
qcom,ipc = <&apcs 16 10>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <2>;
|
|
|
|
adsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
adsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
smp2p-slpi {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <481>, <430>;
|
|
|
|
interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
qcom,ipc = <&apcs 16 26>;
|
|
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <3>;
|
|
|
|
slpi_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
slpi_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
};
|
|
|
|
};
|
|
#include "msm8996-pins.dtsi"
|