mirror of https://gitee.com/openkylin/linux.git
250 lines
6.0 KiB
C
250 lines
6.0 KiB
C
/*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/slab.h>
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#include "clkc.h"
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static DEFINE_SPINLOCK(clk_lock);
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static struct clk **clks;
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static struct clk_onecell_data clk_data;
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struct clk ** __init meson_clk_init(struct device_node *np,
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unsigned long nr_clks)
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{
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clks = kcalloc(nr_clks, sizeof(*clks), GFP_KERNEL);
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if (!clks)
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return ERR_PTR(-ENOMEM);
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clk_data.clks = clks;
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clk_data.clk_num = nr_clks;
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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return clks;
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}
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static void meson_clk_add_lookup(struct clk *clk, unsigned int id)
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{
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if (clks && id)
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clks[id] = clk;
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}
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static struct clk * __init
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meson_clk_register_composite(const struct clk_conf *clk_conf,
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void __iomem *clk_base)
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{
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struct clk *clk;
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struct clk_mux *mux = NULL;
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struct clk_divider *div = NULL;
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struct clk_gate *gate = NULL;
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const struct clk_ops *mux_ops = NULL;
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const struct composite_conf *composite_conf;
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composite_conf = clk_conf->conf.composite;
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if (clk_conf->num_parents > 1) {
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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mux->reg = clk_base + clk_conf->reg_off
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+ composite_conf->mux_parm.reg_off;
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mux->shift = composite_conf->mux_parm.shift;
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mux->mask = BIT(composite_conf->mux_parm.width) - 1;
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mux->flags = composite_conf->mux_flags;
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mux->lock = &clk_lock;
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mux->table = composite_conf->mux_table;
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mux_ops = (composite_conf->mux_flags & CLK_MUX_READ_ONLY) ?
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&clk_mux_ro_ops : &clk_mux_ops;
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}
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if (MESON_PARM_APPLICABLE(&composite_conf->div_parm)) {
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div) {
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clk = ERR_PTR(-ENOMEM);
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goto error;
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}
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div->reg = clk_base + clk_conf->reg_off
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+ composite_conf->div_parm.reg_off;
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div->shift = composite_conf->div_parm.shift;
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div->width = composite_conf->div_parm.width;
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div->lock = &clk_lock;
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div->flags = composite_conf->div_flags;
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div->table = composite_conf->div_table;
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}
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if (MESON_PARM_APPLICABLE(&composite_conf->gate_parm)) {
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate) {
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clk = ERR_PTR(-ENOMEM);
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goto error;
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}
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gate->reg = clk_base + clk_conf->reg_off
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+ composite_conf->div_parm.reg_off;
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gate->bit_idx = composite_conf->gate_parm.shift;
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gate->flags = composite_conf->gate_flags;
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gate->lock = &clk_lock;
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}
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clk = clk_register_composite(NULL, clk_conf->clk_name,
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clk_conf->clks_parent,
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clk_conf->num_parents,
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mux ? &mux->hw : NULL, mux_ops,
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div ? &div->hw : NULL, &clk_divider_ops,
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gate ? &gate->hw : NULL, &clk_gate_ops,
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clk_conf->flags);
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if (IS_ERR(clk))
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goto error;
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return clk;
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error:
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kfree(gate);
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kfree(div);
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kfree(mux);
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return clk;
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}
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static struct clk * __init
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meson_clk_register_fixed_factor(const struct clk_conf *clk_conf,
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void __iomem *clk_base)
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{
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struct clk *clk;
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const struct fixed_fact_conf *fixed_fact_conf;
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const struct parm *p;
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unsigned int mult, div;
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u32 reg;
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fixed_fact_conf = &clk_conf->conf.fixed_fact;
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mult = clk_conf->conf.fixed_fact.mult;
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div = clk_conf->conf.fixed_fact.div;
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if (!mult) {
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mult = 1;
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p = &fixed_fact_conf->mult_parm;
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if (MESON_PARM_APPLICABLE(p)) {
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reg = readl(clk_base + clk_conf->reg_off + p->reg_off);
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mult = PARM_GET(p->width, p->shift, reg);
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}
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}
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if (!div) {
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div = 1;
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p = &fixed_fact_conf->div_parm;
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if (MESON_PARM_APPLICABLE(p)) {
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reg = readl(clk_base + clk_conf->reg_off + p->reg_off);
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mult = PARM_GET(p->width, p->shift, reg);
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}
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}
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clk = clk_register_fixed_factor(NULL,
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clk_conf->clk_name,
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clk_conf->clks_parent[0],
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clk_conf->flags,
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mult, div);
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return clk;
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}
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static struct clk * __init
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meson_clk_register_fixed_rate(const struct clk_conf *clk_conf,
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void __iomem *clk_base)
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{
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struct clk *clk;
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const struct fixed_rate_conf *fixed_rate_conf;
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const struct parm *r;
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unsigned long rate;
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u32 reg;
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fixed_rate_conf = &clk_conf->conf.fixed_rate;
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rate = fixed_rate_conf->rate;
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if (!rate) {
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r = &fixed_rate_conf->rate_parm;
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reg = readl(clk_base + clk_conf->reg_off + r->reg_off);
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rate = PARM_GET(r->width, r->shift, reg);
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}
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rate *= 1000000;
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clk = clk_register_fixed_rate(NULL,
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clk_conf->clk_name,
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clk_conf->num_parents
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? clk_conf->clks_parent[0] : NULL,
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clk_conf->flags, rate);
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return clk;
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}
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void __init meson_clk_register_clks(const struct clk_conf *clk_confs,
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size_t nr_confs,
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void __iomem *clk_base)
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{
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unsigned int i;
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struct clk *clk = NULL;
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for (i = 0; i < nr_confs; i++) {
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const struct clk_conf *clk_conf = &clk_confs[i];
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switch (clk_conf->clk_type) {
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case CLK_FIXED_RATE:
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clk = meson_clk_register_fixed_rate(clk_conf,
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clk_base);
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break;
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case CLK_FIXED_FACTOR:
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clk = meson_clk_register_fixed_factor(clk_conf,
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clk_base);
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break;
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case CLK_COMPOSITE:
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clk = meson_clk_register_composite(clk_conf,
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clk_base);
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break;
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case CLK_CPU:
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clk = meson_clk_register_cpu(clk_conf, clk_base,
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&clk_lock);
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break;
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case CLK_PLL:
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clk = meson_clk_register_pll(clk_conf, clk_base,
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&clk_lock);
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break;
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default:
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clk = NULL;
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}
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if (!clk) {
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pr_err("%s: unknown clock type %d\n", __func__,
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clk_conf->clk_type);
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continue;
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}
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if (IS_ERR(clk)) {
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pr_warn("%s: Unable to create %s clock\n", __func__,
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clk_conf->clk_name);
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continue;
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}
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meson_clk_add_lookup(clk, clk_conf->clk_id);
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}
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}
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