mirror of https://gitee.com/openkylin/linux.git
167 lines
4.7 KiB
C
167 lines
4.7 KiB
C
/*
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* Tegra124 DFLL FCPU clock source driver
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*
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* Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved.
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*
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* Aleksandr Frid <afrid@nvidia.com>
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* Paul Walmsley <pwalmsley@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/cpu.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <soc/tegra/fuse.h>
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#include "clk.h"
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#include "clk-dfll.h"
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#include "cvb.h"
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/* Maximum CPU frequency, indexed by CPU speedo id */
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static const unsigned long cpu_max_freq_table[] = {
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[0] = 2014500000UL,
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[1] = 2320500000UL,
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[2] = 2116500000UL,
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[3] = 2524500000UL,
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};
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static const struct cvb_table tegra124_cpu_cvb_tables[] = {
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{
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.speedo_id = -1,
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.process_id = -1,
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.min_millivolts = 900,
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.max_millivolts = 1260,
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.alignment = {
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.step_uv = 10000, /* 10mV */
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},
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.speedo_scale = 100,
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.voltage_scale = 1000,
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.cvb_table = {
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{204000000UL, {1112619, -29295, 402} },
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{306000000UL, {1150460, -30585, 402} },
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{408000000UL, {1190122, -31865, 402} },
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{510000000UL, {1231606, -33155, 402} },
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{612000000UL, {1274912, -34435, 402} },
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{714000000UL, {1320040, -35725, 402} },
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{816000000UL, {1366990, -37005, 402} },
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{918000000UL, {1415762, -38295, 402} },
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{1020000000UL, {1466355, -39575, 402} },
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{1122000000UL, {1518771, -40865, 402} },
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{1224000000UL, {1573009, -42145, 402} },
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{1326000000UL, {1629068, -43435, 402} },
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{1428000000UL, {1686950, -44715, 402} },
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{1530000000UL, {1746653, -46005, 402} },
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{1632000000UL, {1808179, -47285, 402} },
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{1734000000UL, {1871526, -48575, 402} },
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{1836000000UL, {1936696, -49855, 402} },
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{1938000000UL, {2003687, -51145, 402} },
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{2014500000UL, {2054787, -52095, 402} },
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{2116500000UL, {2124957, -53385, 402} },
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{2218500000UL, {2196950, -54665, 402} },
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{2320500000UL, {2270765, -55955, 402} },
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{2422500000UL, {2346401, -57235, 402} },
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{2524500000UL, {2437299, -58535, 402} },
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{0, { 0, 0, 0} },
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},
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.cpu_dfll_data = {
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.tune0_low = 0x005020ff,
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.tune0_high = 0x005040ff,
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.tune1 = 0x00000060,
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}
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},
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};
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static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
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{
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int process_id, speedo_id, speedo_value;
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struct tegra_dfll_soc_data *soc;
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const struct cvb_table *cvb;
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process_id = tegra_sku_info.cpu_process_id;
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speedo_id = tegra_sku_info.cpu_speedo_id;
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speedo_value = tegra_sku_info.cpu_speedo_value;
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if (speedo_id >= ARRAY_SIZE(cpu_max_freq_table)) {
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dev_err(&pdev->dev, "unknown max CPU freq for speedo_id=%d\n",
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speedo_id);
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return -ENODEV;
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}
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soc = devm_kzalloc(&pdev->dev, sizeof(*soc), GFP_KERNEL);
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if (!soc)
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return -ENOMEM;
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soc->dev = get_cpu_device(0);
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if (!soc->dev) {
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dev_err(&pdev->dev, "no CPU0 device\n");
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return -ENODEV;
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}
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cvb = tegra_cvb_build_opp_table(tegra124_cpu_cvb_tables,
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ARRAY_SIZE(tegra124_cpu_cvb_tables),
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process_id, speedo_id, speedo_value,
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cpu_max_freq_table[speedo_id],
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soc->dev);
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if (IS_ERR(cvb)) {
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dev_err(&pdev->dev, "couldn't build OPP table: %ld\n",
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PTR_ERR(cvb));
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return PTR_ERR(cvb);
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}
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soc->min_millivolts = cvb->min_millivolts;
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soc->tune0_low = cvb->cpu_dfll_data.tune0_low;
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soc->tune0_high = cvb->cpu_dfll_data.tune0_high;
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soc->tune1 = cvb->cpu_dfll_data.tune1;
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return tegra_dfll_register(pdev, soc);
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}
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static const struct of_device_id tegra124_dfll_fcpu_of_match[] = {
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{ .compatible = "nvidia,tegra124-dfll", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, tegra124_dfll_fcpu_of_match);
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static const struct dev_pm_ops tegra124_dfll_pm_ops = {
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SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend,
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tegra_dfll_runtime_resume, NULL)
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};
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static struct platform_driver tegra124_dfll_fcpu_driver = {
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.probe = tegra124_dfll_fcpu_probe,
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.remove = tegra_dfll_unregister,
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.driver = {
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.name = "tegra124-dfll",
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.of_match_table = tegra124_dfll_fcpu_of_match,
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.pm = &tegra124_dfll_pm_ops,
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},
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};
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static int __init tegra124_dfll_fcpu_init(void)
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{
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return platform_driver_register(&tegra124_dfll_fcpu_driver);
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}
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module_init(tegra124_dfll_fcpu_init);
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static void __exit tegra124_dfll_fcpu_exit(void)
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{
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platform_driver_unregister(&tegra124_dfll_fcpu_driver);
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}
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module_exit(tegra124_dfll_fcpu_exit);
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MODULE_DESCRIPTION("Tegra124 DFLL clock source driver");
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Aleksandr Frid <afrid@nvidia.com>");
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MODULE_AUTHOR("Paul Walmsley <pwalmsley@nvidia.com>");
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