mirror of https://gitee.com/openkylin/linux.git
434 lines
16 KiB
C
434 lines
16 KiB
C
/*
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* Board definitions for the Radstone PPC7D boards.
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*
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* Author: James Chapman <jchapman@katalix.com>
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*
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* Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
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* Based on code done by - Mark A. Greer <mgreer@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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* The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
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* PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
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* We'll only use one PCI MEM window on each PCI bus.
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*
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* This is the CPU physical memory map (windows must be at least 1MB
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* and start on a boundary that is a multiple of the window size):
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*
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* 0xff800000-0xffffffff - Boot window
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* 0xff000000-0xff000fff - AFIX registers (DevCS2)
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* 0xfef00000-0xfef0ffff - Internal MV64x60 registers
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* 0xfef40000-0xfef7ffff - Internal SRAM
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* 0xfef00000-0xfef0ffff - MV64360 Registers
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* 0x70000000-0x7fffffff - soldered flash (DevCS3)
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* 0xe8000000-0xe9ffffff - PCI I/O
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* 0x80000000-0xbfffffff - PCI MEM
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*/
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#ifndef __PPC_PLATFORMS_PPC7D_H
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#define __PPC_PLATFORMS_PPC7D_H
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#include <asm/ppcboot.h>
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/*****************************************************************************
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* CPU Physical Memory Map setup.
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*****************************************************************************/
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#define PPC7D_BOOT_WINDOW_BASE 0xff800000
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#define PPC7D_AFIX_REG_BASE 0xff000000
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#define PPC7D_INTERNAL_SRAM_BASE 0xfef40000
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#define PPC7D_FLASH_BASE 0x70000000
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#define PPC7D_BOOT_WINDOW_SIZE_ACTUAL 0x00800000 /* 8MB */
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#define PPC7D_FLASH_SIZE_ACTUAL 0x10000000 /* 256MB */
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#define PPC7D_BOOT_WINDOW_SIZE max(MV64360_WINDOW_SIZE_MIN, \
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PPC7D_BOOT_WINDOW_SIZE_ACTUAL)
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#define PPC7D_FLASH_SIZE max(MV64360_WINDOW_SIZE_MIN, \
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PPC7D_FLASH_SIZE_ACTUAL)
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#define PPC7D_AFIX_REG_SIZE max(MV64360_WINDOW_SIZE_MIN, 0xff)
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#define PPC7D_PCI0_MEM0_START_PROC_ADDR 0x80000000UL
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#define PPC7D_PCI0_MEM0_START_PCI_HI_ADDR 0x00000000UL
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#define PPC7D_PCI0_MEM0_START_PCI_LO_ADDR 0x80000000UL
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#define PPC7D_PCI0_MEM0_SIZE 0x20000000UL
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#define PPC7D_PCI0_MEM1_START_PROC_ADDR 0xe8010000UL
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#define PPC7D_PCI0_MEM1_START_PCI_HI_ADDR 0x00000000UL
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#define PPC7D_PCI0_MEM1_START_PCI_LO_ADDR 0x00000000UL
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#define PPC7D_PCI0_MEM1_SIZE 0x000f0000UL
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#define PPC7D_PCI0_IO_START_PROC_ADDR 0xe8000000UL
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#define PPC7D_PCI0_IO_START_PCI_ADDR 0x00000000UL
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#define PPC7D_PCI0_IO_SIZE 0x00010000UL
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#define PPC7D_PCI1_MEM0_START_PROC_ADDR 0xa0000000UL
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#define PPC7D_PCI1_MEM0_START_PCI_HI_ADDR 0x00000000UL
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#define PPC7D_PCI1_MEM0_START_PCI_LO_ADDR 0xa0000000UL
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#define PPC7D_PCI1_MEM0_SIZE 0x20000000UL
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#define PPC7D_PCI1_MEM1_START_PROC_ADDR 0xe9800000UL
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#define PPC7D_PCI1_MEM1_START_PCI_HI_ADDR 0x00000000UL
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#define PPC7D_PCI1_MEM1_START_PCI_LO_ADDR 0x00000000UL
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#define PPC7D_PCI1_MEM1_SIZE 0x00800000UL
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#define PPC7D_PCI1_IO_START_PROC_ADDR 0xe9000000UL
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#define PPC7D_PCI1_IO_START_PCI_ADDR 0x00000000UL
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#define PPC7D_PCI1_IO_SIZE 0x00010000UL
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#define PPC7D_DEFAULT_BAUD 9600
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#define PPC7D_MPSC_CLK_SRC 8 /* TCLK */
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#define PPC7D_MPSC_CLK_FREQ 133333333 /* 133.3333... MHz */
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#define PPC7D_ETH0_PHY_ADDR 8
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#define PPC7D_ETH1_PHY_ADDR 9
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#define PPC7D_ETH2_PHY_ADDR 0
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#define PPC7D_ETH_TX_QUEUE_SIZE 400
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#define PPC7D_ETH_RX_QUEUE_SIZE 400
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#define PPC7D_ETH_PORT_CONFIG_VALUE \
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MV64340_ETH_UNICAST_NORMAL_MODE | \
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MV64340_ETH_DEFAULT_RX_QUEUE_0 | \
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MV64340_ETH_DEFAULT_RX_ARP_QUEUE_0 | \
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MV64340_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
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MV64340_ETH_RECEIVE_BC_IF_IP | \
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MV64340_ETH_RECEIVE_BC_IF_ARP | \
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MV64340_ETH_CAPTURE_TCP_FRAMES_DIS | \
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MV64340_ETH_CAPTURE_UDP_FRAMES_DIS | \
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MV64340_ETH_DEFAULT_RX_TCP_QUEUE_0 | \
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MV64340_ETH_DEFAULT_RX_UDP_QUEUE_0 | \
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MV64340_ETH_DEFAULT_RX_BPDU_QUEUE_0
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#define PPC7D_ETH_PORT_CONFIG_EXTEND_VALUE \
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MV64340_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
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MV64340_ETH_PARTITION_DISABLE
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#define GT_ETH_IPG_INT_RX(value) \
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((value & 0x3fff) << 8)
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#define PPC7D_ETH_PORT_SDMA_CONFIG_VALUE \
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MV64340_ETH_RX_BURST_SIZE_4_64BIT | \
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GT_ETH_IPG_INT_RX(0) | \
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MV64340_ETH_TX_BURST_SIZE_4_64BIT
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#define PPC7D_ETH_PORT_SERIAL_CONTROL_VALUE \
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MV64340_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
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MV64340_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
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MV64340_ETH_ADV_SYMMETRIC_FLOW_CTRL | \
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MV64340_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
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MV64340_ETH_FORCE_BP_MODE_NO_JAM | \
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(1 << 9) | \
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MV64340_ETH_DO_NOT_FORCE_LINK_FAIL | \
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MV64340_ETH_RETRANSMIT_16_ATTEMPTS | \
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MV64340_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
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MV64340_ETH_DTE_ADV_0 | \
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MV64340_ETH_DISABLE_AUTO_NEG_BYPASS | \
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MV64340_ETH_AUTO_NEG_NO_CHANGE | \
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MV64340_ETH_MAX_RX_PACKET_9700BYTE | \
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MV64340_ETH_CLR_EXT_LOOPBACK | \
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MV64340_ETH_SET_FULL_DUPLEX_MODE | \
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MV64340_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
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/*****************************************************************************
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* Serial defines.
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*****************************************************************************/
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#define PPC7D_SERIAL_0 0xe80003f8
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#define PPC7D_SERIAL_1 0xe80002f8
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#define RS_TABLE_SIZE 2
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/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
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#define UART_CLK 1843200
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#define BASE_BAUD ( UART_CLK / 16 )
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#ifdef CONFIG_SERIAL_DETECT_IRQ
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ)
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#else
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#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF)
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#endif
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#define STD_SERIAL_PORT_DFNS \
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{ 0, BASE_BAUD, PPC7D_SERIAL_0, 4, STD_COM_FLAGS, /* ttyS0 */ \
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iomem_base: (u8 *)PPC7D_SERIAL_0, \
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io_type: SERIAL_IO_MEM, }, \
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{ 0, BASE_BAUD, PPC7D_SERIAL_1, 3, STD_COM_FLAGS, /* ttyS1 */ \
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iomem_base: (u8 *)PPC7D_SERIAL_1, \
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io_type: SERIAL_IO_MEM },
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#define SERIAL_PORT_DFNS \
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STD_SERIAL_PORT_DFNS
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/*****************************************************************************
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* CPLD defines.
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*
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* Register map:-
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*
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* 0000 to 000F South Bridge DMA 1 Control
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* 0020 and 0021 South Bridge Interrupt 1 Control
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* 0040 to 0043 South Bridge Counter Control
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* 0060 Keyboard
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* 0061 South Bridge NMI Status and Control
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* 0064 Keyboard
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* 0071 and 0072 RTC R/W
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* 0078 to 007B South Bridge BIOS Timer
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* 0080 to 0090 South Bridge DMA Pages
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* 00A0 and 00A1 South Bridge Interrupt 2 Control
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* 00C0 to 00DE South Bridge DMA 2 Control
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* 02E8 to 02EF COM6 R/W
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* 02F8 to 02FF South Bridge COM2 R/W
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* 03E8 to 03EF COM5 R/W
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* 03F8 to 03FF South Bridge COM1 R/W
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* 040A South Bridge DMA Scatter/Gather RO
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* 040B DMA 1 Extended Mode WO
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* 0410 to 043F South Bridge DMA Scatter/Gather
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* 0481 to 048B South Bridge DMA High Pages
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* 04D0 and 04D1 South Bridge Edge/Level Control
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* 04D6 DMA 2 Extended Mode WO
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* 0804 Memory Configuration RO
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* 0806 Memory Configuration Extend RO
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* 0808 SCSI Activity LED R/W
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* 080C Equipment Present 1 RO
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* 080E Equipment Present 2 RO
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* 0810 Equipment Present 3 RO
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* 0812 Equipment Present 4 RO
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* 0818 Key Lock RO
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* 0820 LEDS R/W
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* 0824 COMs R/W
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* 0826 RTS R/W
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* 0828 Reset R/W
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* 082C Watchdog Trig R/W
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* 082E Interrupt R/W
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* 0830 Interrupt Status RO
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* 0832 PCI configuration RO
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* 0854 Board Revision RO
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* 0858 Extended ID RO
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* 0864 ID Link RO
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* 0866 Motherboard Type RO
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* 0868 FLASH Write control RO
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* 086A Software FLASH write protect R/W
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* 086E FLASH Control R/W
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*****************************************************************************/
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#define PPC7D_CPLD_MEM_CONFIG 0x0804
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#define PPC7D_CPLD_MEM_CONFIG_EXTEND 0x0806
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#define PPC7D_CPLD_SCSI_ACTIVITY_LED 0x0808
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#define PPC7D_CPLD_EQUIPMENT_PRESENT_1 0x080C
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#define PPC7D_CPLD_EQUIPMENT_PRESENT_2 0x080E
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#define PPC7D_CPLD_EQUIPMENT_PRESENT_3 0x0810
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#define PPC7D_CPLD_EQUIPMENT_PRESENT_4 0x0812
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#define PPC7D_CPLD_KEY_LOCK 0x0818
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#define PPC7D_CPLD_LEDS 0x0820
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#define PPC7D_CPLD_COMS 0x0824
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#define PPC7D_CPLD_RTS 0x0826
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#define PPC7D_CPLD_RESET 0x0828
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#define PPC7D_CPLD_WATCHDOG_TRIG 0x082C
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#define PPC7D_CPLD_INTR 0x082E
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#define PPC7D_CPLD_INTR_STATUS 0x0830
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#define PPC7D_CPLD_PCI_CONFIG 0x0832
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#define PPC7D_CPLD_BOARD_REVISION 0x0854
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#define PPC7D_CPLD_EXTENDED_ID 0x0858
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#define PPC7D_CPLD_ID_LINK 0x0864
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#define PPC7D_CPLD_MOTHERBOARD_TYPE 0x0866
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#define PPC7D_CPLD_FLASH_WRITE_CNTL 0x0868
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#define PPC7D_CPLD_SW_FLASH_WRITE_PROTECT 0x086A
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#define PPC7D_CPLD_FLASH_CNTL 0x086E
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/* MEMORY_CONFIG_EXTEND */
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#define PPC7D_CPLD_SDRAM_BANK_NUM_MASK 0x02
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#define PPC7D_CPLD_SDRAM_BANK_SIZE_MASK 0xc0
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#define PPC7D_CPLD_SDRAM_BANK_SIZE_128M 0
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#define PPC7D_CPLD_SDRAM_BANK_SIZE_256M 0x40
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#define PPC7D_CPLD_SDRAM_BANK_SIZE_512M 0x80
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#define PPC7D_CPLD_SDRAM_BANK_SIZE_1G 0xc0
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#define PPC7D_CPLD_FLASH_DEV_SIZE_MASK 0x03
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#define PPC7D_CPLD_FLASH_BANK_NUM_MASK 0x0c
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#define PPC7D_CPLD_FLASH_DEV_SIZE_64M 0
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#define PPC7D_CPLD_FLASH_DEV_SIZE_32M 1
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#define PPC7D_CPLD_FLASH_DEV_SIZE_16M 3
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#define PPC7D_CPLD_FLASH_BANK_NUM_4 0x00
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#define PPC7D_CPLD_FLASH_BANK_NUM_3 0x04
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#define PPC7D_CPLD_FLASH_BANK_NUM_2 0x08
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#define PPC7D_CPLD_FLASH_BANK_NUM_1 0x0c
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/* SCSI_LED */
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#define PPC7D_CPLD_SCSI_ACTIVITY_LED_OFF 0
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#define PPC7D_CPLD_SCSI_ACTIVITY_LED_ON 1
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/* EQUIPMENT_PRESENT_1 */
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#define PPC7D_CPLD_EQPT_PRES_1_FITTED 0
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#define PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK (0x80 >> 2)
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#define PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK (0x80 >> 3)
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#define PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK (0x80 >> 4)
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/* EQUIPMENT_PRESENT_2 */
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#define PPC7D_CPLD_EQPT_PRES_2_FITTED !0
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#define PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK (0x80 >> 0)
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#define PPC7D_CPLD_EQPT_PRES_2_COM36_MASK (0x80 >> 2)
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#define PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK (0x80 >> 3)
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#define PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK (0x80 >> 4)
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/* EQUIPMENT_PRESENT_3 */
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#define PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK (0x80 >> 3)
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#define PPC7D_CPLD_EQPT_PRES_3_PMC2_5V (0 >> 3)
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#define PPC7D_CPLD_EQPT_PRES_3_PMC2_3V (0x80 >> 3)
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#define PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK (0x80 >> 4)
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#define PPC7D_CPLD_EQPT_PRES_3_PMC1_5V (0 >> 4)
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#define PPC7D_CPLD_EQPT_PRES_3_PMC1_3V (0x80 >> 4)
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#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK (0x80 >> 5)
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#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_INTER (0 >> 5)
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#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_VME (0x80 >> 5)
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/* EQUIPMENT_PRESENT_4 */
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#define PPC7D_CPLD_EQPT_PRES_4_LPT_MASK (0x80 >> 2)
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#define PPC7D_CPLD_EQPT_PRES_4_LPT_FITTED (0x80 >> 2)
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#define PPC7D_CPLD_EQPT_PRES_4_PS2_USB2_MASK (0xc0 >> 6)
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#define PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED (0x40 >> 6)
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#define PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED (0x80 >> 6)
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/* CPLD_LEDS */
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#define PPC7D_CPLD_LEDS_ON (!0)
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#define PPC7D_CPLD_LEDS_OFF (0)
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#define PPC7D_CPLD_LEDS_NVRAM_PAGE_MASK (0xc0 >> 2)
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#define PPC7D_CPLD_LEDS_DS201_MASK (0x80 >> 4)
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#define PPC7D_CPLD_LEDS_DS219_MASK (0x80 >> 5)
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#define PPC7D_CPLD_LEDS_DS220_MASK (0x80 >> 6)
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#define PPC7D_CPLD_LEDS_DS221_MASK (0x80 >> 7)
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/* CPLD_COMS */
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#define PPC7D_CPLD_COMS_COM3_TCLKEN (0x80 >> 0)
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#define PPC7D_CPLD_COMS_COM3_RTCLKEN (0x80 >> 1)
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#define PPC7D_CPLD_COMS_COM3_MODE_MASK (0x80 >> 2)
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#define PPC7D_CPLD_COMS_COM3_MODE_RS232 (0)
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#define PPC7D_CPLD_COMS_COM3_MODE_RS422 (0x80 >> 2)
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#define PPC7D_CPLD_COMS_COM3_TXEN (0x80 >> 3)
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#define PPC7D_CPLD_COMS_COM4_TCLKEN (0x80 >> 4)
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#define PPC7D_CPLD_COMS_COM4_RTCLKEN (0x80 >> 5)
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#define PPC7D_CPLD_COMS_COM4_MODE_MASK (0x80 >> 6)
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#define PPC7D_CPLD_COMS_COM4_MODE_RS232 (0)
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#define PPC7D_CPLD_COMS_COM4_MODE_RS422 (0x80 >> 6)
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#define PPC7D_CPLD_COMS_COM4_TXEN (0x80 >> 7)
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/* CPLD_RTS */
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#define PPC7D_CPLD_RTS_COM36_LOOPBACK (0x80 >> 0)
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#define PPC7D_CPLD_RTS_COM4_SCLK (0x80 >> 1)
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#define PPC7D_CPLD_RTS_COM3_TXFUNC_MASK (0xc0 >> 2)
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#define PPC7D_CPLD_RTS_COM3_TXFUNC_DISABLED (0 >> 2)
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#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED (0x80 >> 2)
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#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED_RTG3 (0xc0 >> 2)
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#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED_RTG3S (0xc0 >> 2)
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#define PPC7D_CPLD_RTS_COM56_MODE_MASK (0x80 >> 4)
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#define PPC7D_CPLD_RTS_COM56_MODE_RS232 (0)
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#define PPC7D_CPLD_RTS_COM56_MODE_RS422 (0x80 >> 4)
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#define PPC7D_CPLD_RTS_COM56_ENABLE_MASK (0x80 >> 5)
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#define PPC7D_CPLD_RTS_COM56_DISABLED (0)
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#define PPC7D_CPLD_RTS_COM56_ENABLED (0x80 >> 5)
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#define PPC7D_CPLD_RTS_COM4_TXFUNC_MASK (0xc0 >> 6)
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#define PPC7D_CPLD_RTS_COM4_TXFUNC_DISABLED (0 >> 6)
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#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED (0x80 >> 6)
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#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED_RTG3 (0x40 >> 6)
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#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED_RTG3S (0x40 >> 6)
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/* WATCHDOG_TRIG */
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#define PPC7D_CPLD_WDOG_CAUSE_MASK (0x80 >> 0)
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#define PPC7D_CPLD_WDOG_CAUSE_NORMAL_RESET (0 >> 0)
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#define PPC7D_CPLD_WDOG_CAUSE_WATCHDOG (0x80 >> 0)
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#define PPC7D_CPLD_WDOG_ENABLE_MASK (0x80 >> 6)
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#define PPC7D_CPLD_WDOG_ENABLE_OFF (0 >> 6)
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#define PPC7D_CPLD_WDOG_ENABLE_ON (0x80 >> 6)
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#define PPC7D_CPLD_WDOG_RESETSW_MASK (0x80 >> 7)
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#define PPC7D_CPLD_WDOG_RESETSW_OFF (0 >> 7)
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#define PPC7D_CPLD_WDOG_RESETSW_ON (0x80 >> 7)
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/* Interrupt mask and status bits */
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#define PPC7D_CPLD_INTR_TEMP_MASK (0x80 >> 0)
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#define PPC7D_CPLD_INTR_HB8_MASK (0x80 >> 1)
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#define PPC7D_CPLD_INTR_PHY1_MASK (0x80 >> 2)
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#define PPC7D_CPLD_INTR_PHY0_MASK (0x80 >> 3)
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#define PPC7D_CPLD_INTR_ISANMI_MASK (0x80 >> 5)
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#define PPC7D_CPLD_INTR_CRITTEMP_MASK (0x80 >> 6)
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/* CPLD_INTR */
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#define PPC7D_CPLD_INTR_ENABLE_OFF (0)
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#define PPC7D_CPLD_INTR_ENABLE_ON (!0)
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/* CPLD_INTR_STATUS */
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#define PPC7D_CPLD_INTR_STATUS_OFF (0)
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#define PPC7D_CPLD_INTR_STATUS_ON (!0)
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/* CPLD_PCI_CONFIG */
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#define PPC7D_CPLD_PCI_CONFIG_PCI0_MASK 0x70
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#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCI33 0x00
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#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCI66 0x10
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#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX33 0x40
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#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX66 0x50
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#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX100 0x60
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#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX133 0x70
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#define PPC7D_CPLD_PCI_CONFIG_PCI1_MASK 0x07
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#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCI33 0x00
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#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCI66 0x01
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#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX33 0x04
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#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX66 0x05
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#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX100 0x06
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#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX133 0x07
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/* CPLD_BOARD_REVISION */
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#define PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK 0xe0
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#define PPC7D_CPLD_BOARD_REVISION_LETTER_MASK 0x1f
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/* CPLD_EXTENDED_ID */
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#define PPC7D_CPLD_EXTENDED_ID_PPC7D 0x18
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/* CPLD_ID_LINK */
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#define PPC7D_CPLD_ID_LINK_VME64_GAP_MASK (0x80 >> 2)
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#define PPC7D_CPLD_ID_LINK_VME64_GA4_MASK (0x80 >> 3)
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#define PPC7D_CPLD_ID_LINK_E13_MASK (0x80 >> 4)
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#define PPC7D_CPLD_ID_LINK_E12_MASK (0x80 >> 5)
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#define PPC7D_CPLD_ID_LINK_E7_MASK (0x80 >> 6)
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#define PPC7D_CPLD_ID_LINK_E6_MASK (0x80 >> 7)
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/* CPLD_MOTHERBOARD_TYPE */
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#define PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK (0x80 >> 0)
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#define PPC7D_CPLD_MB_TYPE_ECC_ENABLED (0x80 >> 0)
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#define PPC7D_CPLD_MB_TYPE_ECC_DISABLED (0 >> 0)
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#define PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK (0x80 >> 3)
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#define PPC7D_CPLD_MB_TYPE_PLL_MASK 0x0c
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#define PPC7D_CPLD_MB_TYPE_PLL_133 0x00
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#define PPC7D_CPLD_MB_TYPE_PLL_100 0x08
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#define PPC7D_CPLD_MB_TYPE_PLL_64 0x04
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#define PPC7D_CPLD_MB_TYPE_HW_ID_MASK 0x03
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/* CPLD_FLASH_WRITE_CNTL */
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#define PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK (0x80 >> 0)
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#define PPD7D_CPLD_FLASH_CNTL_WR_LINK_FITTED (0x80 >> 0)
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#define PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK (0x80 >> 2)
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#define PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_FITTED (0x80 >> 2)
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#define PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK (0x80 >> 3)
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#define PPD7D_CPLD_FLASH_CNTL_USER_LINK_FITTED (0x80 >> 3)
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#define PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK (0x80 >> 5)
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#define PPD7D_CPLD_FLASH_CNTL_RECO_WR_ENABLED (0x80 >> 5)
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#define PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK (0x80 >> 6)
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#define PPD7D_CPLD_FLASH_CNTL_BOOT_WR_ENABLED (0x80 >> 6)
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#define PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK (0x80 >> 7)
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#define PPD7D_CPLD_FLASH_CNTL_USER_WR_ENABLED (0x80 >> 7)
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/* CPLD_SW_FLASH_WRITE_PROTECT */
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#define PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED (!0)
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#define PPC7D_CPLD_SW_FLASH_WRPROT_DISABLED (0)
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#define PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK (0x80 >> 6)
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#define PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK (0x80 >> 7)
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/* CPLD_FLASH_WRITE_CNTL */
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#define PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK (0x80 >> 0)
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#define PPC7D_CPLD_FLASH_CNTL_NVRAM_DISABLED (0 >> 0)
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#define PPC7D_CPLD_FLASH_CNTL_NVRAM_ENABLED (0x80 >> 0)
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#define PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK (0x80 >> 1)
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#define PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK (0x80 >> 2)
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#define PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK (0x80 >> 3)
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#endif /* __PPC_PLATFORMS_PPC7D_H */
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