mirror of https://gitee.com/openkylin/linux.git
866 lines
22 KiB
C
866 lines
22 KiB
C
/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include <linux/perf_event.h>
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#include <linux/pm_runtime.h>
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#include "i915_drv.h"
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#include "i915_pmu.h"
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#include "intel_ringbuffer.h"
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/* Frequency for the sampling timer for events which need it. */
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#define FREQUENCY 200
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#define PERIOD max_t(u64, 10000, NSEC_PER_SEC / FREQUENCY)
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#define ENGINE_SAMPLE_MASK \
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(BIT(I915_SAMPLE_BUSY) | \
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BIT(I915_SAMPLE_WAIT) | \
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BIT(I915_SAMPLE_SEMA))
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#define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS)
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static cpumask_t i915_pmu_cpumask;
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static u8 engine_config_sample(u64 config)
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{
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return config & I915_PMU_SAMPLE_MASK;
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}
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static u8 engine_event_sample(struct perf_event *event)
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{
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return engine_config_sample(event->attr.config);
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}
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static u8 engine_event_class(struct perf_event *event)
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{
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return (event->attr.config >> I915_PMU_CLASS_SHIFT) & 0xff;
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}
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static u8 engine_event_instance(struct perf_event *event)
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{
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return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
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}
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static bool is_engine_config(u64 config)
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{
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return config < __I915_PMU_OTHER(0);
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}
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static unsigned int config_enabled_bit(u64 config)
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{
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if (is_engine_config(config))
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return engine_config_sample(config);
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else
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return ENGINE_SAMPLE_BITS + (config - __I915_PMU_OTHER(0));
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}
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static u64 config_enabled_mask(u64 config)
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{
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return BIT_ULL(config_enabled_bit(config));
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}
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static bool is_engine_event(struct perf_event *event)
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{
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return is_engine_config(event->attr.config);
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}
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static unsigned int event_enabled_bit(struct perf_event *event)
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{
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return config_enabled_bit(event->attr.config);
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}
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static bool pmu_needs_timer(struct drm_i915_private *i915, bool gpu_active)
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{
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u64 enable;
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/*
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* Only some counters need the sampling timer.
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*
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* We start with a bitmask of all currently enabled events.
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*/
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enable = i915->pmu.enable;
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/*
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* Mask out all the ones which do not need the timer, or in
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* other words keep all the ones that could need the timer.
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*/
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enable &= config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY) |
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config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY) |
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ENGINE_SAMPLE_MASK;
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/*
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* When the GPU is idle per-engine counters do not need to be
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* running so clear those bits out.
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*/
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if (!gpu_active)
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enable &= ~ENGINE_SAMPLE_MASK;
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/*
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* Also there is software busyness tracking available we do not
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* need the timer for I915_SAMPLE_BUSY counter.
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*
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* Use RCS as proxy for all engines.
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*/
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else if (intel_engine_supports_stats(i915->engine[RCS]))
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enable &= ~BIT(I915_SAMPLE_BUSY);
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/*
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* If some bits remain it means we need the sampling timer running.
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*/
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return enable;
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}
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void i915_pmu_gt_parked(struct drm_i915_private *i915)
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{
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if (!i915->pmu.base.event_init)
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return;
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spin_lock_irq(&i915->pmu.lock);
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/*
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* Signal sampling timer to stop if only engine events are enabled and
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* GPU went idle.
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*/
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i915->pmu.timer_enabled = pmu_needs_timer(i915, false);
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spin_unlock_irq(&i915->pmu.lock);
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}
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static void __i915_pmu_maybe_start_timer(struct drm_i915_private *i915)
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{
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if (!i915->pmu.timer_enabled && pmu_needs_timer(i915, true)) {
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i915->pmu.timer_enabled = true;
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hrtimer_start_range_ns(&i915->pmu.timer,
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ns_to_ktime(PERIOD), 0,
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HRTIMER_MODE_REL_PINNED);
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}
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}
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void i915_pmu_gt_unparked(struct drm_i915_private *i915)
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{
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if (!i915->pmu.base.event_init)
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return;
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spin_lock_irq(&i915->pmu.lock);
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/*
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* Re-enable sampling timer when GPU goes active.
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*/
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__i915_pmu_maybe_start_timer(i915);
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spin_unlock_irq(&i915->pmu.lock);
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}
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static bool grab_forcewake(struct drm_i915_private *i915, bool fw)
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{
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if (!fw)
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intel_uncore_forcewake_get(i915, FORCEWAKE_ALL);
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return true;
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}
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static void
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update_sample(struct i915_pmu_sample *sample, u32 unit, u32 val)
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{
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sample->cur += mul_u32_u32(val, unit);
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}
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static void engines_sample(struct drm_i915_private *dev_priv)
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{
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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bool fw = false;
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if ((dev_priv->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
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return;
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if (!dev_priv->gt.awake)
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return;
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if (!intel_runtime_pm_get_if_in_use(dev_priv))
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return;
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for_each_engine(engine, dev_priv, id) {
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u32 current_seqno = intel_engine_get_seqno(engine);
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u32 last_seqno = intel_engine_last_submit(engine);
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u32 val;
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val = !i915_seqno_passed(current_seqno, last_seqno);
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update_sample(&engine->pmu.sample[I915_SAMPLE_BUSY],
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PERIOD, val);
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if (val && (engine->pmu.enable &
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(BIT(I915_SAMPLE_WAIT) | BIT(I915_SAMPLE_SEMA)))) {
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fw = grab_forcewake(dev_priv, fw);
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val = I915_READ_FW(RING_CTL(engine->mmio_base));
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} else {
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val = 0;
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}
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update_sample(&engine->pmu.sample[I915_SAMPLE_WAIT],
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PERIOD, !!(val & RING_WAIT));
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update_sample(&engine->pmu.sample[I915_SAMPLE_SEMA],
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PERIOD, !!(val & RING_WAIT_SEMAPHORE));
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}
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if (fw)
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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intel_runtime_pm_put(dev_priv);
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}
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static void frequency_sample(struct drm_i915_private *dev_priv)
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{
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if (dev_priv->pmu.enable &
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config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY)) {
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u32 val;
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val = dev_priv->gt_pm.rps.cur_freq;
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if (dev_priv->gt.awake &&
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intel_runtime_pm_get_if_in_use(dev_priv)) {
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val = intel_get_cagf(dev_priv,
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I915_READ_NOTRACE(GEN6_RPSTAT1));
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intel_runtime_pm_put(dev_priv);
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}
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update_sample(&dev_priv->pmu.sample[__I915_SAMPLE_FREQ_ACT],
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1, intel_gpu_freq(dev_priv, val));
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}
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if (dev_priv->pmu.enable &
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config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY)) {
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update_sample(&dev_priv->pmu.sample[__I915_SAMPLE_FREQ_REQ], 1,
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intel_gpu_freq(dev_priv,
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dev_priv->gt_pm.rps.cur_freq));
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}
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}
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static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer)
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{
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struct drm_i915_private *i915 =
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container_of(hrtimer, struct drm_i915_private, pmu.timer);
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if (!READ_ONCE(i915->pmu.timer_enabled))
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return HRTIMER_NORESTART;
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engines_sample(i915);
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frequency_sample(i915);
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hrtimer_forward_now(hrtimer, ns_to_ktime(PERIOD));
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return HRTIMER_RESTART;
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}
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static u64 count_interrupts(struct drm_i915_private *i915)
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{
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/* open-coded kstat_irqs() */
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struct irq_desc *desc = irq_to_desc(i915->drm.pdev->irq);
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u64 sum = 0;
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int cpu;
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if (!desc || !desc->kstat_irqs)
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return 0;
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for_each_possible_cpu(cpu)
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sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
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return sum;
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}
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static void i915_pmu_event_destroy(struct perf_event *event)
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{
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WARN_ON(event->parent);
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}
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static int engine_event_init(struct perf_event *event)
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{
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struct drm_i915_private *i915 =
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container_of(event->pmu, typeof(*i915), pmu.base);
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if (!intel_engine_lookup_user(i915, engine_event_class(event),
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engine_event_instance(event)))
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return -ENODEV;
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switch (engine_event_sample(event)) {
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case I915_SAMPLE_BUSY:
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case I915_SAMPLE_WAIT:
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break;
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case I915_SAMPLE_SEMA:
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if (INTEL_GEN(i915) < 6)
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return -ENODEV;
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break;
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default:
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return -ENOENT;
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}
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return 0;
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}
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static int i915_pmu_event_init(struct perf_event *event)
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{
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struct drm_i915_private *i915 =
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container_of(event->pmu, typeof(*i915), pmu.base);
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int ret;
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if (event->attr.type != event->pmu->type)
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return -ENOENT;
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/* unsupported modes and filters */
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if (event->attr.sample_period) /* no sampling */
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return -EINVAL;
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if (has_branch_stack(event))
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return -EOPNOTSUPP;
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if (event->cpu < 0)
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return -EINVAL;
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/* only allow running on one cpu at a time */
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if (!cpumask_test_cpu(event->cpu, &i915_pmu_cpumask))
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return -EINVAL;
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if (is_engine_event(event)) {
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ret = engine_event_init(event);
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} else {
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ret = 0;
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switch (event->attr.config) {
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case I915_PMU_ACTUAL_FREQUENCY:
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if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
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/* Requires a mutex for sampling! */
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ret = -ENODEV;
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case I915_PMU_REQUESTED_FREQUENCY:
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if (INTEL_GEN(i915) < 6)
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ret = -ENODEV;
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break;
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case I915_PMU_INTERRUPTS:
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break;
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case I915_PMU_RC6_RESIDENCY:
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if (!HAS_RC6(i915))
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ret = -ENODEV;
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break;
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default:
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ret = -ENOENT;
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break;
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}
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}
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if (ret)
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return ret;
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if (!event->parent)
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event->destroy = i915_pmu_event_destroy;
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return 0;
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}
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static u64 __i915_pmu_event_read(struct perf_event *event)
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{
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struct drm_i915_private *i915 =
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container_of(event->pmu, typeof(*i915), pmu.base);
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u64 val = 0;
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if (is_engine_event(event)) {
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u8 sample = engine_event_sample(event);
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struct intel_engine_cs *engine;
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engine = intel_engine_lookup_user(i915,
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engine_event_class(event),
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engine_event_instance(event));
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if (WARN_ON_ONCE(!engine)) {
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/* Do nothing */
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} else if (sample == I915_SAMPLE_BUSY &&
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engine->pmu.busy_stats) {
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val = ktime_to_ns(intel_engine_get_busy_time(engine));
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} else {
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val = engine->pmu.sample[sample].cur;
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}
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} else {
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switch (event->attr.config) {
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case I915_PMU_ACTUAL_FREQUENCY:
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val =
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div_u64(i915->pmu.sample[__I915_SAMPLE_FREQ_ACT].cur,
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FREQUENCY);
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break;
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case I915_PMU_REQUESTED_FREQUENCY:
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val =
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div_u64(i915->pmu.sample[__I915_SAMPLE_FREQ_REQ].cur,
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FREQUENCY);
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break;
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case I915_PMU_INTERRUPTS:
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val = count_interrupts(i915);
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break;
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case I915_PMU_RC6_RESIDENCY:
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intel_runtime_pm_get(i915);
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val = intel_rc6_residency_ns(i915,
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IS_VALLEYVIEW(i915) ?
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VLV_GT_RENDER_RC6 :
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GEN6_GT_GFX_RC6);
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if (HAS_RC6p(i915))
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val += intel_rc6_residency_ns(i915,
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GEN6_GT_GFX_RC6p);
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if (HAS_RC6pp(i915))
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val += intel_rc6_residency_ns(i915,
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GEN6_GT_GFX_RC6pp);
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intel_runtime_pm_put(i915);
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break;
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}
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}
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return val;
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}
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static void i915_pmu_event_read(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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u64 prev, new;
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again:
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prev = local64_read(&hwc->prev_count);
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new = __i915_pmu_event_read(event);
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if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
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goto again;
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local64_add(new - prev, &event->count);
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}
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static bool engine_needs_busy_stats(struct intel_engine_cs *engine)
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{
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return intel_engine_supports_stats(engine) &&
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(engine->pmu.enable & BIT(I915_SAMPLE_BUSY));
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}
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static void i915_pmu_enable(struct perf_event *event)
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{
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struct drm_i915_private *i915 =
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container_of(event->pmu, typeof(*i915), pmu.base);
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unsigned int bit = event_enabled_bit(event);
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unsigned long flags;
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spin_lock_irqsave(&i915->pmu.lock, flags);
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/*
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* Update the bitmask of enabled events and increment
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* the event reference counter.
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*/
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GEM_BUG_ON(bit >= I915_PMU_MASK_BITS);
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GEM_BUG_ON(i915->pmu.enable_count[bit] == ~0);
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i915->pmu.enable |= BIT_ULL(bit);
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i915->pmu.enable_count[bit]++;
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/*
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* Start the sampling timer if needed and not already enabled.
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*/
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__i915_pmu_maybe_start_timer(i915);
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/*
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* For per-engine events the bitmask and reference counting
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* is stored per engine.
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*/
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if (is_engine_event(event)) {
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u8 sample = engine_event_sample(event);
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struct intel_engine_cs *engine;
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engine = intel_engine_lookup_user(i915,
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engine_event_class(event),
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engine_event_instance(event));
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GEM_BUG_ON(!engine);
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engine->pmu.enable |= BIT(sample);
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GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);
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GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
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if (engine->pmu.enable_count[sample]++ == 0) {
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/*
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* Enable engine busy stats tracking if needed or
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* alternatively cancel the scheduled disable.
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*
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* If the delayed disable was pending, cancel it and
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* in this case do not enable since it already is.
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*/
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if (engine_needs_busy_stats(engine) &&
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!engine->pmu.busy_stats) {
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engine->pmu.busy_stats = true;
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if (!cancel_delayed_work(&engine->pmu.disable_busy_stats))
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intel_enable_engine_stats(engine);
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}
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}
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}
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/*
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* Store the current counter value so we can report the correct delta
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* for all listeners. Even when the event was already enabled and has
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* an existing non-zero value.
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*/
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local64_set(&event->hw.prev_count, __i915_pmu_event_read(event));
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spin_unlock_irqrestore(&i915->pmu.lock, flags);
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}
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static void __disable_busy_stats(struct work_struct *work)
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{
|
|
struct intel_engine_cs *engine =
|
|
container_of(work, typeof(*engine), pmu.disable_busy_stats.work);
|
|
|
|
intel_disable_engine_stats(engine);
|
|
}
|
|
|
|
static void i915_pmu_disable(struct perf_event *event)
|
|
{
|
|
struct drm_i915_private *i915 =
|
|
container_of(event->pmu, typeof(*i915), pmu.base);
|
|
unsigned int bit = event_enabled_bit(event);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&i915->pmu.lock, flags);
|
|
|
|
if (is_engine_event(event)) {
|
|
u8 sample = engine_event_sample(event);
|
|
struct intel_engine_cs *engine;
|
|
|
|
engine = intel_engine_lookup_user(i915,
|
|
engine_event_class(event),
|
|
engine_event_instance(event));
|
|
GEM_BUG_ON(!engine);
|
|
GEM_BUG_ON(sample >= I915_PMU_SAMPLE_BITS);
|
|
GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
|
|
/*
|
|
* Decrement the reference count and clear the enabled
|
|
* bitmask when the last listener on an event goes away.
|
|
*/
|
|
if (--engine->pmu.enable_count[sample] == 0) {
|
|
engine->pmu.enable &= ~BIT(sample);
|
|
if (!engine_needs_busy_stats(engine) &&
|
|
engine->pmu.busy_stats) {
|
|
engine->pmu.busy_stats = false;
|
|
/*
|
|
* We request a delayed disable to handle the
|
|
* rapid on/off cycles on events, which can
|
|
* happen when tools like perf stat start, in a
|
|
* nicer way.
|
|
*
|
|
* In addition, this also helps with busy stats
|
|
* accuracy with background CPU offline/online
|
|
* migration events.
|
|
*/
|
|
queue_delayed_work(system_wq,
|
|
&engine->pmu.disable_busy_stats,
|
|
round_jiffies_up_relative(HZ));
|
|
}
|
|
}
|
|
}
|
|
|
|
GEM_BUG_ON(bit >= I915_PMU_MASK_BITS);
|
|
GEM_BUG_ON(i915->pmu.enable_count[bit] == 0);
|
|
/*
|
|
* Decrement the reference count and clear the enabled
|
|
* bitmask when the last listener on an event goes away.
|
|
*/
|
|
if (--i915->pmu.enable_count[bit] == 0) {
|
|
i915->pmu.enable &= ~BIT_ULL(bit);
|
|
i915->pmu.timer_enabled &= pmu_needs_timer(i915, true);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&i915->pmu.lock, flags);
|
|
}
|
|
|
|
static void i915_pmu_event_start(struct perf_event *event, int flags)
|
|
{
|
|
i915_pmu_enable(event);
|
|
event->hw.state = 0;
|
|
}
|
|
|
|
static void i915_pmu_event_stop(struct perf_event *event, int flags)
|
|
{
|
|
if (flags & PERF_EF_UPDATE)
|
|
i915_pmu_event_read(event);
|
|
i915_pmu_disable(event);
|
|
event->hw.state = PERF_HES_STOPPED;
|
|
}
|
|
|
|
static int i915_pmu_event_add(struct perf_event *event, int flags)
|
|
{
|
|
if (flags & PERF_EF_START)
|
|
i915_pmu_event_start(event, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void i915_pmu_event_del(struct perf_event *event, int flags)
|
|
{
|
|
i915_pmu_event_stop(event, PERF_EF_UPDATE);
|
|
}
|
|
|
|
static int i915_pmu_event_event_idx(struct perf_event *event)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
struct i915_str_attribute {
|
|
struct device_attribute attr;
|
|
const char *str;
|
|
};
|
|
|
|
static ssize_t i915_pmu_format_show(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
struct i915_str_attribute *eattr;
|
|
|
|
eattr = container_of(attr, struct i915_str_attribute, attr);
|
|
return sprintf(buf, "%s\n", eattr->str);
|
|
}
|
|
|
|
#define I915_PMU_FORMAT_ATTR(_name, _config) \
|
|
(&((struct i915_str_attribute[]) { \
|
|
{ .attr = __ATTR(_name, 0444, i915_pmu_format_show, NULL), \
|
|
.str = _config, } \
|
|
})[0].attr.attr)
|
|
|
|
static struct attribute *i915_pmu_format_attrs[] = {
|
|
I915_PMU_FORMAT_ATTR(i915_eventid, "config:0-20"),
|
|
NULL,
|
|
};
|
|
|
|
static const struct attribute_group i915_pmu_format_attr_group = {
|
|
.name = "format",
|
|
.attrs = i915_pmu_format_attrs,
|
|
};
|
|
|
|
struct i915_ext_attribute {
|
|
struct device_attribute attr;
|
|
unsigned long val;
|
|
};
|
|
|
|
static ssize_t i915_pmu_event_show(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
struct i915_ext_attribute *eattr;
|
|
|
|
eattr = container_of(attr, struct i915_ext_attribute, attr);
|
|
return sprintf(buf, "config=0x%lx\n", eattr->val);
|
|
}
|
|
|
|
#define I915_EVENT_ATTR(_name, _config) \
|
|
(&((struct i915_ext_attribute[]) { \
|
|
{ .attr = __ATTR(_name, 0444, i915_pmu_event_show, NULL), \
|
|
.val = _config, } \
|
|
})[0].attr.attr)
|
|
|
|
#define I915_EVENT_STR(_name, _str) \
|
|
(&((struct perf_pmu_events_attr[]) { \
|
|
{ .attr = __ATTR(_name, 0444, perf_event_sysfs_show, NULL), \
|
|
.id = 0, \
|
|
.event_str = _str, } \
|
|
})[0].attr.attr)
|
|
|
|
#define I915_EVENT(_name, _config, _unit) \
|
|
I915_EVENT_ATTR(_name, _config), \
|
|
I915_EVENT_STR(_name.unit, _unit)
|
|
|
|
#define I915_ENGINE_EVENT(_name, _class, _instance, _sample) \
|
|
I915_EVENT_ATTR(_name, __I915_PMU_ENGINE(_class, _instance, _sample)), \
|
|
I915_EVENT_STR(_name.unit, "ns")
|
|
|
|
#define I915_ENGINE_EVENTS(_name, _class, _instance) \
|
|
I915_ENGINE_EVENT(_name##_instance-busy, _class, _instance, I915_SAMPLE_BUSY), \
|
|
I915_ENGINE_EVENT(_name##_instance-sema, _class, _instance, I915_SAMPLE_SEMA), \
|
|
I915_ENGINE_EVENT(_name##_instance-wait, _class, _instance, I915_SAMPLE_WAIT)
|
|
|
|
static struct attribute *i915_pmu_events_attrs[] = {
|
|
I915_ENGINE_EVENTS(rcs, I915_ENGINE_CLASS_RENDER, 0),
|
|
I915_ENGINE_EVENTS(bcs, I915_ENGINE_CLASS_COPY, 0),
|
|
I915_ENGINE_EVENTS(vcs, I915_ENGINE_CLASS_VIDEO, 0),
|
|
I915_ENGINE_EVENTS(vcs, I915_ENGINE_CLASS_VIDEO, 1),
|
|
I915_ENGINE_EVENTS(vecs, I915_ENGINE_CLASS_VIDEO_ENHANCE, 0),
|
|
|
|
I915_EVENT(actual-frequency, I915_PMU_ACTUAL_FREQUENCY, "MHz"),
|
|
I915_EVENT(requested-frequency, I915_PMU_REQUESTED_FREQUENCY, "MHz"),
|
|
|
|
I915_EVENT_ATTR(interrupts, I915_PMU_INTERRUPTS),
|
|
|
|
I915_EVENT(rc6-residency, I915_PMU_RC6_RESIDENCY, "ns"),
|
|
|
|
NULL,
|
|
};
|
|
|
|
static const struct attribute_group i915_pmu_events_attr_group = {
|
|
.name = "events",
|
|
.attrs = i915_pmu_events_attrs,
|
|
};
|
|
|
|
static ssize_t
|
|
i915_pmu_get_attr_cpumask(struct device *dev,
|
|
struct device_attribute *attr,
|
|
char *buf)
|
|
{
|
|
return cpumap_print_to_pagebuf(true, buf, &i915_pmu_cpumask);
|
|
}
|
|
|
|
static DEVICE_ATTR(cpumask, 0444, i915_pmu_get_attr_cpumask, NULL);
|
|
|
|
static struct attribute *i915_cpumask_attrs[] = {
|
|
&dev_attr_cpumask.attr,
|
|
NULL,
|
|
};
|
|
|
|
static struct attribute_group i915_pmu_cpumask_attr_group = {
|
|
.attrs = i915_cpumask_attrs,
|
|
};
|
|
|
|
static const struct attribute_group *i915_pmu_attr_groups[] = {
|
|
&i915_pmu_format_attr_group,
|
|
&i915_pmu_events_attr_group,
|
|
&i915_pmu_cpumask_attr_group,
|
|
NULL
|
|
};
|
|
|
|
static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
|
|
{
|
|
struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node);
|
|
|
|
GEM_BUG_ON(!pmu->base.event_init);
|
|
|
|
/* Select the first online CPU as a designated reader. */
|
|
if (!cpumask_weight(&i915_pmu_cpumask))
|
|
cpumask_set_cpu(cpu, &i915_pmu_cpumask);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
|
|
{
|
|
struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), node);
|
|
unsigned int target;
|
|
|
|
GEM_BUG_ON(!pmu->base.event_init);
|
|
|
|
if (cpumask_test_and_clear_cpu(cpu, &i915_pmu_cpumask)) {
|
|
target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
|
|
/* Migrate events if there is a valid target */
|
|
if (target < nr_cpu_ids) {
|
|
cpumask_set_cpu(target, &i915_pmu_cpumask);
|
|
perf_pmu_migrate_context(&pmu->base, cpu, target);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
|
|
|
|
static int i915_pmu_register_cpuhp_state(struct drm_i915_private *i915)
|
|
{
|
|
enum cpuhp_state slot;
|
|
int ret;
|
|
|
|
ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
|
|
"perf/x86/intel/i915:online",
|
|
i915_pmu_cpu_online,
|
|
i915_pmu_cpu_offline);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
slot = ret;
|
|
ret = cpuhp_state_add_instance(slot, &i915->pmu.node);
|
|
if (ret) {
|
|
cpuhp_remove_multi_state(slot);
|
|
return ret;
|
|
}
|
|
|
|
cpuhp_slot = slot;
|
|
return 0;
|
|
}
|
|
|
|
static void i915_pmu_unregister_cpuhp_state(struct drm_i915_private *i915)
|
|
{
|
|
WARN_ON(cpuhp_slot == CPUHP_INVALID);
|
|
WARN_ON(cpuhp_state_remove_instance(cpuhp_slot, &i915->pmu.node));
|
|
cpuhp_remove_multi_state(cpuhp_slot);
|
|
}
|
|
|
|
void i915_pmu_register(struct drm_i915_private *i915)
|
|
{
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
int ret;
|
|
|
|
if (INTEL_GEN(i915) <= 2) {
|
|
DRM_INFO("PMU not supported for this GPU.");
|
|
return;
|
|
}
|
|
|
|
i915->pmu.base.attr_groups = i915_pmu_attr_groups;
|
|
i915->pmu.base.task_ctx_nr = perf_invalid_context;
|
|
i915->pmu.base.event_init = i915_pmu_event_init;
|
|
i915->pmu.base.add = i915_pmu_event_add;
|
|
i915->pmu.base.del = i915_pmu_event_del;
|
|
i915->pmu.base.start = i915_pmu_event_start;
|
|
i915->pmu.base.stop = i915_pmu_event_stop;
|
|
i915->pmu.base.read = i915_pmu_event_read;
|
|
i915->pmu.base.event_idx = i915_pmu_event_event_idx;
|
|
|
|
spin_lock_init(&i915->pmu.lock);
|
|
hrtimer_init(&i915->pmu.timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
|
|
i915->pmu.timer.function = i915_sample;
|
|
|
|
for_each_engine(engine, i915, id)
|
|
INIT_DELAYED_WORK(&engine->pmu.disable_busy_stats,
|
|
__disable_busy_stats);
|
|
|
|
ret = perf_pmu_register(&i915->pmu.base, "i915", -1);
|
|
if (ret)
|
|
goto err;
|
|
|
|
ret = i915_pmu_register_cpuhp_state(i915);
|
|
if (ret)
|
|
goto err_unreg;
|
|
|
|
return;
|
|
|
|
err_unreg:
|
|
perf_pmu_unregister(&i915->pmu.base);
|
|
err:
|
|
i915->pmu.base.event_init = NULL;
|
|
DRM_NOTE("Failed to register PMU! (err=%d)\n", ret);
|
|
}
|
|
|
|
void i915_pmu_unregister(struct drm_i915_private *i915)
|
|
{
|
|
struct intel_engine_cs *engine;
|
|
enum intel_engine_id id;
|
|
|
|
if (!i915->pmu.base.event_init)
|
|
return;
|
|
|
|
WARN_ON(i915->pmu.enable);
|
|
|
|
hrtimer_cancel(&i915->pmu.timer);
|
|
|
|
for_each_engine(engine, i915, id) {
|
|
GEM_BUG_ON(engine->pmu.busy_stats);
|
|
flush_delayed_work(&engine->pmu.disable_busy_stats);
|
|
}
|
|
|
|
i915_pmu_unregister_cpuhp_state(i915);
|
|
|
|
perf_pmu_unregister(&i915->pmu.base);
|
|
i915->pmu.base.event_init = NULL;
|
|
}
|