mirror of https://gitee.com/openkylin/linux.git
1391 lines
34 KiB
C
1391 lines
34 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Hardware modules present on the DRA7xx chips
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
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*
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* Paul Walmsley
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* Benoit Cousson
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*/
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#include <linux/io.h>
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#include "omap_hwmod.h"
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#include "omap_hwmod_common_data.h"
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#include "cm1_7xx.h"
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#include "cm2_7xx.h"
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#include "prm7xx.h"
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#include "soc.h"
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/* Base offset for all DRA7XX interrupts external to MPUSS */
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#define DRA7XX_IRQ_GIC_START 32
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/*
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* IP blocks
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*/
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/*
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* 'dmm' class
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* instance(s): dmm
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*/
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static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
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.name = "dmm",
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};
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/* dmm */
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static struct omap_hwmod dra7xx_dmm_hwmod = {
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.name = "dmm",
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.class = &dra7xx_dmm_hwmod_class,
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.clkdm_name = "emif_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
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},
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},
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};
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/*
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* 'l3' class
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* instance(s): l3_instr, l3_main_1, l3_main_2
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*/
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static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
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.name = "l3",
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};
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/* l3_instr */
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static struct omap_hwmod dra7xx_l3_instr_hwmod = {
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.name = "l3_instr",
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.class = &dra7xx_l3_hwmod_class,
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.clkdm_name = "l3instr_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/* l3_main_1 */
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static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
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.name = "l3_main_1",
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.class = &dra7xx_l3_hwmod_class,
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.clkdm_name = "l3main1_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
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},
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},
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};
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/* l3_main_2 */
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static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
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.name = "l3_main_2",
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.class = &dra7xx_l3_hwmod_class,
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.clkdm_name = "l3instr_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/*
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* 'l4' class
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* instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
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*/
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static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
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.name = "l4",
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};
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/* l4_cfg */
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static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
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.name = "l4_cfg",
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.class = &dra7xx_l4_hwmod_class,
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.clkdm_name = "l4cfg_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
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},
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},
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};
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/* l4_per1 */
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static struct omap_hwmod dra7xx_l4_per1_hwmod = {
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.name = "l4_per1",
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.class = &dra7xx_l4_hwmod_class,
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.clkdm_name = "l4per_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
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},
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},
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};
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/* l4_per2 */
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static struct omap_hwmod dra7xx_l4_per2_hwmod = {
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.name = "l4_per2",
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.class = &dra7xx_l4_hwmod_class,
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.clkdm_name = "l4per2_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
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},
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},
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};
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/* l4_per3 */
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static struct omap_hwmod dra7xx_l4_per3_hwmod = {
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.name = "l4_per3",
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.class = &dra7xx_l4_hwmod_class,
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.clkdm_name = "l4per3_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
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},
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},
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};
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/* l4_wkup */
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static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
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.name = "l4_wkup",
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.class = &dra7xx_l4_hwmod_class,
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.clkdm_name = "wkupaon_clkdm",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
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},
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},
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};
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/*
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* 'atl' class
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*
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*/
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static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
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.name = "atl",
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};
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/* atl */
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static struct omap_hwmod dra7xx_atl_hwmod = {
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.name = "atl",
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.class = &dra7xx_atl_hwmod_class,
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.clkdm_name = "atl_clkdm",
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.main_clk = "atl_gfclk_mux",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'bb2d' class
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*
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*/
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static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
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.name = "bb2d",
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};
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/* bb2d */
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static struct omap_hwmod dra7xx_bb2d_hwmod = {
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.name = "bb2d",
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.class = &dra7xx_bb2d_hwmod_class,
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.clkdm_name = "dss_clkdm",
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.main_clk = "dpll_core_h24x2_ck",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/*
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* 'counter' class
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*
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*/
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static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.sysc_flags = SYSC_HAS_SIDLEMODE,
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
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.name = "counter",
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.sysc = &dra7xx_counter_sysc,
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};
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/* counter_32k */
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static struct omap_hwmod dra7xx_counter_32k_hwmod = {
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.name = "counter_32k",
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.class = &dra7xx_counter_hwmod_class,
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.clkdm_name = "wkupaon_clkdm",
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.flags = HWMOD_SWSUP_SIDLE,
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.main_clk = "wkupaon_iclk_mux",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
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},
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},
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};
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/*
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* 'ctrl_module' class
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*
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*/
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static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
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.name = "ctrl_module",
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};
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/* ctrl_module_wkup */
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static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
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.name = "ctrl_module_wkup",
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.class = &dra7xx_ctrl_module_hwmod_class,
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.clkdm_name = "wkupaon_clkdm",
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.prcm = {
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.omap4 = {
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
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},
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},
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};
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/*
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* 'tpcc' class
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*
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*/
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static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
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.name = "tpcc",
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};
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static struct omap_hwmod dra7xx_tpcc_hwmod = {
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.name = "tpcc",
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.class = &dra7xx_tpcc_hwmod_class,
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.clkdm_name = "l3main1_clkdm",
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.main_clk = "l3_iclk_div",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
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},
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},
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};
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/*
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* 'tptc' class
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*
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*/
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static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
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.name = "tptc",
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};
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/* tptc0 */
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static struct omap_hwmod dra7xx_tptc0_hwmod = {
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.name = "tptc0",
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.class = &dra7xx_tptc_hwmod_class,
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.clkdm_name = "l3main1_clkdm",
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.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
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.main_clk = "l3_iclk_div",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/* tptc1 */
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static struct omap_hwmod dra7xx_tptc1_hwmod = {
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.name = "tptc1",
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.class = &dra7xx_tptc_hwmod_class,
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.clkdm_name = "l3main1_clkdm",
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.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
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.main_clk = "l3_iclk_div",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_HWCTRL,
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},
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},
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};
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/*
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* 'dss' class
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*
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*/
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static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
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.rev_offs = 0x0000,
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.syss_offs = 0x0014,
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.sysc_flags = SYSS_HAS_RESET_STATUS,
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};
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static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
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.name = "dss",
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.sysc = &dra7xx_dss_sysc,
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.reset = omap_dss_reset,
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};
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/* dss */
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static struct omap_hwmod_opt_clk dss_opt_clks[] = {
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{ .role = "dss_clk", .clk = "dss_dss_clk" },
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{ .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
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{ .role = "32khz_clk", .clk = "dss_32khz_clk" },
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{ .role = "video2_clk", .clk = "dss_video2_clk" },
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{ .role = "video1_clk", .clk = "dss_video1_clk" },
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{ .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
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{ .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
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};
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static struct omap_hwmod dra7xx_dss_hwmod = {
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.name = "dss_core",
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.class = &dra7xx_dss_hwmod_class,
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.clkdm_name = "dss_clkdm",
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
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.main_clk = "dss_dss_clk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
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.context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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.opt_clks = dss_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
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};
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/*
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* 'dispc' class
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* display controller
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*/
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static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
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SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
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SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
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.name = "dispc",
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.sysc = &dra7xx_dispc_sysc,
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};
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/* dss_dispc */
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/* dss_dispc dev_attr */
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static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
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.has_framedonetv_irq = 1,
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.manager_count = 4,
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};
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static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
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.name = "dss_dispc",
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.class = &dra7xx_dispc_hwmod_class,
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.clkdm_name = "dss_clkdm",
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.main_clk = "dss_dss_clk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
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},
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},
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.dev_attr = &dss_dispc_dev_attr,
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.parent_hwmod = &dra7xx_dss_hwmod,
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};
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/*
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* 'hdmi' class
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* hdmi controller
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*/
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static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
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.rev_offs = 0x0000,
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.sysc_offs = 0x0010,
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.sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
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SYSC_HAS_SOFTRESET),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type2,
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};
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static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
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.name = "hdmi",
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.sysc = &dra7xx_hdmi_sysc,
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};
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/* dss_hdmi */
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static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
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{ .role = "sys_clk", .clk = "dss_hdmi_clk" },
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};
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static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
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.name = "dss_hdmi",
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.class = &dra7xx_hdmi_hwmod_class,
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.clkdm_name = "dss_clkdm",
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.main_clk = "dss_48mhz_clk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
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.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
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},
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},
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.opt_clks = dss_hdmi_opt_clks,
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.opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
|
|
.parent_hwmod = &dra7xx_dss_hwmod,
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
* 'gpmc' class
|
|
*
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.syss_offs = 0x0014,
|
|
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
|
|
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
|
|
.sysc_fields = &omap_hwmod_sysc_type1,
|
|
};
|
|
|
|
static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
|
|
.name = "gpmc",
|
|
.sysc = &dra7xx_gpmc_sysc,
|
|
};
|
|
|
|
/* gpmc */
|
|
|
|
static struct omap_hwmod dra7xx_gpmc_hwmod = {
|
|
.name = "gpmc",
|
|
.class = &dra7xx_gpmc_hwmod_class,
|
|
.clkdm_name = "l3main1_clkdm",
|
|
/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
|
|
.flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
|
|
.main_clk = "l3_iclk_div",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
* 'mpu' class
|
|
*
|
|
*/
|
|
|
|
static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
|
|
.name = "mpu",
|
|
};
|
|
|
|
/* mpu */
|
|
static struct omap_hwmod dra7xx_mpu_hwmod = {
|
|
.name = "mpu",
|
|
.class = &dra7xx_mpu_hwmod_class,
|
|
.clkdm_name = "mpu_clkdm",
|
|
.flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
|
|
.main_clk = "dpll_mpu_m2_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
|
|
},
|
|
},
|
|
};
|
|
|
|
|
|
/*
|
|
* 'PCIE' class
|
|
*
|
|
*/
|
|
|
|
/*
|
|
* As noted in documentation for _reset() in omap_hwmod.c, the stock reset
|
|
* functionality of OMAP HWMOD layer does not deassert the hardreset lines
|
|
* associated with an IP automatically leaving the driver to handle that
|
|
* by itself. This does not work for PCIeSS which needs the reset lines
|
|
* deasserted for the driver to start accessing registers.
|
|
*
|
|
* We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
|
|
* lines after asserting them.
|
|
*/
|
|
int dra7xx_pciess_reset(struct omap_hwmod *oh)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < oh->rst_lines_cnt; i++) {
|
|
omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
|
|
omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
|
|
.name = "pcie",
|
|
.reset = dra7xx_pciess_reset,
|
|
};
|
|
|
|
/* pcie1 */
|
|
static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
|
|
{ .name = "pcie", .rst_shift = 0 },
|
|
};
|
|
|
|
static struct omap_hwmod dra7xx_pciess1_hwmod = {
|
|
.name = "pcie1",
|
|
.class = &dra7xx_pciess_hwmod_class,
|
|
.clkdm_name = "pcie_clkdm",
|
|
.rst_lines = dra7xx_pciess1_resets,
|
|
.rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
|
|
.main_clk = "l4_root_clk_div",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
|
|
.rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* pcie2 */
|
|
static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
|
|
{ .name = "pcie", .rst_shift = 1 },
|
|
};
|
|
|
|
/* pcie2 */
|
|
static struct omap_hwmod dra7xx_pciess2_hwmod = {
|
|
.name = "pcie2",
|
|
.class = &dra7xx_pciess_hwmod_class,
|
|
.clkdm_name = "pcie_clkdm",
|
|
.rst_lines = dra7xx_pciess2_resets,
|
|
.rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
|
|
.main_clk = "l4_root_clk_div",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
|
|
.rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'qspi' class
|
|
*
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
|
|
.rev_offs = 0,
|
|
.sysc_offs = 0x0010,
|
|
.sysc_flags = SYSC_HAS_SIDLEMODE,
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
|
|
.name = "qspi",
|
|
.sysc = &dra7xx_qspi_sysc,
|
|
};
|
|
|
|
/* qspi */
|
|
static struct omap_hwmod dra7xx_qspi_hwmod = {
|
|
.name = "qspi",
|
|
.class = &dra7xx_qspi_hwmod_class,
|
|
.clkdm_name = "l4per2_clkdm",
|
|
.main_clk = "qspi_gfclk_div",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'rtcss' class
|
|
*
|
|
*/
|
|
static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
|
|
.rev_offs = 0x0074,
|
|
.sysc_offs = 0x0078,
|
|
.sysc_flags = SYSC_HAS_SIDLEMODE,
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type3,
|
|
};
|
|
|
|
static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
|
|
.name = "rtcss",
|
|
.sysc = &dra7xx_rtcss_sysc,
|
|
.unlock = &omap_hwmod_rtc_unlock,
|
|
.lock = &omap_hwmod_rtc_lock,
|
|
};
|
|
|
|
/* rtcss */
|
|
static struct omap_hwmod dra7xx_rtcss_hwmod = {
|
|
.name = "rtcss",
|
|
.class = &dra7xx_rtcss_hwmod_class,
|
|
.clkdm_name = "rtc_clkdm",
|
|
.main_clk = "sys_32k_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'sata' class
|
|
*
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
|
|
.rev_offs = 0x00fc,
|
|
.sysc_offs = 0x0000,
|
|
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
|
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
|
|
.name = "sata",
|
|
.sysc = &dra7xx_sata_sysc,
|
|
};
|
|
|
|
/* sata */
|
|
|
|
static struct omap_hwmod dra7xx_sata_hwmod = {
|
|
.name = "sata",
|
|
.class = &dra7xx_sata_hwmod_class,
|
|
.clkdm_name = "l3init_clkdm",
|
|
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
|
|
.main_clk = "func_48m_fclk",
|
|
.mpu_rt_idx = 1,
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'timer' class
|
|
*
|
|
* This class contains several variants: ['timer_1ms', 'timer_secure',
|
|
* 'timer']
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
|
|
.name = "timer",
|
|
.sysc = &dra7xx_timer_1ms_sysc,
|
|
};
|
|
|
|
static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
|
|
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
|
|
.name = "timer",
|
|
.sysc = &dra7xx_timer_sysc,
|
|
};
|
|
|
|
/* timer1 */
|
|
static struct omap_hwmod dra7xx_timer1_hwmod = {
|
|
.name = "timer1",
|
|
.class = &dra7xx_timer_1ms_hwmod_class,
|
|
.clkdm_name = "wkupaon_clkdm",
|
|
.main_clk = "timer1_gfclk_mux",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* timer2 */
|
|
static struct omap_hwmod dra7xx_timer2_hwmod = {
|
|
.name = "timer2",
|
|
.class = &dra7xx_timer_1ms_hwmod_class,
|
|
.clkdm_name = "l4per_clkdm",
|
|
.main_clk = "timer2_gfclk_mux",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* timer3 */
|
|
static struct omap_hwmod dra7xx_timer3_hwmod = {
|
|
.name = "timer3",
|
|
.class = &dra7xx_timer_hwmod_class,
|
|
.clkdm_name = "l4per_clkdm",
|
|
.main_clk = "timer3_gfclk_mux",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* timer4 */
|
|
static struct omap_hwmod dra7xx_timer4_hwmod = {
|
|
.name = "timer4",
|
|
.class = &dra7xx_timer_hwmod_class,
|
|
.clkdm_name = "l4per_clkdm",
|
|
.main_clk = "timer4_gfclk_mux",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_SWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'usb_otg_ss' class
|
|
*
|
|
*/
|
|
|
|
static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
|
|
.rev_offs = 0x0000,
|
|
.sysc_offs = 0x0010,
|
|
.sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
|
|
SYSC_HAS_SIDLEMODE),
|
|
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
|
MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
|
.sysc_fields = &omap_hwmod_sysc_type2,
|
|
};
|
|
|
|
static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
|
|
.name = "usb_otg_ss",
|
|
.sysc = &dra7xx_usb_otg_ss_sysc,
|
|
};
|
|
|
|
/* usb_otg_ss1 */
|
|
static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
|
|
{ .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
|
|
};
|
|
|
|
static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
|
|
.name = "usb_otg_ss1",
|
|
.class = &dra7xx_usb_otg_ss_hwmod_class,
|
|
.clkdm_name = "l3init_clkdm",
|
|
.main_clk = "dpll_core_h13x2_ck",
|
|
.flags = HWMOD_CLKDM_NOAUTO,
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
},
|
|
},
|
|
.opt_clks = usb_otg_ss1_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
|
|
};
|
|
|
|
/* usb_otg_ss2 */
|
|
static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
|
|
{ .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
|
|
};
|
|
|
|
static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
|
|
.name = "usb_otg_ss2",
|
|
.class = &dra7xx_usb_otg_ss_hwmod_class,
|
|
.clkdm_name = "l3init_clkdm",
|
|
.main_clk = "dpll_core_h13x2_ck",
|
|
.flags = HWMOD_CLKDM_NOAUTO,
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
},
|
|
},
|
|
.opt_clks = usb_otg_ss2_opt_clks,
|
|
.opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
|
|
};
|
|
|
|
/* usb_otg_ss3 */
|
|
static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
|
|
.name = "usb_otg_ss3",
|
|
.class = &dra7xx_usb_otg_ss_hwmod_class,
|
|
.clkdm_name = "l3init_clkdm",
|
|
.main_clk = "dpll_core_h13x2_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* usb_otg_ss4 */
|
|
static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
|
|
.name = "usb_otg_ss4",
|
|
.class = &dra7xx_usb_otg_ss_hwmod_class,
|
|
.clkdm_name = "l3init_clkdm",
|
|
.main_clk = "dpll_core_h13x2_ck",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
|
|
.modulemode = MODULEMODE_HWCTRL,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* 'vcp' class
|
|
*
|
|
*/
|
|
|
|
static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
|
|
.name = "vcp",
|
|
};
|
|
|
|
/* vcp1 */
|
|
static struct omap_hwmod dra7xx_vcp1_hwmod = {
|
|
.name = "vcp1",
|
|
.class = &dra7xx_vcp_hwmod_class,
|
|
.clkdm_name = "l3main1_clkdm",
|
|
.main_clk = "l3_iclk_div",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
|
|
},
|
|
},
|
|
};
|
|
|
|
/* vcp2 */
|
|
static struct omap_hwmod dra7xx_vcp2_hwmod = {
|
|
.name = "vcp2",
|
|
.class = &dra7xx_vcp_hwmod_class,
|
|
.clkdm_name = "l3main1_clkdm",
|
|
.main_clk = "l3_iclk_div",
|
|
.prcm = {
|
|
.omap4 = {
|
|
.clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
|
|
.context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
|
|
},
|
|
},
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
* Interfaces
|
|
*/
|
|
|
|
/* l3_main_1 -> dmm */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_dmm_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_2 -> l3_instr */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
|
|
.master = &dra7xx_l3_main_2_hwmod,
|
|
.slave = &dra7xx_l3_instr_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> l3_main_1 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
|
|
.master = &dra7xx_l4_cfg_hwmod,
|
|
.slave = &dra7xx_l3_main_1_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* mpu -> l3_main_1 */
|
|
static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
|
|
.master = &dra7xx_mpu_hwmod,
|
|
.slave = &dra7xx_l3_main_1_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l3_main_1 -> l3_main_2 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_l3_main_2_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l4_cfg -> l3_main_2 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
|
|
.master = &dra7xx_l4_cfg_hwmod,
|
|
.slave = &dra7xx_l3_main_2_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> l4_cfg */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_l4_cfg_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> l4_per1 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_l4_per1_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> l4_per2 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_l4_per2_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> l4_per3 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_l4_per3_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> l4_wkup */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_l4_wkup_hwmod,
|
|
.clk = "wkupaon_iclk_mux",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per2 -> atl */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
|
|
.master = &dra7xx_l4_per2_hwmod,
|
|
.slave = &dra7xx_atl_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> bb2d */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_bb2d_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> counter_32k */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
|
|
.master = &dra7xx_l4_wkup_hwmod,
|
|
.slave = &dra7xx_counter_32k_hwmod,
|
|
.clk = "wkupaon_iclk_mux",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> ctrl_module_wkup */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
|
|
.master = &dra7xx_l4_wkup_hwmod,
|
|
.slave = &dra7xx_ctrl_module_wkup_hwmod,
|
|
.clk = "wkupaon_iclk_mux",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> tpcc */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_tpcc_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l3_main_1 -> tptc0 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_tptc0_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l3_main_1 -> tptc1 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_tptc1_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU,
|
|
};
|
|
|
|
/* l3_main_1 -> dss */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_dss_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> dispc */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_dss_dispc_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> dispc */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_dss_hdmi_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> gpmc */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_gpmc_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> mpu */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
|
|
.master = &dra7xx_l4_cfg_hwmod,
|
|
.slave = &dra7xx_mpu_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> pciess1 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_pciess1_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> pciess1 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
|
|
.master = &dra7xx_l4_cfg_hwmod,
|
|
.slave = &dra7xx_pciess1_hwmod,
|
|
.clk = "l4_root_clk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> pciess2 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_pciess2_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> pciess2 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
|
|
.master = &dra7xx_l4_cfg_hwmod,
|
|
.slave = &dra7xx_pciess2_hwmod,
|
|
.clk = "l4_root_clk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> qspi */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_qspi_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per3 -> rtcss */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
|
|
.master = &dra7xx_l4_per3_hwmod,
|
|
.slave = &dra7xx_rtcss_hwmod,
|
|
.clk = "l4_root_clk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_cfg -> sata */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
|
|
.master = &dra7xx_l4_cfg_hwmod,
|
|
.slave = &dra7xx_sata_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_wkup -> timer1 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
|
|
.master = &dra7xx_l4_wkup_hwmod,
|
|
.slave = &dra7xx_timer1_hwmod,
|
|
.clk = "wkupaon_iclk_mux",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per1 -> timer2 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
|
|
.master = &dra7xx_l4_per1_hwmod,
|
|
.slave = &dra7xx_timer2_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per1 -> timer3 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
|
|
.master = &dra7xx_l4_per1_hwmod,
|
|
.slave = &dra7xx_timer3_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per1 -> timer4 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
|
|
.master = &dra7xx_l4_per1_hwmod,
|
|
.slave = &dra7xx_timer4_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per3 -> usb_otg_ss1 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
|
|
.master = &dra7xx_l4_per3_hwmod,
|
|
.slave = &dra7xx_usb_otg_ss1_hwmod,
|
|
.clk = "dpll_core_h13x2_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per3 -> usb_otg_ss2 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
|
|
.master = &dra7xx_l4_per3_hwmod,
|
|
.slave = &dra7xx_usb_otg_ss2_hwmod,
|
|
.clk = "dpll_core_h13x2_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per3 -> usb_otg_ss3 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
|
|
.master = &dra7xx_l4_per3_hwmod,
|
|
.slave = &dra7xx_usb_otg_ss3_hwmod,
|
|
.clk = "dpll_core_h13x2_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per3 -> usb_otg_ss4 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
|
|
.master = &dra7xx_l4_per3_hwmod,
|
|
.slave = &dra7xx_usb_otg_ss4_hwmod,
|
|
.clk = "dpll_core_h13x2_ck",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> vcp1 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_vcp1_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per2 -> vcp1 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
|
|
.master = &dra7xx_l4_per2_hwmod,
|
|
.slave = &dra7xx_vcp1_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l3_main_1 -> vcp2 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
|
|
.master = &dra7xx_l3_main_1_hwmod,
|
|
.slave = &dra7xx_vcp2_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
/* l4_per2 -> vcp2 */
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
|
|
.master = &dra7xx_l4_per2_hwmod,
|
|
.slave = &dra7xx_vcp2_hwmod,
|
|
.clk = "l3_iclk_div",
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
|
|
&dra7xx_l3_main_1__dmm,
|
|
&dra7xx_l3_main_2__l3_instr,
|
|
&dra7xx_l4_cfg__l3_main_1,
|
|
&dra7xx_mpu__l3_main_1,
|
|
&dra7xx_l3_main_1__l3_main_2,
|
|
&dra7xx_l4_cfg__l3_main_2,
|
|
&dra7xx_l3_main_1__l4_cfg,
|
|
&dra7xx_l3_main_1__l4_per1,
|
|
&dra7xx_l3_main_1__l4_per2,
|
|
&dra7xx_l3_main_1__l4_per3,
|
|
&dra7xx_l3_main_1__l4_wkup,
|
|
&dra7xx_l4_per2__atl,
|
|
&dra7xx_l3_main_1__bb2d,
|
|
&dra7xx_l4_wkup__counter_32k,
|
|
&dra7xx_l4_wkup__ctrl_module_wkup,
|
|
&dra7xx_l3_main_1__tpcc,
|
|
&dra7xx_l3_main_1__tptc0,
|
|
&dra7xx_l3_main_1__tptc1,
|
|
&dra7xx_l3_main_1__dss,
|
|
&dra7xx_l3_main_1__dispc,
|
|
&dra7xx_l3_main_1__hdmi,
|
|
&dra7xx_l3_main_1__gpmc,
|
|
&dra7xx_l4_cfg__mpu,
|
|
&dra7xx_l3_main_1__pciess1,
|
|
&dra7xx_l4_cfg__pciess1,
|
|
&dra7xx_l3_main_1__pciess2,
|
|
&dra7xx_l4_cfg__pciess2,
|
|
&dra7xx_l3_main_1__qspi,
|
|
&dra7xx_l4_cfg__sata,
|
|
&dra7xx_l4_wkup__timer1,
|
|
&dra7xx_l4_per1__timer2,
|
|
&dra7xx_l4_per1__timer3,
|
|
&dra7xx_l4_per1__timer4,
|
|
&dra7xx_l4_per3__usb_otg_ss1,
|
|
&dra7xx_l4_per3__usb_otg_ss2,
|
|
&dra7xx_l4_per3__usb_otg_ss3,
|
|
&dra7xx_l3_main_1__vcp1,
|
|
&dra7xx_l4_per2__vcp1,
|
|
&dra7xx_l3_main_1__vcp2,
|
|
&dra7xx_l4_per2__vcp2,
|
|
NULL,
|
|
};
|
|
|
|
/* SoC variant specific hwmod links */
|
|
static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
|
|
&dra7xx_l4_per3__usb_otg_ss4,
|
|
NULL,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *acd_76x_hwmod_ocp_ifs[] __initdata = {
|
|
NULL,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
|
|
&dra7xx_l4_per3__usb_otg_ss4,
|
|
NULL,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
|
|
NULL,
|
|
};
|
|
|
|
static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
|
|
&dra7xx_l4_per3__rtcss,
|
|
NULL,
|
|
};
|
|
|
|
int __init dra7xx_hwmod_init(void)
|
|
{
|
|
int ret;
|
|
|
|
omap_hwmod_init();
|
|
ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
|
|
|
|
if (!ret && soc_is_dra74x()) {
|
|
ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
|
|
if (!ret)
|
|
ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
|
|
} else if (!ret && soc_is_dra72x()) {
|
|
ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
|
|
if (!ret && !of_machine_is_compatible("ti,dra718"))
|
|
ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
|
|
} else if (!ret && soc_is_dra76x()) {
|
|
ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
|
|
|
|
if (!ret && soc_is_dra76x_acd()) {
|
|
ret = omap_hwmod_register_links(acd_76x_hwmod_ocp_ifs);
|
|
} else if (!ret && soc_is_dra76x_abz()) {
|
|
ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|