mirror of https://gitee.com/openkylin/linux.git
629 lines
15 KiB
C
629 lines
15 KiB
C
/*
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*
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* Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450.
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*
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* (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
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*
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* Portions Copyright (c) 2001 Matrox Graphics Inc.
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*
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* Version: 1.65 2002/08/14
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*
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* See matroxfb_base.c for contributors.
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*
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*/
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#include "matroxfb_base.h"
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#include "matroxfb_misc.h"
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#include "matroxfb_DAC1064.h"
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#include "g450_pll.h"
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#include <linux/matroxfb.h>
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#include <asm/uaccess.h>
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#include <asm/div64.h>
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#include "matroxfb_g450.h"
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/* Definition of the various controls */
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struct mctl {
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struct v4l2_queryctrl desc;
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size_t control;
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};
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#define BLMIN 0xF3
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#define WLMAX 0x3FF
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static const struct mctl g450_controls[] =
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{ { { V4L2_CID_BRIGHTNESS, V4L2_CTRL_TYPE_INTEGER,
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"brightness",
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0, WLMAX-BLMIN, 1, 370-BLMIN,
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0,
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}, offsetof(struct matrox_fb_info, altout.tvo_params.brightness) },
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{ { V4L2_CID_CONTRAST, V4L2_CTRL_TYPE_INTEGER,
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"contrast",
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0, 1023, 1, 127,
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0,
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}, offsetof(struct matrox_fb_info, altout.tvo_params.contrast) },
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{ { V4L2_CID_SATURATION, V4L2_CTRL_TYPE_INTEGER,
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"saturation",
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0, 255, 1, 165,
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0,
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}, offsetof(struct matrox_fb_info, altout.tvo_params.saturation) },
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{ { V4L2_CID_HUE, V4L2_CTRL_TYPE_INTEGER,
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"hue",
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0, 255, 1, 0,
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0,
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}, offsetof(struct matrox_fb_info, altout.tvo_params.hue) },
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{ { MATROXFB_CID_TESTOUT, V4L2_CTRL_TYPE_BOOLEAN,
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"test output",
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0, 1, 1, 0,
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0,
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}, offsetof(struct matrox_fb_info, altout.tvo_params.testout) },
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};
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#define G450CTRLS (sizeof(g450_controls)/sizeof(g450_controls[0]))
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/* Return: positive number: id found
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-EINVAL: id not found, return failure
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-ENOENT: id not found, create fake disabled control */
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static int get_ctrl_id(__u32 v4l2_id) {
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int i;
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for (i = 0; i < G450CTRLS; i++) {
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if (v4l2_id < g450_controls[i].desc.id) {
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if (g450_controls[i].desc.id == 0x08000000) {
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return -EINVAL;
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}
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return -ENOENT;
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}
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if (v4l2_id == g450_controls[i].desc.id) {
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return i;
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}
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}
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return -EINVAL;
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}
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static inline int* get_ctrl_ptr(WPMINFO unsigned int idx) {
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return (int*)((char*)MINFO + g450_controls[idx].control);
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}
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static void tvo_fill_defaults(WPMINFO2) {
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unsigned int i;
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for (i = 0; i < G450CTRLS; i++) {
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*get_ctrl_ptr(PMINFO i) = g450_controls[i].desc.default_value;
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}
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}
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static int cve2_get_reg(WPMINFO int reg) {
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unsigned long flags;
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int val;
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matroxfb_DAC_lock_irqsave(flags);
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matroxfb_DAC_out(PMINFO 0x87, reg);
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val = matroxfb_DAC_in(PMINFO 0x88);
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matroxfb_DAC_unlock_irqrestore(flags);
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return val;
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}
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static void cve2_set_reg(WPMINFO int reg, int val) {
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unsigned long flags;
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matroxfb_DAC_lock_irqsave(flags);
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matroxfb_DAC_out(PMINFO 0x87, reg);
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matroxfb_DAC_out(PMINFO 0x88, val);
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matroxfb_DAC_unlock_irqrestore(flags);
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}
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static void cve2_set_reg10(WPMINFO int reg, int val) {
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unsigned long flags;
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matroxfb_DAC_lock_irqsave(flags);
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matroxfb_DAC_out(PMINFO 0x87, reg);
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matroxfb_DAC_out(PMINFO 0x88, val >> 2);
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matroxfb_DAC_out(PMINFO 0x87, reg + 1);
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matroxfb_DAC_out(PMINFO 0x88, val & 3);
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matroxfb_DAC_unlock_irqrestore(flags);
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}
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static void g450_compute_bwlevel(CPMINFO int *bl, int *wl) {
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const int b = ACCESS_FBINFO(altout.tvo_params.brightness) + BLMIN;
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const int c = ACCESS_FBINFO(altout.tvo_params.contrast);
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*bl = max(b - c, BLMIN);
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*wl = min(b + c, WLMAX);
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}
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static int g450_query_ctrl(void* md, struct v4l2_queryctrl *p) {
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int i;
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i = get_ctrl_id(p->id);
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if (i >= 0) {
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*p = g450_controls[i].desc;
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return 0;
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}
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if (i == -ENOENT) {
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static const struct v4l2_queryctrl disctrl =
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{ .flags = V4L2_CTRL_FLAG_DISABLED };
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i = p->id;
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*p = disctrl;
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p->id = i;
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sprintf(p->name, "Ctrl #%08X", i);
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return 0;
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}
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return -EINVAL;
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}
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static int g450_set_ctrl(void* md, struct v4l2_control *p) {
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int i;
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MINFO_FROM(md);
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i = get_ctrl_id(p->id);
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if (i < 0) return -EINVAL;
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/*
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* Check if changed.
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*/
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if (p->value == *get_ctrl_ptr(PMINFO i)) return 0;
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/*
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* Check limits.
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*/
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if (p->value > g450_controls[i].desc.maximum) return -EINVAL;
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if (p->value < g450_controls[i].desc.minimum) return -EINVAL;
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/*
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* Store new value.
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*/
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*get_ctrl_ptr(PMINFO i) = p->value;
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switch (p->id) {
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case V4L2_CID_BRIGHTNESS:
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case V4L2_CID_CONTRAST:
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{
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int blacklevel, whitelevel;
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g450_compute_bwlevel(PMINFO &blacklevel, &whitelevel);
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cve2_set_reg10(PMINFO 0x0e, blacklevel);
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cve2_set_reg10(PMINFO 0x1e, whitelevel);
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}
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break;
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case V4L2_CID_SATURATION:
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cve2_set_reg(PMINFO 0x20, p->value);
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cve2_set_reg(PMINFO 0x22, p->value);
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break;
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case V4L2_CID_HUE:
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cve2_set_reg(PMINFO 0x25, p->value);
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break;
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case MATROXFB_CID_TESTOUT:
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{
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unsigned char val = cve2_get_reg (PMINFO 0x05);
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if (p->value) val |= 0x02;
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else val &= ~0x02;
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cve2_set_reg(PMINFO 0x05, val);
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}
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break;
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}
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return 0;
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}
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static int g450_get_ctrl(void* md, struct v4l2_control *p) {
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int i;
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MINFO_FROM(md);
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i = get_ctrl_id(p->id);
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if (i < 0) return -EINVAL;
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p->value = *get_ctrl_ptr(PMINFO i);
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return 0;
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}
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struct output_desc {
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unsigned int h_vis;
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unsigned int h_f_porch;
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unsigned int h_sync;
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unsigned int h_b_porch;
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unsigned long long int chromasc;
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unsigned int burst;
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unsigned int v_total;
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};
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static void computeRegs(WPMINFO struct mavenregs* r, struct my_timming* mt, const struct output_desc* outd) {
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u_int32_t chromasc;
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u_int32_t hlen;
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u_int32_t hsl;
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u_int32_t hbp;
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u_int32_t hfp;
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u_int32_t hvis;
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unsigned int pixclock;
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unsigned long long piic;
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int mnp;
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int over;
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r->regs[0x80] = 0x03; /* | 0x40 for SCART */
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hvis = ((mt->HDisplay << 1) + 3) & ~3;
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if (hvis >= 2048) {
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hvis = 2044;
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}
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piic = 1000000000ULL * hvis;
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do_div(piic, outd->h_vis);
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dprintk(KERN_DEBUG "Want %u kHz pixclock\n", (unsigned int)piic);
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mnp = matroxfb_g450_setclk(PMINFO piic, M_VIDEO_PLL);
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mt->mnp = mnp;
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mt->pixclock = g450_mnp2f(PMINFO mnp);
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dprintk(KERN_DEBUG "MNP=%08X\n", mnp);
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pixclock = 1000000000U / mt->pixclock;
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dprintk(KERN_DEBUG "Got %u ps pixclock\n", pixclock);
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piic = outd->chromasc;
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do_div(piic, mt->pixclock);
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chromasc = piic;
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dprintk(KERN_DEBUG "Chroma is %08X\n", chromasc);
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r->regs[0] = piic >> 24;
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r->regs[1] = piic >> 16;
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r->regs[2] = piic >> 8;
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r->regs[3] = piic >> 0;
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hbp = (((outd->h_b_porch + pixclock) / pixclock)) & ~1;
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hfp = (((outd->h_f_porch + pixclock) / pixclock)) & ~1;
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hsl = (((outd->h_sync + pixclock) / pixclock)) & ~1;
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hlen = hvis + hfp + hsl + hbp;
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over = hlen & 0x0F;
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dprintk(KERN_DEBUG "WL: vis=%u, hf=%u, hs=%u, hb=%u, total=%u\n", hvis, hfp, hsl, hbp, hlen);
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if (over) {
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hfp -= over;
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hlen -= over;
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if (over <= 2) {
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} else if (over < 10) {
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hfp += 4;
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hlen += 4;
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} else {
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hfp += 16;
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hlen += 16;
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}
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}
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/* maybe cve2 has requirement 800 < hlen < 1184 */
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r->regs[0x08] = hsl;
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r->regs[0x09] = (outd->burst + pixclock - 1) / pixclock; /* burst length */
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r->regs[0x0A] = hbp;
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r->regs[0x2C] = hfp;
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r->regs[0x31] = hvis / 8;
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r->regs[0x32] = hvis & 7;
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dprintk(KERN_DEBUG "PG: vis=%04X, hf=%02X, hs=%02X, hb=%02X, total=%04X\n", hvis, hfp, hsl, hbp, hlen);
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r->regs[0x84] = 1; /* x sync point */
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r->regs[0x85] = 0;
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hvis = hvis >> 1;
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hlen = hlen >> 1;
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dprintk(KERN_DEBUG "hlen=%u hvis=%u\n", hlen, hvis);
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mt->interlaced = 1;
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mt->HDisplay = hvis & ~7;
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mt->HSyncStart = mt->HDisplay + 8;
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mt->HSyncEnd = (hlen & ~7) - 8;
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mt->HTotal = hlen;
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{
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int upper;
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unsigned int vtotal;
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unsigned int vsyncend;
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unsigned int vdisplay;
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vtotal = mt->VTotal;
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vsyncend = mt->VSyncEnd;
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vdisplay = mt->VDisplay;
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if (vtotal < outd->v_total) {
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unsigned int yovr = outd->v_total - vtotal;
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vsyncend += yovr >> 1;
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} else if (vtotal > outd->v_total) {
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vdisplay = outd->v_total - 4;
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vsyncend = outd->v_total;
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}
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upper = (outd->v_total - vsyncend) >> 1; /* in field lines */
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r->regs[0x17] = outd->v_total / 4;
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r->regs[0x18] = outd->v_total & 3;
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r->regs[0x33] = upper - 1; /* upper blanking */
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r->regs[0x82] = upper; /* y sync point */
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r->regs[0x83] = upper >> 8;
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mt->VDisplay = vdisplay;
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mt->VSyncStart = outd->v_total - 2;
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mt->VSyncEnd = outd->v_total;
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mt->VTotal = outd->v_total;
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}
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}
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static void cve2_init_TVdata(int norm, struct mavenregs* data, const struct output_desc** outd) {
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static const struct output_desc paloutd = {
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.h_vis = 52148148, // ps
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.h_f_porch = 1407407, // ps
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.h_sync = 4666667, // ps
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.h_b_porch = 5777778, // ps
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.chromasc = 19042247534182ULL, // 4433618.750 Hz
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.burst = 2518518, // ps
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.v_total = 625,
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};
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static const struct output_desc ntscoutd = {
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.h_vis = 52888889, // ps
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.h_f_porch = 1333333, // ps
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.h_sync = 4666667, // ps
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.h_b_porch = 4666667, // ps
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.chromasc = 15374030659475ULL, // 3579545.454 Hz
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.burst = 2418418, // ps
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.v_total = 525, // lines
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};
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static const struct mavenregs palregs = { {
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0x2A, 0x09, 0x8A, 0xCB, /* 00: chroma subcarrier */
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0x00,
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0x00, /* test */
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0xF9, /* modified by code (F9 written...) */
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0x00, /* ? not written */
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0x7E, /* 08 */
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0x44, /* 09 */
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0x9C, /* 0A */
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0x2E, /* 0B */
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0x21, /* 0C */
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0x00, /* ? not written */
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// 0x3F, 0x03, /* 0E-0F */
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0x3C, 0x03,
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0x3C, 0x03, /* 10-11 */
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0x1A, /* 12 */
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0x2A, /* 13 */
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0x1C, 0x3D, 0x14, /* 14-16 */
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0x9C, 0x01, /* 17-18 */
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0x00, /* 19 */
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0xFE, /* 1A */
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0x7E, /* 1B */
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0x60, /* 1C */
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0x05, /* 1D */
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// 0x89, 0x03, /* 1E-1F */
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0xAD, 0x03,
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// 0x72, /* 20 */
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0xA5,
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0x07, /* 21 */
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// 0x72, /* 22 */
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0xA5,
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0x00, /* 23 */
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0x00, /* 24 */
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0x00, /* 25 */
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0x08, /* 26 */
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0x04, /* 27 */
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0x00, /* 28 */
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0x1A, /* 29 */
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0x55, 0x01, /* 2A-2B */
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0x26, /* 2C */
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0x07, 0x7E, /* 2D-2E */
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0x02, 0x54, /* 2F-30 */
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0xB0, 0x00, /* 31-32 */
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0x14, /* 33 */
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0x49, /* 34 */
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0x00, /* 35 written multiple times */
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0x00, /* 36 not written */
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0xA3, /* 37 */
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0xC8, /* 38 */
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0x22, /* 39 */
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0x02, /* 3A */
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0x22, /* 3B */
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0x3F, 0x03, /* 3C-3D */
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0x00, /* 3E written multiple times */
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0x00, /* 3F not written */
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} };
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static struct mavenregs ntscregs = { {
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0x21, 0xF0, 0x7C, 0x1F, /* 00: chroma subcarrier */
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0x00,
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0x00, /* test */
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0xF9, /* modified by code (F9 written...) */
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0x00, /* ? not written */
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0x7E, /* 08 */
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0x43, /* 09 */
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0x7E, /* 0A */
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0x3D, /* 0B */
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0x00, /* 0C */
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0x00, /* ? not written */
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0x41, 0x00, /* 0E-0F */
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0x3C, 0x00, /* 10-11 */
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0x17, /* 12 */
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0x21, /* 13 */
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0x1B, 0x1B, 0x24, /* 14-16 */
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0x83, 0x01, /* 17-18 */
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0x00, /* 19 */
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0x0F, /* 1A */
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0x0F, /* 1B */
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0x60, /* 1C */
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0x05, /* 1D */
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//0x89, 0x02, /* 1E-1F */
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0xC0, 0x02, /* 1E-1F */
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//0x5F, /* 20 */
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0x9C, /* 20 */
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0x04, /* 21 */
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//0x5F, /* 22 */
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0x9C, /* 22 */
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0x01, /* 23 */
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0x02, /* 24 */
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0x00, /* 25 */
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0x0A, /* 26 */
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0x05, /* 27 */
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0x00, /* 28 */
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0x10, /* 29 */
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0xFF, 0x03, /* 2A-2B */
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0x24, /* 2C */
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0x0F, 0x78, /* 2D-2E */
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0x00, 0x00, /* 2F-30 */
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0xB2, 0x04, /* 31-32 */
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0x14, /* 33 */
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0x02, /* 34 */
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0x00, /* 35 written multiple times */
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0x00, /* 36 not written */
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0xA3, /* 37 */
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0xC8, /* 38 */
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0x15, /* 39 */
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0x05, /* 3A */
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0x3B, /* 3B */
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0x3C, 0x00, /* 3C-3D */
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0x00, /* 3E written multiple times */
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0x00, /* never written */
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} };
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if (norm == MATROXFB_OUTPUT_MODE_PAL) {
|
|
*data = palregs;
|
|
*outd = &paloutd;
|
|
} else {
|
|
*data = ntscregs;
|
|
*outd = &ntscoutd;
|
|
}
|
|
return;
|
|
}
|
|
|
|
#define LR(x) cve2_set_reg(PMINFO (x), m->regs[(x)])
|
|
static void cve2_init_TV(WPMINFO const struct mavenregs* m) {
|
|
int i;
|
|
|
|
LR(0x80);
|
|
LR(0x82); LR(0x83);
|
|
LR(0x84); LR(0x85);
|
|
|
|
cve2_set_reg(PMINFO 0x3E, 0x01);
|
|
|
|
for (i = 0; i < 0x3E; i++) {
|
|
LR(i);
|
|
}
|
|
cve2_set_reg(PMINFO 0x3E, 0x00);
|
|
}
|
|
|
|
static int matroxfb_g450_compute(void* md, struct my_timming* mt) {
|
|
MINFO_FROM(md);
|
|
|
|
dprintk(KERN_DEBUG "Computing, mode=%u\n", ACCESS_FBINFO(outputs[1]).mode);
|
|
|
|
if (mt->crtc == MATROXFB_SRC_CRTC2 &&
|
|
ACCESS_FBINFO(outputs[1]).mode != MATROXFB_OUTPUT_MODE_MONITOR) {
|
|
const struct output_desc* outd;
|
|
|
|
cve2_init_TVdata(ACCESS_FBINFO(outputs[1]).mode, &ACCESS_FBINFO(hw).maven, &outd);
|
|
{
|
|
int blacklevel, whitelevel;
|
|
g450_compute_bwlevel(PMINFO &blacklevel, &whitelevel);
|
|
ACCESS_FBINFO(hw).maven.regs[0x0E] = blacklevel >> 2;
|
|
ACCESS_FBINFO(hw).maven.regs[0x0F] = blacklevel & 3;
|
|
ACCESS_FBINFO(hw).maven.regs[0x1E] = whitelevel >> 2;
|
|
ACCESS_FBINFO(hw).maven.regs[0x1F] = whitelevel & 3;
|
|
|
|
ACCESS_FBINFO(hw).maven.regs[0x20] =
|
|
ACCESS_FBINFO(hw).maven.regs[0x22] = ACCESS_FBINFO(altout.tvo_params.saturation);
|
|
|
|
ACCESS_FBINFO(hw).maven.regs[0x25] = ACCESS_FBINFO(altout.tvo_params.hue);
|
|
|
|
if (ACCESS_FBINFO(altout.tvo_params.testout)) {
|
|
ACCESS_FBINFO(hw).maven.regs[0x05] |= 0x02;
|
|
}
|
|
}
|
|
computeRegs(PMINFO &ACCESS_FBINFO(hw).maven, mt, outd);
|
|
} else if (mt->mnp < 0) {
|
|
/* We must program clocks before CRTC2, otherwise interlaced mode
|
|
startup may fail */
|
|
mt->mnp = matroxfb_g450_setclk(PMINFO mt->pixclock, (mt->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
|
|
mt->pixclock = g450_mnp2f(PMINFO mt->mnp);
|
|
}
|
|
dprintk(KERN_DEBUG "Pixclock = %u\n", mt->pixclock);
|
|
return 0;
|
|
}
|
|
|
|
static int matroxfb_g450_program(void* md) {
|
|
MINFO_FROM(md);
|
|
|
|
if (ACCESS_FBINFO(outputs[1]).mode != MATROXFB_OUTPUT_MODE_MONITOR) {
|
|
cve2_init_TV(PMINFO &ACCESS_FBINFO(hw).maven);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int matroxfb_g450_verify_mode(void* md, u_int32_t arg) {
|
|
switch (arg) {
|
|
case MATROXFB_OUTPUT_MODE_PAL:
|
|
case MATROXFB_OUTPUT_MODE_NTSC:
|
|
case MATROXFB_OUTPUT_MODE_MONITOR:
|
|
return 0;
|
|
}
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int g450_dvi_compute(void* md, struct my_timming* mt) {
|
|
MINFO_FROM(md);
|
|
|
|
if (mt->mnp < 0) {
|
|
mt->mnp = matroxfb_g450_setclk(PMINFO mt->pixclock, (mt->crtc == MATROXFB_SRC_CRTC1) ? M_PIXEL_PLL_C : M_VIDEO_PLL);
|
|
mt->pixclock = g450_mnp2f(PMINFO mt->mnp);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static struct matrox_altout matroxfb_g450_altout = {
|
|
.name = "Secondary output",
|
|
.compute = matroxfb_g450_compute,
|
|
.program = matroxfb_g450_program,
|
|
.verifymode = matroxfb_g450_verify_mode,
|
|
.getqueryctrl = g450_query_ctrl,
|
|
.getctrl = g450_get_ctrl,
|
|
.setctrl = g450_set_ctrl,
|
|
};
|
|
|
|
static struct matrox_altout matroxfb_g450_dvi = {
|
|
.name = "DVI output",
|
|
.compute = g450_dvi_compute,
|
|
};
|
|
|
|
void matroxfb_g450_connect(WPMINFO2) {
|
|
if (ACCESS_FBINFO(devflags.g450dac)) {
|
|
down_write(&ACCESS_FBINFO(altout.lock));
|
|
tvo_fill_defaults(PMINFO2);
|
|
ACCESS_FBINFO(outputs[1]).src = ACCESS_FBINFO(outputs[1]).default_src;
|
|
ACCESS_FBINFO(outputs[1]).data = MINFO;
|
|
ACCESS_FBINFO(outputs[1]).output = &matroxfb_g450_altout;
|
|
ACCESS_FBINFO(outputs[1]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
|
|
ACCESS_FBINFO(outputs[2]).src = ACCESS_FBINFO(outputs[2]).default_src;
|
|
ACCESS_FBINFO(outputs[2]).data = MINFO;
|
|
ACCESS_FBINFO(outputs[2]).output = &matroxfb_g450_dvi;
|
|
ACCESS_FBINFO(outputs[2]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
|
|
up_write(&ACCESS_FBINFO(altout.lock));
|
|
}
|
|
}
|
|
|
|
void matroxfb_g450_shutdown(WPMINFO2) {
|
|
if (ACCESS_FBINFO(devflags.g450dac)) {
|
|
down_write(&ACCESS_FBINFO(altout.lock));
|
|
ACCESS_FBINFO(outputs[1]).src = MATROXFB_SRC_NONE;
|
|
ACCESS_FBINFO(outputs[1]).output = NULL;
|
|
ACCESS_FBINFO(outputs[1]).data = NULL;
|
|
ACCESS_FBINFO(outputs[1]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
|
|
ACCESS_FBINFO(outputs[2]).src = MATROXFB_SRC_NONE;
|
|
ACCESS_FBINFO(outputs[2]).output = NULL;
|
|
ACCESS_FBINFO(outputs[2]).data = NULL;
|
|
ACCESS_FBINFO(outputs[2]).mode = MATROXFB_OUTPUT_MODE_MONITOR;
|
|
up_write(&ACCESS_FBINFO(altout.lock));
|
|
}
|
|
}
|
|
|
|
EXPORT_SYMBOL(matroxfb_g450_connect);
|
|
EXPORT_SYMBOL(matroxfb_g450_shutdown);
|
|
|
|
MODULE_AUTHOR("(c) 2000-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");
|
|
MODULE_DESCRIPTION("Matrox G450/G550 output driver");
|
|
MODULE_LICENSE("GPL");
|