mirror of https://gitee.com/openkylin/linux.git
466 lines
12 KiB
C
466 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* This file contains quirk handling code for PnP devices
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* Some devices do not report all their resources, and need to have extra
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* resources added. This is most easily accomplished at initialisation time
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* when building up the resource structure for the first time.
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*
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* Copyright (c) 2000 Peter Denison <peterd@pnd-pc.demon.co.uk>
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* Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
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* Bjorn Helgaas <bjorn.helgaas@hp.com>
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*
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* Heavily based on PCI quirks handling which is
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*
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* Copyright (c) 1999 Martin Mares <mj@ucw.cz>
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/pnp.h>
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#include <linux/io.h>
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#include "base.h"
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static void quirk_awe32_add_ports(struct pnp_dev *dev,
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struct pnp_option *option,
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unsigned int offset)
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{
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struct pnp_option *new_option;
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new_option = kmalloc(sizeof(struct pnp_option), GFP_KERNEL);
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if (!new_option) {
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dev_err(&dev->dev, "couldn't add ioport region to option set "
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"%d\n", pnp_option_set(option));
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return;
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}
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*new_option = *option;
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new_option->u.port.min += offset;
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new_option->u.port.max += offset;
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list_add(&new_option->list, &option->list);
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dev_info(&dev->dev, "added ioport region %#llx-%#llx to set %d\n",
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(unsigned long long) new_option->u.port.min,
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(unsigned long long) new_option->u.port.max,
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pnp_option_set(option));
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}
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static void quirk_awe32_resources(struct pnp_dev *dev)
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{
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struct pnp_option *option;
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unsigned int set = ~0;
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/*
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* Add two extra ioport regions (at offset 0x400 and 0x800 from the
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* one given) to every dependent option set.
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*/
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list_for_each_entry(option, &dev->options, list) {
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if (pnp_option_is_dependent(option) &&
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pnp_option_set(option) != set) {
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set = pnp_option_set(option);
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quirk_awe32_add_ports(dev, option, 0x800);
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quirk_awe32_add_ports(dev, option, 0x400);
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}
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}
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}
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static void quirk_cmi8330_resources(struct pnp_dev *dev)
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{
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struct pnp_option *option;
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struct pnp_irq *irq;
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struct pnp_dma *dma;
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list_for_each_entry(option, &dev->options, list) {
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if (!pnp_option_is_dependent(option))
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continue;
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if (option->type == IORESOURCE_IRQ) {
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irq = &option->u.irq;
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bitmap_zero(irq->map.bits, PNP_IRQ_NR);
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__set_bit(5, irq->map.bits);
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__set_bit(7, irq->map.bits);
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__set_bit(10, irq->map.bits);
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dev_info(&dev->dev, "set possible IRQs in "
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"option set %d to 5, 7, 10\n",
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pnp_option_set(option));
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} else if (option->type == IORESOURCE_DMA) {
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dma = &option->u.dma;
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if ((dma->flags & IORESOURCE_DMA_TYPE_MASK) ==
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IORESOURCE_DMA_8BIT &&
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dma->map != 0x0A) {
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dev_info(&dev->dev, "changing possible "
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"DMA channel mask in option set %d "
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"from %#02x to 0x0A (1, 3)\n",
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pnp_option_set(option), dma->map);
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dma->map = 0x0A;
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}
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}
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}
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}
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static void quirk_sb16audio_resources(struct pnp_dev *dev)
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{
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struct pnp_option *option;
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unsigned int prev_option_flags = ~0, n = 0;
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struct pnp_port *port;
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/*
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* The default range on the OPL port for these devices is 0x388-0x388.
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* Here we increase that range so that two such cards can be
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* auto-configured.
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*/
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list_for_each_entry(option, &dev->options, list) {
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if (prev_option_flags != option->flags) {
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prev_option_flags = option->flags;
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n = 0;
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}
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if (pnp_option_is_dependent(option) &&
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option->type == IORESOURCE_IO) {
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n++;
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port = &option->u.port;
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if (n == 3 && port->min == port->max) {
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port->max += 0x70;
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dev_info(&dev->dev, "increased option port "
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"range from %#llx-%#llx to "
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"%#llx-%#llx\n",
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(unsigned long long) port->min,
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(unsigned long long) port->min,
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(unsigned long long) port->min,
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(unsigned long long) port->max);
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}
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}
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}
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}
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static struct pnp_option *pnp_clone_dependent_set(struct pnp_dev *dev,
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unsigned int set)
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{
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struct pnp_option *tail = NULL, *first_new_option = NULL;
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struct pnp_option *option, *new_option;
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unsigned int flags;
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list_for_each_entry(option, &dev->options, list) {
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if (pnp_option_is_dependent(option))
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tail = option;
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}
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if (!tail) {
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dev_err(&dev->dev, "no dependent option sets\n");
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return NULL;
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}
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flags = pnp_new_dependent_set(dev, PNP_RES_PRIORITY_FUNCTIONAL);
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list_for_each_entry(option, &dev->options, list) {
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if (pnp_option_is_dependent(option) &&
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pnp_option_set(option) == set) {
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new_option = kmalloc(sizeof(struct pnp_option),
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GFP_KERNEL);
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if (!new_option) {
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dev_err(&dev->dev, "couldn't clone dependent "
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"set %d\n", set);
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return NULL;
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}
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*new_option = *option;
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new_option->flags = flags;
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if (!first_new_option)
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first_new_option = new_option;
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list_add(&new_option->list, &tail->list);
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tail = new_option;
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}
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}
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return first_new_option;
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}
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static void quirk_add_irq_optional_dependent_sets(struct pnp_dev *dev)
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{
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struct pnp_option *new_option;
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unsigned int num_sets, i, set;
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struct pnp_irq *irq;
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num_sets = dev->num_dependent_sets;
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for (i = 0; i < num_sets; i++) {
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new_option = pnp_clone_dependent_set(dev, i);
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if (!new_option)
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return;
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set = pnp_option_set(new_option);
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while (new_option && pnp_option_set(new_option) == set) {
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if (new_option->type == IORESOURCE_IRQ) {
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irq = &new_option->u.irq;
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irq->flags |= IORESOURCE_IRQ_OPTIONAL;
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}
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dbg_pnp_show_option(dev, new_option);
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new_option = list_entry(new_option->list.next,
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struct pnp_option, list);
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}
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dev_info(&dev->dev, "added dependent option set %d (same as "
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"set %d except IRQ optional)\n", set, i);
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}
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}
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static void quirk_ad1815_mpu_resources(struct pnp_dev *dev)
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{
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struct pnp_option *option;
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struct pnp_irq *irq = NULL;
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unsigned int independent_irqs = 0;
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list_for_each_entry(option, &dev->options, list) {
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if (option->type == IORESOURCE_IRQ &&
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!pnp_option_is_dependent(option)) {
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independent_irqs++;
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irq = &option->u.irq;
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}
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}
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if (independent_irqs != 1)
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return;
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irq->flags |= IORESOURCE_IRQ_OPTIONAL;
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dev_info(&dev->dev, "made independent IRQ optional\n");
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}
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#include <linux/pci.h>
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static void quirk_system_pci_resources(struct pnp_dev *dev)
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{
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struct pci_dev *pdev = NULL;
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struct resource *res;
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resource_size_t pnp_start, pnp_end, pci_start, pci_end;
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int i, j;
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/*
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* Some BIOSes have PNP motherboard devices with resources that
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* partially overlap PCI BARs. The PNP system driver claims these
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* motherboard resources, which prevents the normal PCI driver from
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* requesting them later.
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*
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* This patch disables the PNP resources that conflict with PCI BARs
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* so they won't be claimed by the PNP system driver.
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*/
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for_each_pci_dev(pdev) {
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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unsigned long flags, type;
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flags = pci_resource_flags(pdev, i);
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type = flags & (IORESOURCE_IO | IORESOURCE_MEM);
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if (!type || pci_resource_len(pdev, i) == 0)
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continue;
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if (flags & IORESOURCE_UNSET)
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continue;
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pci_start = pci_resource_start(pdev, i);
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pci_end = pci_resource_end(pdev, i);
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for (j = 0;
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(res = pnp_get_resource(dev, type, j)); j++) {
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if (res->start == 0 && res->end == 0)
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continue;
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pnp_start = res->start;
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pnp_end = res->end;
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/*
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* If the PNP region doesn't overlap the PCI
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* region at all, there's no problem.
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*/
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if (pnp_end < pci_start || pnp_start > pci_end)
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continue;
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/*
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* If the PNP region completely encloses (or is
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* at least as large as) the PCI region, that's
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* also OK. For example, this happens when the
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* PNP device describes a bridge with PCI
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* behind it.
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*/
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if (pnp_start <= pci_start &&
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pnp_end >= pci_end)
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continue;
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/*
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* Otherwise, the PNP region overlaps *part* of
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* the PCI region, and that might prevent a PCI
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* driver from requesting its resources.
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*/
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dev_warn(&dev->dev,
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"disabling %pR because it overlaps "
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"%s BAR %d %pR\n", res,
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pci_name(pdev), i, &pdev->resource[i]);
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res->flags |= IORESOURCE_DISABLED;
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}
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}
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}
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}
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#ifdef CONFIG_AMD_NB
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#include <asm/amd_nb.h>
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static void quirk_amd_mmconfig_area(struct pnp_dev *dev)
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{
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resource_size_t start, end;
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struct pnp_resource *pnp_res;
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struct resource *res;
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struct resource mmconfig_res, *mmconfig;
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mmconfig = amd_get_mmconfig_range(&mmconfig_res);
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if (!mmconfig)
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return;
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list_for_each_entry(pnp_res, &dev->resources, list) {
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res = &pnp_res->res;
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if (res->end < mmconfig->start || res->start > mmconfig->end ||
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(res->start == mmconfig->start && res->end == mmconfig->end))
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continue;
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dev_info(&dev->dev, FW_BUG
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"%pR covers only part of AMD MMCONFIG area %pR; adding more reservations\n",
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res, mmconfig);
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if (mmconfig->start < res->start) {
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start = mmconfig->start;
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end = res->start - 1;
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pnp_add_mem_resource(dev, start, end, 0);
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}
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if (mmconfig->end > res->end) {
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start = res->end + 1;
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end = mmconfig->end;
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pnp_add_mem_resource(dev, start, end, 0);
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}
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break;
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}
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}
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#endif
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#ifdef CONFIG_PCI
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/* Device IDs of parts that have 32KB MCH space */
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static const unsigned int mch_quirk_devices[] = {
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0x0154, /* Ivy Bridge */
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0x0a04, /* Haswell-ULT */
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0x0c00, /* Haswell */
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0x1604, /* Broadwell */
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};
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static struct pci_dev *get_intel_host(void)
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{
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int i;
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struct pci_dev *host;
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for (i = 0; i < ARRAY_SIZE(mch_quirk_devices); i++) {
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host = pci_get_device(PCI_VENDOR_ID_INTEL, mch_quirk_devices[i],
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NULL);
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if (host)
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return host;
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}
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return NULL;
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}
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static void quirk_intel_mch(struct pnp_dev *dev)
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{
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struct pci_dev *host;
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u32 addr_lo, addr_hi;
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struct pci_bus_region region;
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struct resource mch;
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struct pnp_resource *pnp_res;
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struct resource *res;
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host = get_intel_host();
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if (!host)
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return;
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/*
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* MCHBAR is not an architected PCI BAR, so MCH space is usually
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* reported as a PNP0C02 resource. The MCH space was originally
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* 16KB, but is 32KB in newer parts. Some BIOSes still report a
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* PNP0C02 resource that is only 16KB, which means the rest of the
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* MCH space is consumed but unreported.
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*/
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/*
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* Read MCHBAR for Host Member Mapped Register Range Base
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* https://www-ssl.intel.com/content/www/us/en/processors/core/4th-gen-core-family-desktop-vol-2-datasheet
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* Sec 3.1.12.
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*/
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pci_read_config_dword(host, 0x48, &addr_lo);
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region.start = addr_lo & ~0x7fff;
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pci_read_config_dword(host, 0x4c, &addr_hi);
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region.start |= (u64) addr_hi << 32;
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region.end = region.start + 32*1024 - 1;
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memset(&mch, 0, sizeof(mch));
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mch.flags = IORESOURCE_MEM;
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pcibios_bus_to_resource(host->bus, &mch, ®ion);
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list_for_each_entry(pnp_res, &dev->resources, list) {
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res = &pnp_res->res;
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if (res->end < mch.start || res->start > mch.end)
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continue; /* no overlap */
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if (res->start == mch.start && res->end == mch.end)
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continue; /* exact match */
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dev_info(&dev->dev, FW_BUG "PNP resource %pR covers only part of %s Intel MCH; extending to %pR\n",
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res, pci_name(host), &mch);
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res->start = mch.start;
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res->end = mch.end;
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break;
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}
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pci_dev_put(host);
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}
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#endif
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/*
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* PnP Quirks
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* Cards or devices that need some tweaking due to incomplete resource info
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*/
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static struct pnp_fixup pnp_fixups[] = {
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/* Soundblaster awe io port quirk */
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{"CTL0021", quirk_awe32_resources},
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{"CTL0022", quirk_awe32_resources},
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{"CTL0023", quirk_awe32_resources},
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/* CMI 8330 interrupt and dma fix */
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{"@X@0001", quirk_cmi8330_resources},
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/* Soundblaster audio device io port range quirk */
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{"CTL0001", quirk_sb16audio_resources},
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{"CTL0031", quirk_sb16audio_resources},
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{"CTL0041", quirk_sb16audio_resources},
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{"CTL0042", quirk_sb16audio_resources},
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{"CTL0043", quirk_sb16audio_resources},
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{"CTL0044", quirk_sb16audio_resources},
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{"CTL0045", quirk_sb16audio_resources},
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/* Add IRQ-optional MPU options */
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{"ADS7151", quirk_ad1815_mpu_resources},
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{"ADS7181", quirk_add_irq_optional_dependent_sets},
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{"AZT0002", quirk_add_irq_optional_dependent_sets},
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/* PnP resources that might overlap PCI BARs */
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{"PNP0c01", quirk_system_pci_resources},
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{"PNP0c02", quirk_system_pci_resources},
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#ifdef CONFIG_AMD_NB
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{"PNP0c01", quirk_amd_mmconfig_area},
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#endif
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#ifdef CONFIG_PCI
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{"PNP0c02", quirk_intel_mch},
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#endif
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{""}
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};
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void pnp_fixup_device(struct pnp_dev *dev)
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{
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struct pnp_fixup *f;
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for (f = pnp_fixups; *f->id; f++) {
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if (!compare_pnp_id(dev->id, f->id))
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continue;
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pnp_dbg(&dev->dev, "%s: calling %pS\n", f->id,
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f->quirk_function);
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f->quirk_function(dev);
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}
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}
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