mirror of https://gitee.com/openkylin/linux.git
58d4fafd0b
Add the following new features:
- Generic CPU topology description support for DT-based platforms,
including ARM64, ARM and RISC-V.
- Sparsemem support
- Perf callchain support
- SiFive PLIC irqchip modifications, in preparation for M-mode Linux
and clean up the code base:
- Clean up chip-specific register (CSR) manipulation code, IPIs, TLB
flushing, and the RISC-V CPU-local timer code
- Kbuild cleanup from one of the Kbuild maintainers
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEElRDoIDdEz9/svf2Kx4+xDQu9KksFAl1/pGEACgkQx4+xDQu9
Kkvkyw/9GulLK2yeXG8SoXiXWZAhrgUn487GM87BJXFwXkjDCRvYVk4RD8BKfOGt
w1td6BXK5PjceH+d2m3kHa1aBQwT7sgsfQD0mBiHQ7TG+CMHMPV31eqjgIgnklEY
f6bRl4JGokanPnLWE8tnQrMpu91kDI0XS2pnnQNNrAK3DbWocsdUIei14+auwygp
Djbwssb8R/5RQdFO1dRa+0dWo1omzCJBgkMQBXipvD/z7u8BApioYdEUN1pEg6Yg
YLdVtBUIF5gXIsq9jdqEZHWzvTPnq+5HZPy8pAYe/fPcnga89fCfgpWA9DfqjIEA
bNFHJJKWc/lFAcMmXWWkYwgIbx8PUiktdv27S/DYLdyZ4SIX5YEtmdD6aK4ZStQT
ZQcvCMDq9C3Y4s1PIwl9ORI8aVs3k1cI4Ee0xWS/x6D9h/84Ky1uBFgrPXai2G6q
AUxnu0zWhllNahxp+rvUh0rnfHOMalaTG8eUb1GEoLzFcRhKYrKWLgFG/eBCAiit
dofD24KpYSpZNrhZWgVUuE0Jcc58JSHp/LzDUloR2AcAvdxyQZ2Vd+vwE5BGGTzR
t/V4zjSvndXUxFBVe28zHO2qrDzA+jUE8d+vO8w+lDGjbITYYZwIJPBL3f8Z0s6b
wQWBwWlM4ZATqR662sBpz8P/t+RCcTMfLlatIV/07GRerjvPrd8=
=N9WW
-----END PGP SIGNATURE-----
Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Paul Walmsley:
"Add the following new features:
- Generic CPU topology description support for DT-based platforms,
including ARM64, ARM and RISC-V.
- Sparsemem support
- Perf callchain support
- SiFive PLIC irqchip modifications, in preparation for M-mode Linux
and clean up the code base:
- Clean up chip-specific register (CSR) manipulation code, IPIs, TLB
flushing, and the RISC-V CPU-local timer code
- Kbuild cleanup from one of the Kbuild maintainers"
[ The CPU topology parts came in through the arm64 tree with a shared
branch - Linus ]
* tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
irqchip/sifive-plic: set max threshold for ignored handlers
riscv: move the TLB flush logic out of line
riscv: don't use the rdtime(h) pseudo-instructions
riscv: cleanup riscv_cpuid_to_hartid_mask
riscv: optimize send_ipi_single
riscv: cleanup send_ipi_mask
riscv: refactor the IPI code
riscv: Add support for libdw
riscv: Add support for perf registers sampling
riscv: Add perf callchain support
riscv: add arch/riscv/Kbuild
RISC-V: Implement sparsemem
riscv: Using CSR numbers to access CSRs
|
||
|---|---|---|
| .. | ||
| accounting | ||
| arch | ||
| bpf | ||
| build | ||
| cgroup | ||
| crypto | ||
| debugging | ||
| firewire | ||
| firmware | ||
| gpio | ||
| hv | ||
| iio | ||
| include | ||
| io_uring | ||
| kvm/kvm_stat | ||
| laptop | ||
| leds | ||
| lib | ||
| memory-model | ||
| nfsd | ||
| objtool | ||
| pci | ||
| pcmcia | ||
| perf | ||
| power | ||
| scripts | ||
| spi | ||
| testing | ||
| thermal/tmon | ||
| time | ||
| usb | ||
| virtio | ||
| vm | ||
| wmi | ||
| Makefile | ||