mirror of https://gitee.com/openkylin/linux.git
248 lines
5.9 KiB
C
248 lines
5.9 KiB
C
/*
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* drivers/cpufreq/spear-cpufreq.c
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*
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* CPU Frequency Scaling for SPEAr platform
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*
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* Copyright (C) 2012 ST Microelectronics
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* Deepak Sikri <deepak.sikri@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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/* SPEAr CPUFreq driver data structure */
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static struct {
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struct clk *clk;
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unsigned int transition_latency;
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struct cpufreq_frequency_table *freq_tbl;
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u32 cnt;
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} spear_cpufreq;
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static struct clk *spear1340_cpu_get_possible_parent(unsigned long newfreq)
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{
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struct clk *sys_pclk;
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int pclk;
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/*
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* In SPEAr1340, cpu clk's parent sys clk can take input from
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* following sources
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*/
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const char *sys_clk_src[] = {
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"sys_syn_clk",
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"pll1_clk",
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"pll2_clk",
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"pll3_clk",
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};
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/*
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* As sys clk can have multiple source with their own range
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* limitation so we choose possible sources accordingly
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*/
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if (newfreq <= 300000000)
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pclk = 0; /* src is sys_syn_clk */
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else if (newfreq > 300000000 && newfreq <= 500000000)
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pclk = 3; /* src is pll3_clk */
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else if (newfreq == 600000000)
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pclk = 1; /* src is pll1_clk */
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else
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return ERR_PTR(-EINVAL);
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/* Get parent to sys clock */
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sys_pclk = clk_get(NULL, sys_clk_src[pclk]);
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if (IS_ERR(sys_pclk))
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pr_err("Failed to get %s clock\n", sys_clk_src[pclk]);
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return sys_pclk;
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}
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/*
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* In SPEAr1340, we cannot use newfreq directly because we need to actually
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* access a source clock (clk) which might not be ancestor of cpu at present.
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* Hence in SPEAr1340 we would operate on source clock directly before switching
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* cpu clock to it.
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*/
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static int spear1340_set_cpu_rate(struct clk *sys_pclk, unsigned long newfreq)
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{
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struct clk *sys_clk;
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int ret = 0;
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sys_clk = clk_get_parent(spear_cpufreq.clk);
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if (IS_ERR(sys_clk)) {
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pr_err("failed to get cpu's parent (sys) clock\n");
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return PTR_ERR(sys_clk);
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}
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/* Set the rate of the source clock before changing the parent */
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ret = clk_set_rate(sys_pclk, newfreq);
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if (ret) {
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pr_err("Failed to set sys clk rate to %lu\n", newfreq);
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return ret;
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}
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ret = clk_set_parent(sys_clk, sys_pclk);
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if (ret) {
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pr_err("Failed to set sys clk parent\n");
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return ret;
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}
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return 0;
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}
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static int spear_cpufreq_target(struct cpufreq_policy *policy,
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unsigned int index)
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{
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long newfreq;
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struct clk *srcclk;
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int ret, mult = 1;
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newfreq = spear_cpufreq.freq_tbl[index].frequency * 1000;
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if (of_machine_is_compatible("st,spear1340")) {
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/*
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* SPEAr1340 is special in the sense that due to the possibility
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* of multiple clock sources for cpu clk's parent we can have
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* different clock source for different frequency of cpu clk.
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* Hence we need to choose one from amongst these possible clock
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* sources.
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*/
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srcclk = spear1340_cpu_get_possible_parent(newfreq);
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if (IS_ERR(srcclk)) {
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pr_err("Failed to get src clk\n");
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return PTR_ERR(srcclk);
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}
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/* SPEAr1340: src clk is always 2 * intended cpu clk */
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mult = 2;
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} else {
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/*
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* src clock to be altered is ancestor of cpu clock. Hence we
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* can directly work on cpu clk
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*/
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srcclk = spear_cpufreq.clk;
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}
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newfreq = clk_round_rate(srcclk, newfreq * mult);
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if (newfreq <= 0) {
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pr_err("clk_round_rate failed for cpu src clock\n");
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return newfreq;
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}
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if (mult == 2)
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ret = spear1340_set_cpu_rate(srcclk, newfreq);
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else
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ret = clk_set_rate(spear_cpufreq.clk, newfreq);
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if (ret)
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pr_err("CPU Freq: cpu clk_set_rate failed: %d\n", ret);
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return ret;
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}
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static int spear_cpufreq_init(struct cpufreq_policy *policy)
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{
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policy->clk = spear_cpufreq.clk;
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cpufreq_generic_init(policy, spear_cpufreq.freq_tbl,
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spear_cpufreq.transition_latency);
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return 0;
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}
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static struct cpufreq_driver spear_cpufreq_driver = {
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.name = "cpufreq-spear",
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.flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = spear_cpufreq_target,
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.get = cpufreq_generic_get,
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.init = spear_cpufreq_init,
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.attr = cpufreq_generic_attr,
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};
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static int spear_cpufreq_probe(struct platform_device *pdev)
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{
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struct device_node *np;
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const struct property *prop;
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struct cpufreq_frequency_table *freq_tbl;
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const __be32 *val;
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int cnt, i, ret;
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np = of_cpu_device_node_get(0);
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if (!np) {
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pr_err("No cpu node found\n");
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return -ENODEV;
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}
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if (of_property_read_u32(np, "clock-latency",
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&spear_cpufreq.transition_latency))
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spear_cpufreq.transition_latency = CPUFREQ_ETERNAL;
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prop = of_find_property(np, "cpufreq_tbl", NULL);
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if (!prop || !prop->value) {
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pr_err("Invalid cpufreq_tbl\n");
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ret = -ENODEV;
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goto out_put_node;
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}
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cnt = prop->length / sizeof(u32);
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val = prop->value;
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freq_tbl = kcalloc(cnt + 1, sizeof(*freq_tbl), GFP_KERNEL);
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if (!freq_tbl) {
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ret = -ENOMEM;
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goto out_put_node;
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}
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for (i = 0; i < cnt; i++)
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freq_tbl[i].frequency = be32_to_cpup(val++);
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freq_tbl[i].frequency = CPUFREQ_TABLE_END;
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spear_cpufreq.freq_tbl = freq_tbl;
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of_node_put(np);
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spear_cpufreq.clk = clk_get(NULL, "cpu_clk");
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if (IS_ERR(spear_cpufreq.clk)) {
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pr_err("Unable to get CPU clock\n");
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ret = PTR_ERR(spear_cpufreq.clk);
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goto out_put_mem;
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}
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ret = cpufreq_register_driver(&spear_cpufreq_driver);
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if (!ret)
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return 0;
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pr_err("failed register driver: %d\n", ret);
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clk_put(spear_cpufreq.clk);
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out_put_mem:
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kfree(freq_tbl);
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return ret;
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out_put_node:
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of_node_put(np);
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return ret;
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}
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static struct platform_driver spear_cpufreq_platdrv = {
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.driver = {
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.name = "spear-cpufreq",
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},
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.probe = spear_cpufreq_probe,
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};
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module_platform_driver(spear_cpufreq_platdrv);
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MODULE_AUTHOR("Deepak Sikri <deepak.sikri@st.com>");
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MODULE_DESCRIPTION("SPEAr CPUFreq driver");
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MODULE_LICENSE("GPL");
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