mirror of https://gitee.com/openkylin/linux.git
473 lines
13 KiB
C
473 lines
13 KiB
C
/*
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* Copyright (C) 2014 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/printk.h>
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#include <linux/slab.h>
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#include "clk.h"
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#define PLL_STATUS 0x0
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#define PLL_STATUS_LOCK BIT(0)
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#define PLL_CTRL1 0x4
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#define PLL_CTRL1_REFDIV_SHIFT 0
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#define PLL_CTRL1_REFDIV_MASK 0x3f
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#define PLL_CTRL1_FBDIV_SHIFT 6
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#define PLL_CTRL1_FBDIV_MASK 0xfff
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#define PLL_INT_CTRL1_POSTDIV1_SHIFT 18
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#define PLL_INT_CTRL1_POSTDIV1_MASK 0x7
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#define PLL_INT_CTRL1_POSTDIV2_SHIFT 21
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#define PLL_INT_CTRL1_POSTDIV2_MASK 0x7
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#define PLL_INT_CTRL1_PD BIT(24)
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#define PLL_INT_CTRL1_DSMPD BIT(25)
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#define PLL_INT_CTRL1_FOUTPOSTDIVPD BIT(26)
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#define PLL_INT_CTRL1_FOUTVCOPD BIT(27)
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#define PLL_CTRL2 0x8
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#define PLL_FRAC_CTRL2_FRAC_SHIFT 0
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#define PLL_FRAC_CTRL2_FRAC_MASK 0xffffff
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#define PLL_FRAC_CTRL2_POSTDIV1_SHIFT 24
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#define PLL_FRAC_CTRL2_POSTDIV1_MASK 0x7
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#define PLL_FRAC_CTRL2_POSTDIV2_SHIFT 27
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#define PLL_FRAC_CTRL2_POSTDIV2_MASK 0x7
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#define PLL_INT_CTRL2_BYPASS BIT(28)
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#define PLL_CTRL3 0xc
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#define PLL_FRAC_CTRL3_PD BIT(0)
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#define PLL_FRAC_CTRL3_DACPD BIT(1)
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#define PLL_FRAC_CTRL3_DSMPD BIT(2)
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#define PLL_FRAC_CTRL3_FOUTPOSTDIVPD BIT(3)
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#define PLL_FRAC_CTRL3_FOUT4PHASEPD BIT(4)
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#define PLL_FRAC_CTRL3_FOUTVCOPD BIT(5)
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#define PLL_CTRL4 0x10
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#define PLL_FRAC_CTRL4_BYPASS BIT(28)
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#define MIN_PFD 9600000UL
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#define MIN_VCO_LA 400000000UL
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#define MAX_VCO_LA 1600000000UL
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#define MIN_VCO_FRAC_INT 600000000UL
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#define MAX_VCO_FRAC_INT 1600000000UL
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#define MIN_VCO_FRAC_FRAC 600000000UL
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#define MAX_VCO_FRAC_FRAC 2400000000UL
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#define MIN_OUTPUT_LA 8000000UL
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#define MAX_OUTPUT_LA 1600000000UL
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#define MIN_OUTPUT_FRAC 12000000UL
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#define MAX_OUTPUT_FRAC 1600000000UL
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struct pistachio_clk_pll {
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struct clk_hw hw;
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void __iomem *base;
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struct pistachio_pll_rate_table *rates;
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unsigned int nr_rates;
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};
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static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg)
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{
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return readl(pll->base + reg);
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}
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static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg)
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{
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writel(val, pll->base + reg);
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}
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static inline void pll_lock(struct pistachio_clk_pll *pll)
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{
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while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))
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cpu_relax();
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}
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static inline u32 do_div_round_closest(u64 dividend, u32 divisor)
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{
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dividend += divisor / 2;
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do_div(dividend, divisor);
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return dividend;
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}
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static inline struct pistachio_clk_pll *to_pistachio_pll(struct clk_hw *hw)
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{
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return container_of(hw, struct pistachio_clk_pll, hw);
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}
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static struct pistachio_pll_rate_table *
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pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref,
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unsigned long fout)
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{
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unsigned int i;
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for (i = 0; i < pll->nr_rates; i++) {
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if (pll->rates[i].fref == fref && pll->rates[i].fout == fout)
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return &pll->rates[i];
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}
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return NULL;
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}
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static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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unsigned int i;
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for (i = 0; i < pll->nr_rates; i++) {
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if (i > 0 && pll->rates[i].fref == *parent_rate &&
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pll->rates[i].fout <= rate)
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return pll->rates[i - 1].fout;
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}
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return pll->rates[0].fout;
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}
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static int pll_gf40lp_frac_enable(struct clk_hw *hw)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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u32 val;
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val = pll_readl(pll, PLL_CTRL3);
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val &= ~(PLL_FRAC_CTRL3_PD | PLL_FRAC_CTRL3_DACPD |
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PLL_FRAC_CTRL3_DSMPD | PLL_FRAC_CTRL3_FOUTPOSTDIVPD |
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PLL_FRAC_CTRL3_FOUT4PHASEPD | PLL_FRAC_CTRL3_FOUTVCOPD);
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pll_writel(pll, val, PLL_CTRL3);
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val = pll_readl(pll, PLL_CTRL4);
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val &= ~PLL_FRAC_CTRL4_BYPASS;
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pll_writel(pll, val, PLL_CTRL4);
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pll_lock(pll);
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return 0;
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}
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static void pll_gf40lp_frac_disable(struct clk_hw *hw)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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u32 val;
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val = pll_readl(pll, PLL_CTRL3);
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val |= PLL_FRAC_CTRL3_PD;
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pll_writel(pll, val, PLL_CTRL3);
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}
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static int pll_gf40lp_frac_is_enabled(struct clk_hw *hw)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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return !(pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_PD);
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}
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static int pll_gf40lp_frac_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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struct pistachio_pll_rate_table *params;
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int enabled = pll_gf40lp_frac_is_enabled(hw);
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u32 val, vco, old_postdiv1, old_postdiv2;
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const char *name = __clk_get_name(hw->clk);
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if (rate < MIN_OUTPUT_FRAC || rate > MAX_OUTPUT_FRAC)
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return -EINVAL;
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params = pll_get_params(pll, parent_rate, rate);
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if (!params || !params->refdiv)
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return -EINVAL;
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vco = params->fref * params->fbdiv / params->refdiv;
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if (vco < MIN_VCO_FRAC_FRAC || vco > MAX_VCO_FRAC_FRAC)
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pr_warn("%s: VCO %u is out of range %lu..%lu\n", name, vco,
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MIN_VCO_FRAC_FRAC, MAX_VCO_FRAC_FRAC);
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val = params->fref / params->refdiv;
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if (val < MIN_PFD)
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pr_warn("%s: PFD %u is too low (min %lu)\n",
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name, val, MIN_PFD);
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if (val > vco / 16)
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pr_warn("%s: PFD %u is too high (max %u)\n",
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name, val, vco / 16);
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val = pll_readl(pll, PLL_CTRL1);
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val &= ~((PLL_CTRL1_REFDIV_MASK << PLL_CTRL1_REFDIV_SHIFT) |
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(PLL_CTRL1_FBDIV_MASK << PLL_CTRL1_FBDIV_SHIFT));
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val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) |
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(params->fbdiv << PLL_CTRL1_FBDIV_SHIFT);
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pll_writel(pll, val, PLL_CTRL1);
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val = pll_readl(pll, PLL_CTRL2);
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old_postdiv1 = (val >> PLL_FRAC_CTRL2_POSTDIV1_SHIFT) &
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PLL_FRAC_CTRL2_POSTDIV1_MASK;
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old_postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) &
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PLL_FRAC_CTRL2_POSTDIV2_MASK;
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if (enabled &&
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(params->postdiv1 != old_postdiv1 ||
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params->postdiv2 != old_postdiv2))
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pr_warn("%s: changing postdiv while PLL is enabled\n", name);
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if (params->postdiv2 > params->postdiv1)
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pr_warn("%s: postdiv2 should not exceed postdiv1\n", name);
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val &= ~((PLL_FRAC_CTRL2_FRAC_MASK << PLL_FRAC_CTRL2_FRAC_SHIFT) |
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(PLL_FRAC_CTRL2_POSTDIV1_MASK <<
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PLL_FRAC_CTRL2_POSTDIV1_SHIFT) |
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(PLL_FRAC_CTRL2_POSTDIV2_MASK <<
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PLL_FRAC_CTRL2_POSTDIV2_SHIFT));
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val |= (params->frac << PLL_FRAC_CTRL2_FRAC_SHIFT) |
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(params->postdiv1 << PLL_FRAC_CTRL2_POSTDIV1_SHIFT) |
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(params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT);
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pll_writel(pll, val, PLL_CTRL2);
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if (enabled)
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pll_lock(pll);
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return 0;
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}
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static unsigned long pll_gf40lp_frac_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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u32 val, prediv, fbdiv, frac, postdiv1, postdiv2;
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u64 rate = parent_rate;
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val = pll_readl(pll, PLL_CTRL1);
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prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK;
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fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK;
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val = pll_readl(pll, PLL_CTRL2);
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postdiv1 = (val >> PLL_FRAC_CTRL2_POSTDIV1_SHIFT) &
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PLL_FRAC_CTRL2_POSTDIV1_MASK;
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postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) &
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PLL_FRAC_CTRL2_POSTDIV2_MASK;
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frac = (val >> PLL_FRAC_CTRL2_FRAC_SHIFT) & PLL_FRAC_CTRL2_FRAC_MASK;
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rate *= (fbdiv << 24) + frac;
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rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24);
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return rate;
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}
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static struct clk_ops pll_gf40lp_frac_ops = {
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.enable = pll_gf40lp_frac_enable,
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.disable = pll_gf40lp_frac_disable,
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.is_enabled = pll_gf40lp_frac_is_enabled,
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.recalc_rate = pll_gf40lp_frac_recalc_rate,
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.round_rate = pll_round_rate,
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.set_rate = pll_gf40lp_frac_set_rate,
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};
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static struct clk_ops pll_gf40lp_frac_fixed_ops = {
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.enable = pll_gf40lp_frac_enable,
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.disable = pll_gf40lp_frac_disable,
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.is_enabled = pll_gf40lp_frac_is_enabled,
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.recalc_rate = pll_gf40lp_frac_recalc_rate,
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};
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static int pll_gf40lp_laint_enable(struct clk_hw *hw)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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u32 val;
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val = pll_readl(pll, PLL_CTRL1);
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val &= ~(PLL_INT_CTRL1_PD | PLL_INT_CTRL1_DSMPD |
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PLL_INT_CTRL1_FOUTPOSTDIVPD | PLL_INT_CTRL1_FOUTVCOPD);
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pll_writel(pll, val, PLL_CTRL1);
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val = pll_readl(pll, PLL_CTRL2);
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val &= ~PLL_INT_CTRL2_BYPASS;
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pll_writel(pll, val, PLL_CTRL2);
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pll_lock(pll);
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return 0;
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}
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static void pll_gf40lp_laint_disable(struct clk_hw *hw)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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u32 val;
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val = pll_readl(pll, PLL_CTRL1);
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val |= PLL_INT_CTRL1_PD;
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pll_writel(pll, val, PLL_CTRL1);
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}
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static int pll_gf40lp_laint_is_enabled(struct clk_hw *hw)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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return !(pll_readl(pll, PLL_CTRL1) & PLL_INT_CTRL1_PD);
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}
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static int pll_gf40lp_laint_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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struct pistachio_pll_rate_table *params;
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int enabled = pll_gf40lp_laint_is_enabled(hw);
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u32 val, vco, old_postdiv1, old_postdiv2;
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const char *name = __clk_get_name(hw->clk);
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if (rate < MIN_OUTPUT_LA || rate > MAX_OUTPUT_LA)
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return -EINVAL;
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params = pll_get_params(pll, parent_rate, rate);
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if (!params || !params->refdiv)
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return -EINVAL;
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vco = params->fref * params->fbdiv / params->refdiv;
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if (vco < MIN_VCO_LA || vco > MAX_VCO_LA)
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pr_warn("%s: VCO %u is out of range %lu..%lu\n", name, vco,
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MIN_VCO_LA, MAX_VCO_LA);
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val = params->fref / params->refdiv;
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if (val < MIN_PFD)
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pr_warn("%s: PFD %u is too low (min %lu)\n",
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name, val, MIN_PFD);
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if (val > vco / 16)
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pr_warn("%s: PFD %u is too high (max %u)\n",
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name, val, vco / 16);
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val = pll_readl(pll, PLL_CTRL1);
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old_postdiv1 = (val >> PLL_INT_CTRL1_POSTDIV1_SHIFT) &
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PLL_INT_CTRL1_POSTDIV1_MASK;
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old_postdiv2 = (val >> PLL_INT_CTRL1_POSTDIV2_SHIFT) &
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PLL_INT_CTRL1_POSTDIV2_MASK;
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if (enabled &&
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(params->postdiv1 != old_postdiv1 ||
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params->postdiv2 != old_postdiv2))
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pr_warn("%s: changing postdiv while PLL is enabled\n", name);
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if (params->postdiv2 > params->postdiv1)
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pr_warn("%s: postdiv2 should not exceed postdiv1\n", name);
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val &= ~((PLL_CTRL1_REFDIV_MASK << PLL_CTRL1_REFDIV_SHIFT) |
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(PLL_CTRL1_FBDIV_MASK << PLL_CTRL1_FBDIV_SHIFT) |
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(PLL_INT_CTRL1_POSTDIV1_MASK << PLL_INT_CTRL1_POSTDIV1_SHIFT) |
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(PLL_INT_CTRL1_POSTDIV2_MASK << PLL_INT_CTRL1_POSTDIV2_SHIFT));
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val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) |
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(params->fbdiv << PLL_CTRL1_FBDIV_SHIFT) |
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(params->postdiv1 << PLL_INT_CTRL1_POSTDIV1_SHIFT) |
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(params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT);
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pll_writel(pll, val, PLL_CTRL1);
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if (enabled)
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pll_lock(pll);
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return 0;
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}
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static unsigned long pll_gf40lp_laint_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
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u32 val, prediv, fbdiv, postdiv1, postdiv2;
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u64 rate = parent_rate;
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val = pll_readl(pll, PLL_CTRL1);
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prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK;
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fbdiv = (val >> PLL_CTRL1_FBDIV_SHIFT) & PLL_CTRL1_FBDIV_MASK;
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postdiv1 = (val >> PLL_INT_CTRL1_POSTDIV1_SHIFT) &
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PLL_INT_CTRL1_POSTDIV1_MASK;
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postdiv2 = (val >> PLL_INT_CTRL1_POSTDIV2_SHIFT) &
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PLL_INT_CTRL1_POSTDIV2_MASK;
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rate *= fbdiv;
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rate = do_div_round_closest(rate, prediv * postdiv1 * postdiv2);
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return rate;
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}
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static struct clk_ops pll_gf40lp_laint_ops = {
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.enable = pll_gf40lp_laint_enable,
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.disable = pll_gf40lp_laint_disable,
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.is_enabled = pll_gf40lp_laint_is_enabled,
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.recalc_rate = pll_gf40lp_laint_recalc_rate,
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.round_rate = pll_round_rate,
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.set_rate = pll_gf40lp_laint_set_rate,
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};
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static struct clk_ops pll_gf40lp_laint_fixed_ops = {
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.enable = pll_gf40lp_laint_enable,
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.disable = pll_gf40lp_laint_disable,
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.is_enabled = pll_gf40lp_laint_is_enabled,
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.recalc_rate = pll_gf40lp_laint_recalc_rate,
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};
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static struct clk *pll_register(const char *name, const char *parent_name,
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unsigned long flags, void __iomem *base,
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enum pistachio_pll_type type,
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struct pistachio_pll_rate_table *rates,
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unsigned int nr_rates)
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{
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struct pistachio_clk_pll *pll;
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struct clk_init_data init;
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struct clk *clk;
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.flags = flags | CLK_GET_RATE_NOCACHE;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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switch (type) {
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case PLL_GF40LP_FRAC:
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if (rates)
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init.ops = &pll_gf40lp_frac_ops;
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else
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init.ops = &pll_gf40lp_frac_fixed_ops;
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break;
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case PLL_GF40LP_LAINT:
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if (rates)
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init.ops = &pll_gf40lp_laint_ops;
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else
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init.ops = &pll_gf40lp_laint_fixed_ops;
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break;
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default:
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pr_err("Unrecognized PLL type %u\n", type);
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kfree(pll);
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return ERR_PTR(-EINVAL);
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|
}
|
|
|
|
pll->hw.init = &init;
|
|
pll->base = base;
|
|
pll->rates = rates;
|
|
pll->nr_rates = nr_rates;
|
|
|
|
clk = clk_register(NULL, &pll->hw);
|
|
if (IS_ERR(clk))
|
|
kfree(pll);
|
|
|
|
return clk;
|
|
}
|
|
|
|
void pistachio_clk_register_pll(struct pistachio_clk_provider *p,
|
|
struct pistachio_pll *pll,
|
|
unsigned int num)
|
|
{
|
|
struct clk *clk;
|
|
unsigned int i;
|
|
|
|
for (i = 0; i < num; i++) {
|
|
clk = pll_register(pll[i].name, pll[i].parent,
|
|
0, p->base + pll[i].reg_base,
|
|
pll[i].type, pll[i].rates,
|
|
pll[i].nr_rates);
|
|
p->clk_data.clks[pll[i].id] = clk;
|
|
}
|
|
}
|