mirror of https://gitee.com/openkylin/linux.git
1414 lines
38 KiB
C
1414 lines
38 KiB
C
/*
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* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
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*
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* Rewrite, cleanup:
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*
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* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
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* Copyright (C) 2006 Olof Johansson <olof@lixom.net>
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*
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* Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/memblock.h>
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#include <linux/spinlock.h>
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#include <linux/sched.h> /* for show_stack */
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#include <linux/string.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/crash_dump.h>
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#include <linux/memory.h>
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#include <linux/of.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/rtas.h>
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#include <asm/iommu.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/firmware.h>
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#include <asm/tce.h>
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#include <asm/ppc-pci.h>
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#include <asm/udbg.h>
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#include <asm/mmzone.h>
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#include "plpar_wrappers.h"
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static void tce_invalidate_pSeries_sw(struct iommu_table *tbl,
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u64 *startp, u64 *endp)
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{
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u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
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unsigned long start, end, inc;
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start = __pa(startp);
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end = __pa(endp);
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inc = L1_CACHE_BYTES; /* invalidate a cacheline of TCEs at a time */
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/* If this is non-zero, change the format. We shift the
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* address and or in the magic from the device tree. */
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if (tbl->it_busno) {
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start <<= 12;
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end <<= 12;
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inc <<= 12;
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start |= tbl->it_busno;
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end |= tbl->it_busno;
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}
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end |= inc - 1; /* round up end to be different than start */
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mb(); /* Make sure TCEs in memory are written */
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while (start <= end) {
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out_be64(invalidate, start);
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start += inc;
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}
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}
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static int tce_build_pSeries(struct iommu_table *tbl, long index,
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long npages, unsigned long uaddr,
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enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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u64 proto_tce;
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u64 *tcep, *tces;
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u64 rpn;
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proto_tce = TCE_PCI_READ; // Read allowed
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if (direction != DMA_TO_DEVICE)
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proto_tce |= TCE_PCI_WRITE;
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tces = tcep = ((u64 *)tbl->it_base) + index;
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while (npages--) {
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/* can't move this out since we might cross MEMBLOCK boundary */
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rpn = __pa(uaddr) >> TCE_SHIFT;
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*tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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uaddr += TCE_PAGE_SIZE;
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tcep++;
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}
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if (tbl->it_type & TCE_PCI_SWINV_CREATE)
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tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
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return 0;
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}
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static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
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{
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u64 *tcep, *tces;
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tces = tcep = ((u64 *)tbl->it_base) + index;
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while (npages--)
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*(tcep++) = 0;
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if (tbl->it_type & TCE_PCI_SWINV_FREE)
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tce_invalidate_pSeries_sw(tbl, tces, tcep - 1);
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}
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static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
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{
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u64 *tcep;
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tcep = ((u64 *)tbl->it_base) + index;
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return *tcep;
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}
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static void tce_free_pSeriesLP(struct iommu_table*, long, long);
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static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long);
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static int tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
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long npages, unsigned long uaddr,
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enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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u64 rc = 0;
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u64 proto_tce, tce;
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u64 rpn;
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int ret = 0;
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long tcenum_start = tcenum, npages_start = npages;
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rpn = __pa(uaddr) >> TCE_SHIFT;
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proto_tce = TCE_PCI_READ;
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if (direction != DMA_TO_DEVICE)
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proto_tce |= TCE_PCI_WRITE;
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while (npages--) {
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tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
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if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
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ret = (int)rc;
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tce_free_pSeriesLP(tbl, tcenum_start,
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(npages_start - (npages + 1)));
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break;
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}
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if (rc && printk_ratelimit()) {
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printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
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printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
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printk("\ttcenum = 0x%llx\n", (u64)tcenum);
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printk("\ttce val = 0x%llx\n", tce );
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show_stack(current, (unsigned long *)__get_SP());
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}
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tcenum++;
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rpn++;
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}
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return ret;
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}
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static DEFINE_PER_CPU(u64 *, tce_page);
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static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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long npages, unsigned long uaddr,
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enum dma_data_direction direction,
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struct dma_attrs *attrs)
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{
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u64 rc = 0;
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u64 proto_tce;
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u64 *tcep;
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u64 rpn;
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long l, limit;
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long tcenum_start = tcenum, npages_start = npages;
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int ret = 0;
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unsigned long flags;
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if (npages == 1) {
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return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
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direction, attrs);
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}
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local_irq_save(flags); /* to protect tcep and the page behind it */
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tcep = __get_cpu_var(tce_page);
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/* This is safe to do since interrupts are off when we're called
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* from iommu_alloc{,_sg}()
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*/
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if (!tcep) {
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tcep = (u64 *)__get_free_page(GFP_ATOMIC);
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/* If allocation fails, fall back to the loop implementation */
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if (!tcep) {
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local_irq_restore(flags);
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return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
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direction, attrs);
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}
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__get_cpu_var(tce_page) = tcep;
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}
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rpn = __pa(uaddr) >> TCE_SHIFT;
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proto_tce = TCE_PCI_READ;
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if (direction != DMA_TO_DEVICE)
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proto_tce |= TCE_PCI_WRITE;
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/* We can map max one pageful of TCEs at a time */
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do {
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/*
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* Set up the page with TCE data, looping through and setting
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* the values.
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*/
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limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
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for (l = 0; l < limit; l++) {
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tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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rpn++;
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}
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rc = plpar_tce_put_indirect((u64)tbl->it_index,
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(u64)tcenum << 12,
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(u64)__pa(tcep),
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limit);
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npages -= limit;
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tcenum += limit;
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} while (npages > 0 && !rc);
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local_irq_restore(flags);
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if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
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ret = (int)rc;
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tce_freemulti_pSeriesLP(tbl, tcenum_start,
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(npages_start - (npages + limit)));
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return ret;
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}
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if (rc && printk_ratelimit()) {
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printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
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printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
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printk("\tnpages = 0x%llx\n", (u64)npages);
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printk("\ttce[0] val = 0x%llx\n", tcep[0]);
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show_stack(current, (unsigned long *)__get_SP());
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}
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return ret;
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}
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static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
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{
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u64 rc;
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while (npages--) {
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rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
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if (rc && printk_ratelimit()) {
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printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc);
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printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
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printk("\ttcenum = 0x%llx\n", (u64)tcenum);
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show_stack(current, (unsigned long *)__get_SP());
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}
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tcenum++;
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}
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}
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static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
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{
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u64 rc;
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rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
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if (rc && printk_ratelimit()) {
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printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
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printk("\trc = %lld\n", rc);
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printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
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printk("\tnpages = 0x%llx\n", (u64)npages);
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show_stack(current, (unsigned long *)__get_SP());
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}
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}
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static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
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{
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u64 rc;
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unsigned long tce_ret;
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rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
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if (rc && printk_ratelimit()) {
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printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc);
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printk("\tindex = 0x%llx\n", (u64)tbl->it_index);
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printk("\ttcenum = 0x%llx\n", (u64)tcenum);
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show_stack(current, (unsigned long *)__get_SP());
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}
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return tce_ret;
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}
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/* this is compatible with cells for the device tree property */
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struct dynamic_dma_window_prop {
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__be32 liobn; /* tce table number */
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__be64 dma_base; /* address hi,lo */
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__be32 tce_shift; /* ilog2(tce_page_size) */
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__be32 window_shift; /* ilog2(tce_window_size) */
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};
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struct direct_window {
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struct device_node *device;
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const struct dynamic_dma_window_prop *prop;
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struct list_head list;
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};
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/* Dynamic DMA Window support */
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struct ddw_query_response {
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u32 windows_available;
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u32 largest_available_block;
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u32 page_size;
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u32 migration_capable;
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};
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struct ddw_create_response {
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u32 liobn;
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u32 addr_hi;
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u32 addr_lo;
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};
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static LIST_HEAD(direct_window_list);
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/* prevents races between memory on/offline and window creation */
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static DEFINE_SPINLOCK(direct_window_list_lock);
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/* protects initializing window twice for same device */
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static DEFINE_MUTEX(direct_window_init_mutex);
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#define DIRECT64_PROPNAME "linux,direct64-ddr-window-info"
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static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn,
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unsigned long num_pfn, const void *arg)
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{
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const struct dynamic_dma_window_prop *maprange = arg;
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int rc;
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u64 tce_size, num_tce, dma_offset, next;
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u32 tce_shift;
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long limit;
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tce_shift = be32_to_cpu(maprange->tce_shift);
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tce_size = 1ULL << tce_shift;
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next = start_pfn << PAGE_SHIFT;
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num_tce = num_pfn << PAGE_SHIFT;
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/* round back to the beginning of the tce page size */
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num_tce += next & (tce_size - 1);
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next &= ~(tce_size - 1);
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/* covert to number of tces */
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num_tce |= tce_size - 1;
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num_tce >>= tce_shift;
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do {
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/*
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* Set up the page with TCE data, looping through and setting
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* the values.
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*/
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limit = min_t(long, num_tce, 512);
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dma_offset = next + be64_to_cpu(maprange->dma_base);
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rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn),
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dma_offset,
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0, limit);
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next += limit * tce_size;
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num_tce -= limit;
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} while (num_tce > 0 && !rc);
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return rc;
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}
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static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn,
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unsigned long num_pfn, const void *arg)
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{
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const struct dynamic_dma_window_prop *maprange = arg;
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u64 *tcep, tce_size, num_tce, dma_offset, next, proto_tce, liobn;
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u32 tce_shift;
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u64 rc = 0;
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long l, limit;
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local_irq_disable(); /* to protect tcep and the page behind it */
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tcep = __get_cpu_var(tce_page);
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if (!tcep) {
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tcep = (u64 *)__get_free_page(GFP_ATOMIC);
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if (!tcep) {
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local_irq_enable();
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return -ENOMEM;
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}
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__get_cpu_var(tce_page) = tcep;
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}
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proto_tce = TCE_PCI_READ | TCE_PCI_WRITE;
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liobn = (u64)be32_to_cpu(maprange->liobn);
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tce_shift = be32_to_cpu(maprange->tce_shift);
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tce_size = 1ULL << tce_shift;
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next = start_pfn << PAGE_SHIFT;
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num_tce = num_pfn << PAGE_SHIFT;
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/* round back to the beginning of the tce page size */
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num_tce += next & (tce_size - 1);
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next &= ~(tce_size - 1);
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/* covert to number of tces */
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num_tce |= tce_size - 1;
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num_tce >>= tce_shift;
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/* We can map max one pageful of TCEs at a time */
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do {
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/*
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* Set up the page with TCE data, looping through and setting
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* the values.
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*/
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limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
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dma_offset = next + be64_to_cpu(maprange->dma_base);
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for (l = 0; l < limit; l++) {
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tcep[l] = proto_tce | next;
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next += tce_size;
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}
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rc = plpar_tce_put_indirect(liobn,
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dma_offset,
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(u64)__pa(tcep),
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limit);
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num_tce -= limit;
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} while (num_tce > 0 && !rc);
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/* error cleanup: caller will clear whole range */
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local_irq_enable();
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return rc;
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}
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static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn,
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unsigned long num_pfn, void *arg)
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{
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return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg);
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}
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#ifdef CONFIG_PCI
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static void iommu_table_setparms(struct pci_controller *phb,
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struct device_node *dn,
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struct iommu_table *tbl)
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{
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struct device_node *node;
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const unsigned long *basep, *sw_inval;
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const u32 *sizep;
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node = phb->dn;
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basep = of_get_property(node, "linux,tce-base", NULL);
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sizep = of_get_property(node, "linux,tce-size", NULL);
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if (basep == NULL || sizep == NULL) {
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printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
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"missing tce entries !\n", dn->full_name);
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return;
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}
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tbl->it_base = (unsigned long)__va(*basep);
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if (!is_kdump_kernel())
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memset((void *)tbl->it_base, 0, *sizep);
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tbl->it_busno = phb->bus->number;
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/* Units of tce entries */
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tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT;
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/* Test if we are going over 2GB of DMA space */
|
|
if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
|
|
udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
|
|
panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
|
|
}
|
|
|
|
phb->dma_window_base_cur += phb->dma_window_size;
|
|
|
|
/* Set the tce table size - measured in entries */
|
|
tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT;
|
|
|
|
tbl->it_index = 0;
|
|
tbl->it_blocksize = 16;
|
|
tbl->it_type = TCE_PCI;
|
|
|
|
sw_inval = of_get_property(node, "linux,tce-sw-invalidate-info", NULL);
|
|
if (sw_inval) {
|
|
/*
|
|
* This property contains information on how to
|
|
* invalidate the TCE entry. The first property is
|
|
* the base MMIO address used to invalidate entries.
|
|
* The second property tells us the format of the TCE
|
|
* invalidate (whether it needs to be shifted) and
|
|
* some magic routing info to add to our invalidate
|
|
* command.
|
|
*/
|
|
tbl->it_index = (unsigned long) ioremap(sw_inval[0], 8);
|
|
tbl->it_busno = sw_inval[1]; /* overload this with magic */
|
|
tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* iommu_table_setparms_lpar
|
|
*
|
|
* Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
|
|
*/
|
|
static void iommu_table_setparms_lpar(struct pci_controller *phb,
|
|
struct device_node *dn,
|
|
struct iommu_table *tbl,
|
|
const void *dma_window)
|
|
{
|
|
unsigned long offset, size;
|
|
|
|
of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
|
|
|
|
tbl->it_busno = phb->bus->number;
|
|
tbl->it_base = 0;
|
|
tbl->it_blocksize = 16;
|
|
tbl->it_type = TCE_PCI;
|
|
tbl->it_offset = offset >> IOMMU_PAGE_SHIFT;
|
|
tbl->it_size = size >> IOMMU_PAGE_SHIFT;
|
|
}
|
|
|
|
static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
|
|
{
|
|
struct device_node *dn;
|
|
struct iommu_table *tbl;
|
|
struct device_node *isa_dn, *isa_dn_orig;
|
|
struct device_node *tmp;
|
|
struct pci_dn *pci;
|
|
int children;
|
|
|
|
dn = pci_bus_to_OF_node(bus);
|
|
|
|
pr_debug("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name);
|
|
|
|
if (bus->self) {
|
|
/* This is not a root bus, any setup will be done for the
|
|
* device-side of the bridge in iommu_dev_setup_pSeries().
|
|
*/
|
|
return;
|
|
}
|
|
pci = PCI_DN(dn);
|
|
|
|
/* Check if the ISA bus on the system is under
|
|
* this PHB.
|
|
*/
|
|
isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
|
|
|
|
while (isa_dn && isa_dn != dn)
|
|
isa_dn = isa_dn->parent;
|
|
|
|
if (isa_dn_orig)
|
|
of_node_put(isa_dn_orig);
|
|
|
|
/* Count number of direct PCI children of the PHB. */
|
|
for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
|
|
children++;
|
|
|
|
pr_debug("Children: %d\n", children);
|
|
|
|
/* Calculate amount of DMA window per slot. Each window must be
|
|
* a power of two (due to pci_alloc_consistent requirements).
|
|
*
|
|
* Keep 256MB aside for PHBs with ISA.
|
|
*/
|
|
|
|
if (!isa_dn) {
|
|
/* No ISA/IDE - just set window size and return */
|
|
pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
|
|
|
|
while (pci->phb->dma_window_size * children > 0x80000000ul)
|
|
pci->phb->dma_window_size >>= 1;
|
|
pr_debug("No ISA/IDE, window size is 0x%llx\n",
|
|
pci->phb->dma_window_size);
|
|
pci->phb->dma_window_base_cur = 0;
|
|
|
|
return;
|
|
}
|
|
|
|
/* If we have ISA, then we probably have an IDE
|
|
* controller too. Allocate a 128MB table but
|
|
* skip the first 128MB to avoid stepping on ISA
|
|
* space.
|
|
*/
|
|
pci->phb->dma_window_size = 0x8000000ul;
|
|
pci->phb->dma_window_base_cur = 0x8000000ul;
|
|
|
|
tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
|
|
pci->phb->node);
|
|
|
|
iommu_table_setparms(pci->phb, dn, tbl);
|
|
pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
|
|
iommu_register_group(tbl, pci_domain_nr(bus), 0);
|
|
|
|
/* Divide the rest (1.75GB) among the children */
|
|
pci->phb->dma_window_size = 0x80000000ul;
|
|
while (pci->phb->dma_window_size * children > 0x70000000ul)
|
|
pci->phb->dma_window_size >>= 1;
|
|
|
|
pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size);
|
|
}
|
|
|
|
|
|
static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
|
|
{
|
|
struct iommu_table *tbl;
|
|
struct device_node *dn, *pdn;
|
|
struct pci_dn *ppci;
|
|
const void *dma_window = NULL;
|
|
|
|
dn = pci_bus_to_OF_node(bus);
|
|
|
|
pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n",
|
|
dn->full_name);
|
|
|
|
/* Find nearest ibm,dma-window, walking up the device tree */
|
|
for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
|
|
dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
|
|
if (dma_window != NULL)
|
|
break;
|
|
}
|
|
|
|
if (dma_window == NULL) {
|
|
pr_debug(" no ibm,dma-window property !\n");
|
|
return;
|
|
}
|
|
|
|
ppci = PCI_DN(pdn);
|
|
|
|
pr_debug(" parent is %s, iommu_table: 0x%p\n",
|
|
pdn->full_name, ppci->iommu_table);
|
|
|
|
if (!ppci->iommu_table) {
|
|
tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
|
|
ppci->phb->node);
|
|
iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
|
|
ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node);
|
|
iommu_register_group(tbl, pci_domain_nr(bus), 0);
|
|
pr_debug(" created table: %p\n", ppci->iommu_table);
|
|
}
|
|
}
|
|
|
|
|
|
static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
|
|
{
|
|
struct device_node *dn;
|
|
struct iommu_table *tbl;
|
|
|
|
pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
|
|
|
|
dn = dev->dev.of_node;
|
|
|
|
/* If we're the direct child of a root bus, then we need to allocate
|
|
* an iommu table ourselves. The bus setup code should have setup
|
|
* the window sizes already.
|
|
*/
|
|
if (!dev->bus->self) {
|
|
struct pci_controller *phb = PCI_DN(dn)->phb;
|
|
|
|
pr_debug(" --> first child, no bridge. Allocating iommu table.\n");
|
|
tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
|
|
phb->node);
|
|
iommu_table_setparms(phb, dn, tbl);
|
|
PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node);
|
|
iommu_register_group(tbl, pci_domain_nr(phb->bus), 0);
|
|
set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
|
|
return;
|
|
}
|
|
|
|
/* If this device is further down the bus tree, search upwards until
|
|
* an already allocated iommu table is found and use that.
|
|
*/
|
|
|
|
while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL)
|
|
dn = dn->parent;
|
|
|
|
if (dn && PCI_DN(dn))
|
|
set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
|
|
else
|
|
printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
|
|
pci_name(dev));
|
|
}
|
|
|
|
static int __read_mostly disable_ddw;
|
|
|
|
static int __init disable_ddw_setup(char *str)
|
|
{
|
|
disable_ddw = 1;
|
|
printk(KERN_INFO "ppc iommu: disabling ddw.\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
early_param("disable_ddw", disable_ddw_setup);
|
|
|
|
static inline void __remove_ddw(struct device_node *np, const u32 *ddw_avail, u64 liobn)
|
|
{
|
|
int ret;
|
|
|
|
ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
|
|
if (ret)
|
|
pr_warning("%s: failed to remove DMA window: rtas returned "
|
|
"%d to ibm,remove-pe-dma-window(%x) %llx\n",
|
|
np->full_name, ret, ddw_avail[2], liobn);
|
|
else
|
|
pr_debug("%s: successfully removed DMA window: rtas returned "
|
|
"%d to ibm,remove-pe-dma-window(%x) %llx\n",
|
|
np->full_name, ret, ddw_avail[2], liobn);
|
|
}
|
|
|
|
static void remove_ddw(struct device_node *np)
|
|
{
|
|
struct dynamic_dma_window_prop *dwp;
|
|
struct property *win64;
|
|
const u32 *ddw_avail;
|
|
u64 liobn;
|
|
int len, ret;
|
|
|
|
ddw_avail = of_get_property(np, "ibm,ddw-applicable", &len);
|
|
win64 = of_find_property(np, DIRECT64_PROPNAME, NULL);
|
|
if (!win64)
|
|
return;
|
|
|
|
if (!ddw_avail || len < 3 * sizeof(u32) || win64->length < sizeof(*dwp))
|
|
goto delprop;
|
|
|
|
dwp = win64->value;
|
|
liobn = (u64)be32_to_cpu(dwp->liobn);
|
|
|
|
/* clear the whole window, note the arg is in kernel pages */
|
|
ret = tce_clearrange_multi_pSeriesLP(0,
|
|
1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp);
|
|
if (ret)
|
|
pr_warning("%s failed to clear tces in window.\n",
|
|
np->full_name);
|
|
else
|
|
pr_debug("%s successfully cleared tces in window.\n",
|
|
np->full_name);
|
|
|
|
__remove_ddw(np, ddw_avail, liobn);
|
|
|
|
delprop:
|
|
ret = of_remove_property(np, win64);
|
|
if (ret)
|
|
pr_warning("%s: failed to remove direct window property: %d\n",
|
|
np->full_name, ret);
|
|
}
|
|
|
|
static u64 find_existing_ddw(struct device_node *pdn)
|
|
{
|
|
struct direct_window *window;
|
|
const struct dynamic_dma_window_prop *direct64;
|
|
u64 dma_addr = 0;
|
|
|
|
spin_lock(&direct_window_list_lock);
|
|
/* check if we already created a window and dupe that config if so */
|
|
list_for_each_entry(window, &direct_window_list, list) {
|
|
if (window->device == pdn) {
|
|
direct64 = window->prop;
|
|
dma_addr = direct64->dma_base;
|
|
break;
|
|
}
|
|
}
|
|
spin_unlock(&direct_window_list_lock);
|
|
|
|
return dma_addr;
|
|
}
|
|
|
|
static void __restore_default_window(struct eeh_dev *edev,
|
|
u32 ddw_restore_token)
|
|
{
|
|
u32 cfg_addr;
|
|
u64 buid;
|
|
int ret;
|
|
|
|
/*
|
|
* Get the config address and phb buid of the PE window.
|
|
* Rely on eeh to retrieve this for us.
|
|
* Retrieve them from the pci device, not the node with the
|
|
* dma-window property
|
|
*/
|
|
cfg_addr = edev->config_addr;
|
|
if (edev->pe_config_addr)
|
|
cfg_addr = edev->pe_config_addr;
|
|
buid = edev->phb->buid;
|
|
|
|
do {
|
|
ret = rtas_call(ddw_restore_token, 3, 1, NULL, cfg_addr,
|
|
BUID_HI(buid), BUID_LO(buid));
|
|
} while (rtas_busy_delay(ret));
|
|
pr_info("ibm,reset-pe-dma-windows(%x) %x %x %x returned %d\n",
|
|
ddw_restore_token, cfg_addr, BUID_HI(buid), BUID_LO(buid), ret);
|
|
}
|
|
|
|
static int find_existing_ddw_windows(void)
|
|
{
|
|
struct device_node *pdn;
|
|
const struct dynamic_dma_window_prop *direct64;
|
|
const u32 *ddw_extensions;
|
|
|
|
if (!firmware_has_feature(FW_FEATURE_LPAR))
|
|
return 0;
|
|
|
|
for_each_node_with_property(pdn, DIRECT64_PROPNAME) {
|
|
direct64 = of_get_property(pdn, DIRECT64_PROPNAME, NULL);
|
|
if (!direct64)
|
|
continue;
|
|
|
|
/*
|
|
* We need to ensure the IOMMU table is active when we
|
|
* return from the IOMMU setup so that the common code
|
|
* can clear the table or find the holes. To that end,
|
|
* first, remove any existing DDW configuration.
|
|
*/
|
|
remove_ddw(pdn);
|
|
|
|
/*
|
|
* Second, if we are running on a new enough level of
|
|
* firmware where the restore API is present, use it to
|
|
* restore the 32-bit window, which was removed in
|
|
* create_ddw.
|
|
* If the API is not present, then create_ddw couldn't
|
|
* have removed the 32-bit window in the first place, so
|
|
* removing the DDW configuration should be sufficient.
|
|
*/
|
|
ddw_extensions = of_get_property(pdn, "ibm,ddw-extensions",
|
|
NULL);
|
|
if (ddw_extensions && ddw_extensions[0] > 0)
|
|
__restore_default_window(of_node_to_eeh_dev(pdn),
|
|
ddw_extensions[1]);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
machine_arch_initcall(pseries, find_existing_ddw_windows);
|
|
|
|
static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail,
|
|
struct ddw_query_response *query)
|
|
{
|
|
struct eeh_dev *edev;
|
|
u32 cfg_addr;
|
|
u64 buid;
|
|
int ret;
|
|
|
|
/*
|
|
* Get the config address and phb buid of the PE window.
|
|
* Rely on eeh to retrieve this for us.
|
|
* Retrieve them from the pci device, not the node with the
|
|
* dma-window property
|
|
*/
|
|
edev = pci_dev_to_eeh_dev(dev);
|
|
cfg_addr = edev->config_addr;
|
|
if (edev->pe_config_addr)
|
|
cfg_addr = edev->pe_config_addr;
|
|
buid = edev->phb->buid;
|
|
|
|
ret = rtas_call(ddw_avail[0], 3, 5, (u32 *)query,
|
|
cfg_addr, BUID_HI(buid), BUID_LO(buid));
|
|
dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x"
|
|
" returned %d\n", ddw_avail[0], cfg_addr, BUID_HI(buid),
|
|
BUID_LO(buid), ret);
|
|
return ret;
|
|
}
|
|
|
|
static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
|
|
struct ddw_create_response *create, int page_shift,
|
|
int window_shift)
|
|
{
|
|
struct eeh_dev *edev;
|
|
u32 cfg_addr;
|
|
u64 buid;
|
|
int ret;
|
|
|
|
/*
|
|
* Get the config address and phb buid of the PE window.
|
|
* Rely on eeh to retrieve this for us.
|
|
* Retrieve them from the pci device, not the node with the
|
|
* dma-window property
|
|
*/
|
|
edev = pci_dev_to_eeh_dev(dev);
|
|
cfg_addr = edev->config_addr;
|
|
if (edev->pe_config_addr)
|
|
cfg_addr = edev->pe_config_addr;
|
|
buid = edev->phb->buid;
|
|
|
|
do {
|
|
/* extra outputs are LIOBN and dma-addr (hi, lo) */
|
|
ret = rtas_call(ddw_avail[1], 5, 4, (u32 *)create, cfg_addr,
|
|
BUID_HI(buid), BUID_LO(buid), page_shift, window_shift);
|
|
} while (rtas_busy_delay(ret));
|
|
dev_info(&dev->dev,
|
|
"ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d "
|
|
"(liobn = 0x%x starting addr = %x %x)\n", ddw_avail[1],
|
|
cfg_addr, BUID_HI(buid), BUID_LO(buid), page_shift,
|
|
window_shift, ret, create->liobn, create->addr_hi, create->addr_lo);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void restore_default_window(struct pci_dev *dev,
|
|
u32 ddw_restore_token)
|
|
{
|
|
__restore_default_window(pci_dev_to_eeh_dev(dev), ddw_restore_token);
|
|
}
|
|
|
|
struct failed_ddw_pdn {
|
|
struct device_node *pdn;
|
|
struct list_head list;
|
|
};
|
|
|
|
static LIST_HEAD(failed_ddw_pdn_list);
|
|
|
|
/*
|
|
* If the PE supports dynamic dma windows, and there is space for a table
|
|
* that can map all pages in a linear offset, then setup such a table,
|
|
* and record the dma-offset in the struct device.
|
|
*
|
|
* dev: the pci device we are checking
|
|
* pdn: the parent pe node with the ibm,dma_window property
|
|
* Future: also check if we can remap the base window for our base page size
|
|
*
|
|
* returns the dma offset for use by dma_set_mask
|
|
*/
|
|
static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
|
|
{
|
|
int len, ret;
|
|
struct ddw_query_response query;
|
|
struct ddw_create_response create;
|
|
int page_shift;
|
|
u64 dma_addr, max_addr;
|
|
struct device_node *dn;
|
|
const u32 *uninitialized_var(ddw_avail);
|
|
const u32 *uninitialized_var(ddw_extensions);
|
|
u32 ddw_restore_token = 0;
|
|
struct direct_window *window;
|
|
struct property *win64;
|
|
struct dynamic_dma_window_prop *ddwprop;
|
|
const void *dma_window = NULL;
|
|
unsigned long liobn, offset, size;
|
|
struct failed_ddw_pdn *fpdn;
|
|
|
|
mutex_lock(&direct_window_init_mutex);
|
|
|
|
dma_addr = find_existing_ddw(pdn);
|
|
if (dma_addr != 0)
|
|
goto out_unlock;
|
|
|
|
/*
|
|
* If we already went through this for a previous function of
|
|
* the same device and failed, we don't want to muck with the
|
|
* DMA window again, as it will race with in-flight operations
|
|
* and can lead to EEHs. The above mutex protects access to the
|
|
* list.
|
|
*/
|
|
list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) {
|
|
if (!strcmp(fpdn->pdn->full_name, pdn->full_name))
|
|
goto out_unlock;
|
|
}
|
|
|
|
/*
|
|
* the ibm,ddw-applicable property holds the tokens for:
|
|
* ibm,query-pe-dma-window
|
|
* ibm,create-pe-dma-window
|
|
* ibm,remove-pe-dma-window
|
|
* for the given node in that order.
|
|
* the property is actually in the parent, not the PE
|
|
*/
|
|
ddw_avail = of_get_property(pdn, "ibm,ddw-applicable", &len);
|
|
if (!ddw_avail || len < 3 * sizeof(u32))
|
|
goto out_unlock;
|
|
|
|
/*
|
|
* the extensions property is only required to exist in certain
|
|
* levels of firmware and later
|
|
* the ibm,ddw-extensions property is a list with the first
|
|
* element containing the number of extensions and each
|
|
* subsequent entry is a value corresponding to that extension
|
|
*/
|
|
ddw_extensions = of_get_property(pdn, "ibm,ddw-extensions", &len);
|
|
if (ddw_extensions) {
|
|
/*
|
|
* each new defined extension length should be added to
|
|
* the top of the switch so the "earlier" entries also
|
|
* get picked up
|
|
*/
|
|
switch (ddw_extensions[0]) {
|
|
/* ibm,reset-pe-dma-windows */
|
|
case 1:
|
|
ddw_restore_token = ddw_extensions[1];
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Only remove the existing DMA window if we can restore back to
|
|
* the default state. Removing the existing window maximizes the
|
|
* resources available to firmware for dynamic window creation.
|
|
*/
|
|
if (ddw_restore_token) {
|
|
dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
|
|
of_parse_dma_window(pdn, dma_window, &liobn, &offset, &size);
|
|
__remove_ddw(pdn, ddw_avail, liobn);
|
|
}
|
|
|
|
/*
|
|
* Query if there is a second window of size to map the
|
|
* whole partition. Query returns number of windows, largest
|
|
* block assigned to PE (partition endpoint), and two bitmasks
|
|
* of page sizes: supported and supported for migrate-dma.
|
|
*/
|
|
dn = pci_device_to_OF_node(dev);
|
|
ret = query_ddw(dev, ddw_avail, &query);
|
|
if (ret != 0)
|
|
goto out_restore_window;
|
|
|
|
if (query.windows_available == 0) {
|
|
/*
|
|
* no additional windows are available for this device.
|
|
* We might be able to reallocate the existing window,
|
|
* trading in for a larger page size.
|
|
*/
|
|
dev_dbg(&dev->dev, "no free dynamic windows");
|
|
goto out_restore_window;
|
|
}
|
|
if (query.page_size & 4) {
|
|
page_shift = 24; /* 16MB */
|
|
} else if (query.page_size & 2) {
|
|
page_shift = 16; /* 64kB */
|
|
} else if (query.page_size & 1) {
|
|
page_shift = 12; /* 4kB */
|
|
} else {
|
|
dev_dbg(&dev->dev, "no supported direct page size in mask %x",
|
|
query.page_size);
|
|
goto out_restore_window;
|
|
}
|
|
/* verify the window * number of ptes will map the partition */
|
|
/* check largest block * page size > max memory hotplug addr */
|
|
max_addr = memory_hotplug_max();
|
|
if (query.largest_available_block < (max_addr >> page_shift)) {
|
|
dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
|
|
"%llu-sized pages\n", max_addr, query.largest_available_block,
|
|
1ULL << page_shift);
|
|
goto out_restore_window;
|
|
}
|
|
len = order_base_2(max_addr);
|
|
win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
|
|
if (!win64) {
|
|
dev_info(&dev->dev,
|
|
"couldn't allocate property for 64bit dma window\n");
|
|
goto out_restore_window;
|
|
}
|
|
win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
|
|
win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
|
|
win64->length = sizeof(*ddwprop);
|
|
if (!win64->name || !win64->value) {
|
|
dev_info(&dev->dev,
|
|
"couldn't allocate property name and value\n");
|
|
goto out_free_prop;
|
|
}
|
|
|
|
ret = create_ddw(dev, ddw_avail, &create, page_shift, len);
|
|
if (ret != 0)
|
|
goto out_free_prop;
|
|
|
|
ddwprop->liobn = cpu_to_be32(create.liobn);
|
|
ddwprop->dma_base = cpu_to_be64(of_read_number(&create.addr_hi, 2));
|
|
ddwprop->tce_shift = cpu_to_be32(page_shift);
|
|
ddwprop->window_shift = cpu_to_be32(len);
|
|
|
|
dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %s\n",
|
|
create.liobn, dn->full_name);
|
|
|
|
window = kzalloc(sizeof(*window), GFP_KERNEL);
|
|
if (!window)
|
|
goto out_clear_window;
|
|
|
|
ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT,
|
|
win64->value, tce_setrange_multi_pSeriesLP_walk);
|
|
if (ret) {
|
|
dev_info(&dev->dev, "failed to map direct window for %s: %d\n",
|
|
dn->full_name, ret);
|
|
goto out_free_window;
|
|
}
|
|
|
|
ret = of_add_property(pdn, win64);
|
|
if (ret) {
|
|
dev_err(&dev->dev, "unable to add dma window property for %s: %d",
|
|
pdn->full_name, ret);
|
|
goto out_free_window;
|
|
}
|
|
|
|
window->device = pdn;
|
|
window->prop = ddwprop;
|
|
spin_lock(&direct_window_list_lock);
|
|
list_add(&window->list, &direct_window_list);
|
|
spin_unlock(&direct_window_list_lock);
|
|
|
|
dma_addr = of_read_number(&create.addr_hi, 2);
|
|
goto out_unlock;
|
|
|
|
out_free_window:
|
|
kfree(window);
|
|
|
|
out_clear_window:
|
|
remove_ddw(pdn);
|
|
|
|
out_free_prop:
|
|
kfree(win64->name);
|
|
kfree(win64->value);
|
|
kfree(win64);
|
|
|
|
out_restore_window:
|
|
if (ddw_restore_token)
|
|
restore_default_window(dev, ddw_restore_token);
|
|
|
|
fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL);
|
|
if (!fpdn)
|
|
goto out_unlock;
|
|
fpdn->pdn = pdn;
|
|
list_add(&fpdn->list, &failed_ddw_pdn_list);
|
|
|
|
out_unlock:
|
|
mutex_unlock(&direct_window_init_mutex);
|
|
return dma_addr;
|
|
}
|
|
|
|
static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
|
|
{
|
|
struct device_node *pdn, *dn;
|
|
struct iommu_table *tbl;
|
|
const void *dma_window = NULL;
|
|
struct pci_dn *pci;
|
|
|
|
pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
|
|
|
|
/* dev setup for LPAR is a little tricky, since the device tree might
|
|
* contain the dma-window properties per-device and not necessarily
|
|
* for the bus. So we need to search upwards in the tree until we
|
|
* either hit a dma-window property, OR find a parent with a table
|
|
* already allocated.
|
|
*/
|
|
dn = pci_device_to_OF_node(dev);
|
|
pr_debug(" node is %s\n", dn->full_name);
|
|
|
|
for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
|
|
pdn = pdn->parent) {
|
|
dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
|
|
if (dma_window)
|
|
break;
|
|
}
|
|
|
|
if (!pdn || !PCI_DN(pdn)) {
|
|
printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
|
|
"no DMA window found for pci dev=%s dn=%s\n",
|
|
pci_name(dev), of_node_full_name(dn));
|
|
return;
|
|
}
|
|
pr_debug(" parent is %s\n", pdn->full_name);
|
|
|
|
pci = PCI_DN(pdn);
|
|
if (!pci->iommu_table) {
|
|
tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
|
|
pci->phb->node);
|
|
iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
|
|
pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
|
|
iommu_register_group(tbl, pci_domain_nr(pci->phb->bus), 0);
|
|
pr_debug(" created table: %p\n", pci->iommu_table);
|
|
} else {
|
|
pr_debug(" found DMA window, table: %p\n", pci->iommu_table);
|
|
}
|
|
|
|
set_iommu_table_base(&dev->dev, pci->iommu_table);
|
|
}
|
|
|
|
static int dma_set_mask_pSeriesLP(struct device *dev, u64 dma_mask)
|
|
{
|
|
bool ddw_enabled = false;
|
|
struct device_node *pdn, *dn;
|
|
struct pci_dev *pdev;
|
|
const void *dma_window = NULL;
|
|
u64 dma_offset;
|
|
|
|
if (!dev->dma_mask)
|
|
return -EIO;
|
|
|
|
if (!dev_is_pci(dev))
|
|
goto check_mask;
|
|
|
|
pdev = to_pci_dev(dev);
|
|
|
|
/* only attempt to use a new window if 64-bit DMA is requested */
|
|
if (!disable_ddw && dma_mask == DMA_BIT_MASK(64)) {
|
|
dn = pci_device_to_OF_node(pdev);
|
|
dev_dbg(dev, "node is %s\n", dn->full_name);
|
|
|
|
/*
|
|
* the device tree might contain the dma-window properties
|
|
* per-device and not necessarily for the bus. So we need to
|
|
* search upwards in the tree until we either hit a dma-window
|
|
* property, OR find a parent with a table already allocated.
|
|
*/
|
|
for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
|
|
pdn = pdn->parent) {
|
|
dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
|
|
if (dma_window)
|
|
break;
|
|
}
|
|
if (pdn && PCI_DN(pdn)) {
|
|
dma_offset = enable_ddw(pdev, pdn);
|
|
if (dma_offset != 0) {
|
|
dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
|
|
set_dma_offset(dev, dma_offset);
|
|
set_dma_ops(dev, &dma_direct_ops);
|
|
ddw_enabled = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* fall back on iommu ops, restore table pointer with ops */
|
|
if (!ddw_enabled && get_dma_ops(dev) != &dma_iommu_ops) {
|
|
dev_info(dev, "Restoring 32-bit DMA via iommu\n");
|
|
set_dma_ops(dev, &dma_iommu_ops);
|
|
pci_dma_dev_setup_pSeriesLP(pdev);
|
|
}
|
|
|
|
check_mask:
|
|
if (!dma_supported(dev, dma_mask))
|
|
return -EIO;
|
|
|
|
*dev->dma_mask = dma_mask;
|
|
return 0;
|
|
}
|
|
|
|
static u64 dma_get_required_mask_pSeriesLP(struct device *dev)
|
|
{
|
|
if (!dev->dma_mask)
|
|
return 0;
|
|
|
|
if (!disable_ddw && dev_is_pci(dev)) {
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct device_node *dn;
|
|
|
|
dn = pci_device_to_OF_node(pdev);
|
|
|
|
/* search upwards for ibm,dma-window */
|
|
for (; dn && PCI_DN(dn) && !PCI_DN(dn)->iommu_table;
|
|
dn = dn->parent)
|
|
if (of_get_property(dn, "ibm,dma-window", NULL))
|
|
break;
|
|
/* if there is a ibm,ddw-applicable property require 64 bits */
|
|
if (dn && PCI_DN(dn) &&
|
|
of_get_property(dn, "ibm,ddw-applicable", NULL))
|
|
return DMA_BIT_MASK(64);
|
|
}
|
|
|
|
return dma_iommu_ops.get_required_mask(dev);
|
|
}
|
|
|
|
#else /* CONFIG_PCI */
|
|
#define pci_dma_bus_setup_pSeries NULL
|
|
#define pci_dma_dev_setup_pSeries NULL
|
|
#define pci_dma_bus_setup_pSeriesLP NULL
|
|
#define pci_dma_dev_setup_pSeriesLP NULL
|
|
#define dma_set_mask_pSeriesLP NULL
|
|
#define dma_get_required_mask_pSeriesLP NULL
|
|
#endif /* !CONFIG_PCI */
|
|
|
|
static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action,
|
|
void *data)
|
|
{
|
|
struct direct_window *window;
|
|
struct memory_notify *arg = data;
|
|
int ret = 0;
|
|
|
|
switch (action) {
|
|
case MEM_GOING_ONLINE:
|
|
spin_lock(&direct_window_list_lock);
|
|
list_for_each_entry(window, &direct_window_list, list) {
|
|
ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn,
|
|
arg->nr_pages, window->prop);
|
|
/* XXX log error */
|
|
}
|
|
spin_unlock(&direct_window_list_lock);
|
|
break;
|
|
case MEM_CANCEL_ONLINE:
|
|
case MEM_OFFLINE:
|
|
spin_lock(&direct_window_list_lock);
|
|
list_for_each_entry(window, &direct_window_list, list) {
|
|
ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn,
|
|
arg->nr_pages, window->prop);
|
|
/* XXX log error */
|
|
}
|
|
spin_unlock(&direct_window_list_lock);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
if (ret && action != MEM_CANCEL_ONLINE)
|
|
return NOTIFY_BAD;
|
|
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block iommu_mem_nb = {
|
|
.notifier_call = iommu_mem_notifier,
|
|
};
|
|
|
|
static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
|
|
{
|
|
int err = NOTIFY_OK;
|
|
struct device_node *np = node;
|
|
struct pci_dn *pci = PCI_DN(np);
|
|
struct direct_window *window;
|
|
|
|
switch (action) {
|
|
case OF_RECONFIG_DETACH_NODE:
|
|
remove_ddw(np);
|
|
if (pci && pci->iommu_table)
|
|
iommu_free_table(pci->iommu_table, np->full_name);
|
|
|
|
spin_lock(&direct_window_list_lock);
|
|
list_for_each_entry(window, &direct_window_list, list) {
|
|
if (window->device == np) {
|
|
list_del(&window->list);
|
|
kfree(window);
|
|
break;
|
|
}
|
|
}
|
|
spin_unlock(&direct_window_list_lock);
|
|
break;
|
|
default:
|
|
err = NOTIFY_DONE;
|
|
break;
|
|
}
|
|
return err;
|
|
}
|
|
|
|
static struct notifier_block iommu_reconfig_nb = {
|
|
.notifier_call = iommu_reconfig_notifier,
|
|
};
|
|
|
|
/* These are called very early. */
|
|
void iommu_init_early_pSeries(void)
|
|
{
|
|
if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL))
|
|
return;
|
|
|
|
if (firmware_has_feature(FW_FEATURE_LPAR)) {
|
|
if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
|
|
ppc_md.tce_build = tce_buildmulti_pSeriesLP;
|
|
ppc_md.tce_free = tce_freemulti_pSeriesLP;
|
|
} else {
|
|
ppc_md.tce_build = tce_build_pSeriesLP;
|
|
ppc_md.tce_free = tce_free_pSeriesLP;
|
|
}
|
|
ppc_md.tce_get = tce_get_pSeriesLP;
|
|
ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
|
|
ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
|
|
ppc_md.dma_set_mask = dma_set_mask_pSeriesLP;
|
|
ppc_md.dma_get_required_mask = dma_get_required_mask_pSeriesLP;
|
|
} else {
|
|
ppc_md.tce_build = tce_build_pSeries;
|
|
ppc_md.tce_free = tce_free_pSeries;
|
|
ppc_md.tce_get = tce_get_pseries;
|
|
ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries;
|
|
ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries;
|
|
}
|
|
|
|
|
|
of_reconfig_notifier_register(&iommu_reconfig_nb);
|
|
register_memory_notifier(&iommu_mem_nb);
|
|
|
|
set_pci_dma_ops(&dma_iommu_ops);
|
|
}
|
|
|
|
static int __init disable_multitce(char *str)
|
|
{
|
|
if (strcmp(str, "off") == 0 &&
|
|
firmware_has_feature(FW_FEATURE_LPAR) &&
|
|
firmware_has_feature(FW_FEATURE_MULTITCE)) {
|
|
printk(KERN_INFO "Disabling MULTITCE firmware feature\n");
|
|
ppc_md.tce_build = tce_build_pSeriesLP;
|
|
ppc_md.tce_free = tce_free_pSeriesLP;
|
|
powerpc_firmware_features &= ~FW_FEATURE_MULTITCE;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
__setup("multitce=", disable_multitce);
|