mirror of https://gitee.com/openkylin/linux.git
879 lines
26 KiB
C
879 lines
26 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <drm/drmP.h>
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#include "radeon.h"
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#include <drm/radeon_drm.h>
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#include "radeon_asic.h"
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#include <linux/vga_switcheroo.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#if defined(CONFIG_VGA_SWITCHEROO)
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bool radeon_has_atpx(void);
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#else
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static inline bool radeon_has_atpx(void) { return false; }
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#endif
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/**
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* radeon_driver_unload_kms - Main unload function for KMS.
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*
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* @dev: drm dev pointer
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*
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* This is the main unload function for KMS (all asics).
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* It calls radeon_modeset_fini() to tear down the
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* displays, and radeon_device_fini() to tear down
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* the rest of the device (CP, writeback, etc.).
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* Returns 0 on success.
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*/
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int radeon_driver_unload_kms(struct drm_device *dev)
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{
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struct radeon_device *rdev = dev->dev_private;
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if (rdev == NULL)
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return 0;
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if (rdev->rmmio == NULL)
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goto done_free;
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pm_runtime_get_sync(dev->dev);
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radeon_acpi_fini(rdev);
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radeon_modeset_fini(rdev);
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radeon_device_fini(rdev);
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done_free:
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kfree(rdev);
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dev->dev_private = NULL;
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return 0;
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}
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/**
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* radeon_driver_load_kms - Main load function for KMS.
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*
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* @dev: drm dev pointer
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* @flags: device flags
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*
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* This is the main load function for KMS (all asics).
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* It calls radeon_device_init() to set up the non-display
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* parts of the chip (asic init, CP, writeback, etc.), and
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* radeon_modeset_init() to set up the display parts
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* (crtcs, encoders, hotplug detect, etc.).
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* Returns 0 on success, error on failure.
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*/
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int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
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{
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struct radeon_device *rdev;
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int r, acpi_status;
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rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
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if (rdev == NULL) {
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return -ENOMEM;
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}
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dev->dev_private = (void *)rdev;
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/* update BUS flag */
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if (drm_pci_device_is_agp(dev)) {
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flags |= RADEON_IS_AGP;
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} else if (pci_is_pcie(dev->pdev)) {
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flags |= RADEON_IS_PCIE;
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} else {
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flags |= RADEON_IS_PCI;
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}
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if ((radeon_runtime_pm != 0) &&
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radeon_has_atpx() &&
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((flags & RADEON_IS_IGP) == 0))
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flags |= RADEON_IS_PX;
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/* radeon_device_init should report only fatal error
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* like memory allocation failure or iomapping failure,
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* or memory manager initialization failure, it must
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* properly initialize the GPU MC controller and permit
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* VRAM allocation
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*/
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r = radeon_device_init(rdev, dev, dev->pdev, flags);
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if (r) {
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dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
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goto out;
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}
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/* Again modeset_init should fail only on fatal error
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* otherwise it should provide enough functionalities
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* for shadowfb to run
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*/
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r = radeon_modeset_init(rdev);
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if (r)
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dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
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/* Call ACPI methods: require modeset init
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* but failure is not fatal
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*/
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if (!r) {
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acpi_status = radeon_acpi_init(rdev);
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if (acpi_status)
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dev_dbg(&dev->pdev->dev,
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"Error during ACPI methods call\n");
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}
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if (radeon_is_px(dev)) {
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pm_runtime_use_autosuspend(dev->dev);
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pm_runtime_set_autosuspend_delay(dev->dev, 5000);
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pm_runtime_set_active(dev->dev);
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pm_runtime_allow(dev->dev);
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pm_runtime_mark_last_busy(dev->dev);
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pm_runtime_put_autosuspend(dev->dev);
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}
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out:
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if (r)
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radeon_driver_unload_kms(dev);
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return r;
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}
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/**
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* radeon_set_filp_rights - Set filp right.
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*
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* @dev: drm dev pointer
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* @owner: drm file
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* @applier: drm file
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* @value: value
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*
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* Sets the filp rights for the device (all asics).
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*/
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static void radeon_set_filp_rights(struct drm_device *dev,
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struct drm_file **owner,
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struct drm_file *applier,
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uint32_t *value)
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{
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mutex_lock(&dev->struct_mutex);
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if (*value == 1) {
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/* wants rights */
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if (!*owner)
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*owner = applier;
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} else if (*value == 0) {
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/* revokes rights */
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if (*owner == applier)
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*owner = NULL;
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}
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*value = *owner == applier ? 1 : 0;
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mutex_unlock(&dev->struct_mutex);
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}
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/*
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* Userspace get information ioctl
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*/
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/**
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* radeon_info_ioctl - answer a device specific request.
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*
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* @rdev: radeon device pointer
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* @data: request object
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* @filp: drm filp
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*
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* This function is used to pass device specific parameters to the userspace
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* drivers. Examples include: pci device id, pipeline parms, tiling params,
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* etc. (all asics).
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* Returns 0 on success, -EINVAL on failure.
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*/
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static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
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{
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struct radeon_device *rdev = dev->dev_private;
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struct drm_radeon_info *info = data;
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struct radeon_mode_info *minfo = &rdev->mode_info;
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uint32_t *value, value_tmp, *value_ptr, value_size;
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uint64_t value64;
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struct drm_crtc *crtc;
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int i, found;
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value_ptr = (uint32_t *)((unsigned long)info->value);
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value = &value_tmp;
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value_size = sizeof(uint32_t);
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switch (info->request) {
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case RADEON_INFO_DEVICE_ID:
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*value = dev->pdev->device;
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break;
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case RADEON_INFO_NUM_GB_PIPES:
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*value = rdev->num_gb_pipes;
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break;
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case RADEON_INFO_NUM_Z_PIPES:
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*value = rdev->num_z_pipes;
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break;
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case RADEON_INFO_ACCEL_WORKING:
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/* xf86-video-ati 6.13.0 relies on this being false for evergreen */
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if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
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*value = false;
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else
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*value = rdev->accel_working;
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break;
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case RADEON_INFO_CRTC_FROM_ID:
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if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
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DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
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return -EFAULT;
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}
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for (i = 0, found = 0; i < rdev->num_crtc; i++) {
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crtc = (struct drm_crtc *)minfo->crtcs[i];
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if (crtc && crtc->base.id == *value) {
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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*value = radeon_crtc->crtc_id;
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found = 1;
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break;
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}
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}
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if (!found) {
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DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
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return -EINVAL;
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}
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break;
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case RADEON_INFO_ACCEL_WORKING2:
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*value = rdev->accel_working;
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break;
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case RADEON_INFO_TILING_CONFIG:
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if (rdev->family >= CHIP_BONAIRE)
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*value = rdev->config.cik.tile_config;
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else if (rdev->family >= CHIP_TAHITI)
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*value = rdev->config.si.tile_config;
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else if (rdev->family >= CHIP_CAYMAN)
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*value = rdev->config.cayman.tile_config;
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else if (rdev->family >= CHIP_CEDAR)
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*value = rdev->config.evergreen.tile_config;
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else if (rdev->family >= CHIP_RV770)
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*value = rdev->config.rv770.tile_config;
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else if (rdev->family >= CHIP_R600)
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*value = rdev->config.r600.tile_config;
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else {
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DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
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return -EINVAL;
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}
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break;
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case RADEON_INFO_WANT_HYPERZ:
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/* The "value" here is both an input and output parameter.
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* If the input value is 1, filp requests hyper-z access.
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* If the input value is 0, filp revokes its hyper-z access.
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*
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* When returning, the value is 1 if filp owns hyper-z access,
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* 0 otherwise. */
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if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
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DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
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return -EFAULT;
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}
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if (*value >= 2) {
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DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
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return -EINVAL;
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}
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radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
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break;
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case RADEON_INFO_WANT_CMASK:
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/* The same logic as Hyper-Z. */
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if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
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DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
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return -EFAULT;
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}
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if (*value >= 2) {
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DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
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return -EINVAL;
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}
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radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
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break;
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case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
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/* return clock value in KHz */
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if (rdev->asic->get_xclk)
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*value = radeon_get_xclk(rdev) * 10;
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else
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*value = rdev->clock.spll.reference_freq * 10;
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break;
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case RADEON_INFO_NUM_BACKENDS:
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if (rdev->family >= CHIP_BONAIRE)
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*value = rdev->config.cik.max_backends_per_se *
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rdev->config.cik.max_shader_engines;
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else if (rdev->family >= CHIP_TAHITI)
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*value = rdev->config.si.max_backends_per_se *
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rdev->config.si.max_shader_engines;
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else if (rdev->family >= CHIP_CAYMAN)
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*value = rdev->config.cayman.max_backends_per_se *
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rdev->config.cayman.max_shader_engines;
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else if (rdev->family >= CHIP_CEDAR)
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*value = rdev->config.evergreen.max_backends;
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else if (rdev->family >= CHIP_RV770)
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*value = rdev->config.rv770.max_backends;
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else if (rdev->family >= CHIP_R600)
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*value = rdev->config.r600.max_backends;
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else {
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return -EINVAL;
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}
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break;
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case RADEON_INFO_NUM_TILE_PIPES:
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if (rdev->family >= CHIP_BONAIRE)
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*value = rdev->config.cik.max_tile_pipes;
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else if (rdev->family >= CHIP_TAHITI)
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*value = rdev->config.si.max_tile_pipes;
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else if (rdev->family >= CHIP_CAYMAN)
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*value = rdev->config.cayman.max_tile_pipes;
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else if (rdev->family >= CHIP_CEDAR)
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*value = rdev->config.evergreen.max_tile_pipes;
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else if (rdev->family >= CHIP_RV770)
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*value = rdev->config.rv770.max_tile_pipes;
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else if (rdev->family >= CHIP_R600)
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*value = rdev->config.r600.max_tile_pipes;
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else {
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return -EINVAL;
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}
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break;
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case RADEON_INFO_FUSION_GART_WORKING:
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*value = 1;
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break;
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case RADEON_INFO_BACKEND_MAP:
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if (rdev->family >= CHIP_BONAIRE)
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*value = rdev->config.cik.backend_map;
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else if (rdev->family >= CHIP_TAHITI)
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*value = rdev->config.si.backend_map;
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else if (rdev->family >= CHIP_CAYMAN)
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*value = rdev->config.cayman.backend_map;
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else if (rdev->family >= CHIP_CEDAR)
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*value = rdev->config.evergreen.backend_map;
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else if (rdev->family >= CHIP_RV770)
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*value = rdev->config.rv770.backend_map;
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else if (rdev->family >= CHIP_R600)
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*value = rdev->config.r600.backend_map;
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else {
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return -EINVAL;
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}
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break;
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case RADEON_INFO_VA_START:
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/* this is where we report if vm is supported or not */
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if (rdev->family < CHIP_CAYMAN)
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return -EINVAL;
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*value = RADEON_VA_RESERVED_SIZE;
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break;
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case RADEON_INFO_IB_VM_MAX_SIZE:
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/* this is where we report if vm is supported or not */
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if (rdev->family < CHIP_CAYMAN)
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return -EINVAL;
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*value = RADEON_IB_VM_MAX_SIZE;
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break;
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case RADEON_INFO_MAX_PIPES:
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if (rdev->family >= CHIP_BONAIRE)
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*value = rdev->config.cik.max_cu_per_sh;
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else if (rdev->family >= CHIP_TAHITI)
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*value = rdev->config.si.max_cu_per_sh;
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else if (rdev->family >= CHIP_CAYMAN)
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*value = rdev->config.cayman.max_pipes_per_simd;
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else if (rdev->family >= CHIP_CEDAR)
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*value = rdev->config.evergreen.max_pipes;
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else if (rdev->family >= CHIP_RV770)
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*value = rdev->config.rv770.max_pipes;
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else if (rdev->family >= CHIP_R600)
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*value = rdev->config.r600.max_pipes;
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else {
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return -EINVAL;
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}
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break;
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case RADEON_INFO_TIMESTAMP:
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if (rdev->family < CHIP_R600) {
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DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
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return -EINVAL;
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}
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value = (uint32_t*)&value64;
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value_size = sizeof(uint64_t);
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value64 = radeon_get_gpu_clock_counter(rdev);
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break;
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case RADEON_INFO_MAX_SE:
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if (rdev->family >= CHIP_BONAIRE)
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*value = rdev->config.cik.max_shader_engines;
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else if (rdev->family >= CHIP_TAHITI)
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*value = rdev->config.si.max_shader_engines;
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else if (rdev->family >= CHIP_CAYMAN)
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*value = rdev->config.cayman.max_shader_engines;
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else if (rdev->family >= CHIP_CEDAR)
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*value = rdev->config.evergreen.num_ses;
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else
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*value = 1;
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break;
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case RADEON_INFO_MAX_SH_PER_SE:
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if (rdev->family >= CHIP_BONAIRE)
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*value = rdev->config.cik.max_sh_per_se;
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else if (rdev->family >= CHIP_TAHITI)
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*value = rdev->config.si.max_sh_per_se;
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else
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return -EINVAL;
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break;
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case RADEON_INFO_FASTFB_WORKING:
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*value = rdev->fastfb_working;
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break;
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case RADEON_INFO_RING_WORKING:
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if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
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DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
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return -EFAULT;
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}
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switch (*value) {
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case RADEON_CS_RING_GFX:
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case RADEON_CS_RING_COMPUTE:
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*value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
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break;
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case RADEON_CS_RING_DMA:
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*value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
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*value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
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break;
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case RADEON_CS_RING_UVD:
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*value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
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break;
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case RADEON_CS_RING_VCE:
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*value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
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break;
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default:
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return -EINVAL;
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}
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break;
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case RADEON_INFO_SI_TILE_MODE_ARRAY:
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if (rdev->family >= CHIP_BONAIRE) {
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value = rdev->config.cik.tile_mode_array;
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value_size = sizeof(uint32_t)*32;
|
|
} else if (rdev->family >= CHIP_TAHITI) {
|
|
value = rdev->config.si.tile_mode_array;
|
|
value_size = sizeof(uint32_t)*32;
|
|
} else {
|
|
DRM_DEBUG_KMS("tile mode array is si+ only!\n");
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
|
|
if (rdev->family >= CHIP_BONAIRE) {
|
|
value = rdev->config.cik.macrotile_mode_array;
|
|
value_size = sizeof(uint32_t)*16;
|
|
} else {
|
|
DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
|
|
return -EINVAL;
|
|
}
|
|
break;
|
|
case RADEON_INFO_SI_CP_DMA_COMPUTE:
|
|
*value = 1;
|
|
break;
|
|
case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
|
|
if (rdev->family >= CHIP_BONAIRE) {
|
|
*value = rdev->config.cik.backend_enable_mask;
|
|
} else if (rdev->family >= CHIP_TAHITI) {
|
|
*value = rdev->config.si.backend_enable_mask;
|
|
} else {
|
|
DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
|
|
}
|
|
break;
|
|
case RADEON_INFO_MAX_SCLK:
|
|
if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
|
|
rdev->pm.dpm_enabled)
|
|
*value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
|
|
else
|
|
*value = rdev->pm.default_sclk * 10;
|
|
break;
|
|
case RADEON_INFO_VCE_FW_VERSION:
|
|
*value = rdev->vce.fw_version;
|
|
break;
|
|
case RADEON_INFO_VCE_FB_VERSION:
|
|
*value = rdev->vce.fb_version;
|
|
break;
|
|
case RADEON_INFO_NUM_BYTES_MOVED:
|
|
value = (uint32_t*)&value64;
|
|
value_size = sizeof(uint64_t);
|
|
value64 = atomic64_read(&rdev->num_bytes_moved);
|
|
break;
|
|
case RADEON_INFO_VRAM_USAGE:
|
|
value = (uint32_t*)&value64;
|
|
value_size = sizeof(uint64_t);
|
|
value64 = atomic64_read(&rdev->vram_usage);
|
|
break;
|
|
case RADEON_INFO_GTT_USAGE:
|
|
value = (uint32_t*)&value64;
|
|
value_size = sizeof(uint64_t);
|
|
value64 = atomic64_read(&rdev->gtt_usage);
|
|
break;
|
|
case RADEON_INFO_ACTIVE_CU_COUNT:
|
|
if (rdev->family >= CHIP_BONAIRE)
|
|
*value = rdev->config.cik.active_cus;
|
|
else if (rdev->family >= CHIP_TAHITI)
|
|
*value = rdev->config.si.active_cus;
|
|
else if (rdev->family >= CHIP_CAYMAN)
|
|
*value = rdev->config.cayman.active_simds;
|
|
else if (rdev->family >= CHIP_CEDAR)
|
|
*value = rdev->config.evergreen.active_simds;
|
|
else if (rdev->family >= CHIP_RV770)
|
|
*value = rdev->config.rv770.active_simds;
|
|
else if (rdev->family >= CHIP_R600)
|
|
*value = rdev->config.r600.active_simds;
|
|
else
|
|
*value = 1;
|
|
break;
|
|
default:
|
|
DRM_DEBUG_KMS("Invalid request %d\n", info->request);
|
|
return -EINVAL;
|
|
}
|
|
if (copy_to_user(value_ptr, (char*)value, value_size)) {
|
|
DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
|
|
return -EFAULT;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
/*
|
|
* Outdated mess for old drm with Xorg being in charge (void function now).
|
|
*/
|
|
/**
|
|
* radeon_driver_firstopen_kms - drm callback for last close
|
|
*
|
|
* @dev: drm dev pointer
|
|
*
|
|
* Switch vga switcheroo state after last close (all asics).
|
|
*/
|
|
void radeon_driver_lastclose_kms(struct drm_device *dev)
|
|
{
|
|
vga_switcheroo_process_delayed_switch();
|
|
}
|
|
|
|
/**
|
|
* radeon_driver_open_kms - drm callback for open
|
|
*
|
|
* @dev: drm dev pointer
|
|
* @file_priv: drm file
|
|
*
|
|
* On device open, init vm on cayman+ (all asics).
|
|
* Returns 0 on success, error on failure.
|
|
*/
|
|
int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
|
|
{
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
int r;
|
|
|
|
file_priv->driver_priv = NULL;
|
|
|
|
r = pm_runtime_get_sync(dev->dev);
|
|
if (r < 0)
|
|
return r;
|
|
|
|
/* new gpu have virtual address space support */
|
|
if (rdev->family >= CHIP_CAYMAN) {
|
|
struct radeon_fpriv *fpriv;
|
|
struct radeon_bo_va *bo_va;
|
|
int r;
|
|
|
|
fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
|
|
if (unlikely(!fpriv)) {
|
|
return -ENOMEM;
|
|
}
|
|
|
|
r = radeon_vm_init(rdev, &fpriv->vm);
|
|
if (r) {
|
|
kfree(fpriv);
|
|
return r;
|
|
}
|
|
|
|
if (rdev->accel_working) {
|
|
r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
|
|
if (r) {
|
|
radeon_vm_fini(rdev, &fpriv->vm);
|
|
kfree(fpriv);
|
|
return r;
|
|
}
|
|
|
|
/* map the ib pool buffer read only into
|
|
* virtual address space */
|
|
bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
|
|
rdev->ring_tmp_bo.bo);
|
|
r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
|
|
RADEON_VM_PAGE_READABLE |
|
|
RADEON_VM_PAGE_SNOOPED);
|
|
|
|
radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
|
|
if (r) {
|
|
radeon_vm_fini(rdev, &fpriv->vm);
|
|
kfree(fpriv);
|
|
return r;
|
|
}
|
|
}
|
|
file_priv->driver_priv = fpriv;
|
|
}
|
|
|
|
pm_runtime_mark_last_busy(dev->dev);
|
|
pm_runtime_put_autosuspend(dev->dev);
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* radeon_driver_postclose_kms - drm callback for post close
|
|
*
|
|
* @dev: drm dev pointer
|
|
* @file_priv: drm file
|
|
*
|
|
* On device post close, tear down vm on cayman+ (all asics).
|
|
*/
|
|
void radeon_driver_postclose_kms(struct drm_device *dev,
|
|
struct drm_file *file_priv)
|
|
{
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
/* new gpu have virtual address space support */
|
|
if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
|
|
struct radeon_fpriv *fpriv = file_priv->driver_priv;
|
|
struct radeon_bo_va *bo_va;
|
|
int r;
|
|
|
|
if (rdev->accel_working) {
|
|
r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
|
|
if (!r) {
|
|
bo_va = radeon_vm_bo_find(&fpriv->vm,
|
|
rdev->ring_tmp_bo.bo);
|
|
if (bo_va)
|
|
radeon_vm_bo_rmv(rdev, bo_va);
|
|
radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
|
|
}
|
|
}
|
|
|
|
radeon_vm_fini(rdev, &fpriv->vm);
|
|
kfree(fpriv);
|
|
file_priv->driver_priv = NULL;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* radeon_driver_preclose_kms - drm callback for pre close
|
|
*
|
|
* @dev: drm dev pointer
|
|
* @file_priv: drm file
|
|
*
|
|
* On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
|
|
* (all asics).
|
|
*/
|
|
void radeon_driver_preclose_kms(struct drm_device *dev,
|
|
struct drm_file *file_priv)
|
|
{
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
if (rdev->hyperz_filp == file_priv)
|
|
rdev->hyperz_filp = NULL;
|
|
if (rdev->cmask_filp == file_priv)
|
|
rdev->cmask_filp = NULL;
|
|
radeon_uvd_free_handles(rdev, file_priv);
|
|
radeon_vce_free_handles(rdev, file_priv);
|
|
}
|
|
|
|
/*
|
|
* VBlank related functions.
|
|
*/
|
|
/**
|
|
* radeon_get_vblank_counter_kms - get frame count
|
|
*
|
|
* @dev: drm dev pointer
|
|
* @crtc: crtc to get the frame count from
|
|
*
|
|
* Gets the frame count on the requested crtc (all asics).
|
|
* Returns frame count on success, -EINVAL on failure.
|
|
*/
|
|
u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
|
|
{
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
if (crtc < 0 || crtc >= rdev->num_crtc) {
|
|
DRM_ERROR("Invalid crtc %d\n", crtc);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return radeon_get_vblank_counter(rdev, crtc);
|
|
}
|
|
|
|
/**
|
|
* radeon_enable_vblank_kms - enable vblank interrupt
|
|
*
|
|
* @dev: drm dev pointer
|
|
* @crtc: crtc to enable vblank interrupt for
|
|
*
|
|
* Enable the interrupt on the requested crtc (all asics).
|
|
* Returns 0 on success, -EINVAL on failure.
|
|
*/
|
|
int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
|
|
{
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
unsigned long irqflags;
|
|
int r;
|
|
|
|
if (crtc < 0 || crtc >= rdev->num_crtc) {
|
|
DRM_ERROR("Invalid crtc %d\n", crtc);
|
|
return -EINVAL;
|
|
}
|
|
|
|
spin_lock_irqsave(&rdev->irq.lock, irqflags);
|
|
rdev->irq.crtc_vblank_int[crtc] = true;
|
|
r = radeon_irq_set(rdev);
|
|
spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
|
|
return r;
|
|
}
|
|
|
|
/**
|
|
* radeon_disable_vblank_kms - disable vblank interrupt
|
|
*
|
|
* @dev: drm dev pointer
|
|
* @crtc: crtc to disable vblank interrupt for
|
|
*
|
|
* Disable the interrupt on the requested crtc (all asics).
|
|
*/
|
|
void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
|
|
{
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
unsigned long irqflags;
|
|
|
|
if (crtc < 0 || crtc >= rdev->num_crtc) {
|
|
DRM_ERROR("Invalid crtc %d\n", crtc);
|
|
return;
|
|
}
|
|
|
|
spin_lock_irqsave(&rdev->irq.lock, irqflags);
|
|
rdev->irq.crtc_vblank_int[crtc] = false;
|
|
radeon_irq_set(rdev);
|
|
spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
|
|
}
|
|
|
|
/**
|
|
* radeon_get_vblank_timestamp_kms - get vblank timestamp
|
|
*
|
|
* @dev: drm dev pointer
|
|
* @crtc: crtc to get the timestamp for
|
|
* @max_error: max error
|
|
* @vblank_time: time value
|
|
* @flags: flags passed to the driver
|
|
*
|
|
* Gets the timestamp on the requested crtc based on the
|
|
* scanout position. (all asics).
|
|
* Returns postive status flags on success, negative error on failure.
|
|
*/
|
|
int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
|
|
int *max_error,
|
|
struct timeval *vblank_time,
|
|
unsigned flags)
|
|
{
|
|
struct drm_crtc *drmcrtc;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
|
|
if (crtc < 0 || crtc >= dev->num_crtcs) {
|
|
DRM_ERROR("Invalid crtc %d\n", crtc);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Get associated drm_crtc: */
|
|
drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
|
|
|
|
/* Helper routine in DRM core does all the work: */
|
|
return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
|
|
vblank_time, flags,
|
|
drmcrtc, &drmcrtc->hwmode);
|
|
}
|
|
|
|
#define KMS_INVALID_IOCTL(name) \
|
|
static int name(struct drm_device *dev, void *data, struct drm_file \
|
|
*file_priv) \
|
|
{ \
|
|
DRM_ERROR("invalid ioctl with kms %s\n", __func__); \
|
|
return -EINVAL; \
|
|
}
|
|
|
|
/*
|
|
* All these ioctls are invalid in kms world.
|
|
*/
|
|
KMS_INVALID_IOCTL(radeon_cp_init_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_start_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_stop_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_reset_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_idle_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_resume_kms)
|
|
KMS_INVALID_IOCTL(radeon_engine_reset_kms)
|
|
KMS_INVALID_IOCTL(radeon_fullscreen_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_swap_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_clear_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_indices_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_texture_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_flip_kms)
|
|
KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
|
|
KMS_INVALID_IOCTL(radeon_mem_free_kms)
|
|
KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
|
|
KMS_INVALID_IOCTL(radeon_irq_emit_kms)
|
|
KMS_INVALID_IOCTL(radeon_irq_wait_kms)
|
|
KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
|
|
KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
|
|
KMS_INVALID_IOCTL(radeon_surface_free_kms)
|
|
|
|
|
|
const struct drm_ioctl_desc radeon_ioctls_kms[] = {
|
|
DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
|
|
/* KMS */
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
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DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
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|
DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
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|
DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
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|
DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
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|
};
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|
int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);
|