mirror of https://gitee.com/openkylin/linux.git
520 lines
14 KiB
C
520 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __KVM_X86_VMX_H
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#define __KVM_X86_VMX_H
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#include <linux/kvm_host.h>
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#include <asm/kvm.h>
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#include <asm/intel_pt.h>
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#include "capabilities.h"
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#include "kvm_cache_regs.h"
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#include "posted_intr.h"
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#include "vmcs.h"
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#include "vmx_ops.h"
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#include "cpuid.h"
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extern const u32 vmx_msr_index[];
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#define MSR_TYPE_R 1
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#define MSR_TYPE_W 2
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#define MSR_TYPE_RW 3
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#define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
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#ifdef CONFIG_X86_64
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#define MAX_NR_USER_RETURN_MSRS 7
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#else
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#define MAX_NR_USER_RETURN_MSRS 4
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#endif
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#define MAX_NR_LOADSTORE_MSRS 8
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struct vmx_msrs {
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unsigned int nr;
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struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS];
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};
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struct vmx_uret_msr {
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unsigned int slot; /* The MSR's slot in kvm_user_return_msrs. */
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u64 data;
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u64 mask;
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};
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enum segment_cache_field {
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SEG_FIELD_SEL = 0,
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SEG_FIELD_BASE = 1,
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SEG_FIELD_LIMIT = 2,
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SEG_FIELD_AR = 3,
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SEG_FIELD_NR = 4
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};
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#define RTIT_ADDR_RANGE 4
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struct pt_ctx {
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u64 ctl;
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u64 status;
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u64 output_base;
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u64 output_mask;
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u64 cr3_match;
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u64 addr_a[RTIT_ADDR_RANGE];
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u64 addr_b[RTIT_ADDR_RANGE];
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};
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struct pt_desc {
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u64 ctl_bitmask;
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u32 addr_range;
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u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
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struct pt_ctx host;
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struct pt_ctx guest;
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};
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union vmx_exit_reason {
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struct {
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u32 basic : 16;
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u32 reserved16 : 1;
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u32 reserved17 : 1;
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u32 reserved18 : 1;
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u32 reserved19 : 1;
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u32 reserved20 : 1;
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u32 reserved21 : 1;
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u32 reserved22 : 1;
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u32 reserved23 : 1;
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u32 reserved24 : 1;
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u32 reserved25 : 1;
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u32 bus_lock_detected : 1;
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u32 enclave_mode : 1;
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u32 smi_pending_mtf : 1;
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u32 smi_from_vmx_root : 1;
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u32 reserved30 : 1;
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u32 failed_vmentry : 1;
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};
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u32 full;
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};
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/*
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* The nested_vmx structure is part of vcpu_vmx, and holds information we need
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* for correct emulation of VMX (i.e., nested VMX) on this vcpu.
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*/
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struct nested_vmx {
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/* Has the level1 guest done vmxon? */
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bool vmxon;
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gpa_t vmxon_ptr;
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bool pml_full;
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/* The guest-physical address of the current VMCS L1 keeps for L2 */
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gpa_t current_vmptr;
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/*
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* Cache of the guest's VMCS, existing outside of guest memory.
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* Loaded from guest memory during VMPTRLD. Flushed to guest
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* memory during VMCLEAR and VMPTRLD.
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*/
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struct vmcs12 *cached_vmcs12;
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/*
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* Cache of the guest's shadow VMCS, existing outside of guest
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* memory. Loaded from guest memory during VM entry. Flushed
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* to guest memory during VM exit.
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*/
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struct vmcs12 *cached_shadow_vmcs12;
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/*
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* Indicates if the shadow vmcs or enlightened vmcs must be updated
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* with the data held by struct vmcs12.
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*/
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bool need_vmcs12_to_shadow_sync;
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bool dirty_vmcs12;
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/*
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* Indicates lazily loaded guest state has not yet been decached from
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* vmcs02.
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*/
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bool need_sync_vmcs02_to_vmcs12_rare;
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/*
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* vmcs02 has been initialized, i.e. state that is constant for
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* vmcs02 has been written to the backing VMCS. Initialization
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* is delayed until L1 actually attempts to run a nested VM.
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*/
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bool vmcs02_initialized;
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bool change_vmcs01_virtual_apic_mode;
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bool reload_vmcs01_apic_access_page;
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/*
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* Enlightened VMCS has been enabled. It does not mean that L1 has to
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* use it. However, VMX features available to L1 will be limited based
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* on what the enlightened VMCS supports.
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*/
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bool enlightened_vmcs_enabled;
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/* L2 must run next, and mustn't decide to exit to L1. */
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bool nested_run_pending;
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/* Pending MTF VM-exit into L1. */
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bool mtf_pending;
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struct loaded_vmcs vmcs02;
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/*
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* Guest pages referred to in the vmcs02 with host-physical
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* pointers, so we must keep them pinned while L2 runs.
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*/
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struct page *apic_access_page;
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struct kvm_host_map virtual_apic_map;
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struct kvm_host_map pi_desc_map;
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struct kvm_host_map msr_bitmap_map;
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struct pi_desc *pi_desc;
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bool pi_pending;
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u16 posted_intr_nv;
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struct hrtimer preemption_timer;
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u64 preemption_timer_deadline;
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bool has_preemption_timer_deadline;
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bool preemption_timer_expired;
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/* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
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u64 vmcs01_debugctl;
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u64 vmcs01_guest_bndcfgs;
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/* to migrate it to L1 if L2 writes to L1's CR8 directly */
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int l1_tpr_threshold;
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u16 vpid02;
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u16 last_vpid;
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struct nested_vmx_msrs msrs;
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/* SMM related state */
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struct {
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/* in VMX operation on SMM entry? */
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bool vmxon;
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/* in guest mode on SMM entry? */
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bool guest_mode;
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} smm;
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gpa_t hv_evmcs_vmptr;
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struct kvm_host_map hv_evmcs_map;
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struct hv_enlightened_vmcs *hv_evmcs;
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};
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struct vcpu_vmx {
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struct kvm_vcpu vcpu;
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u8 fail;
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u8 msr_bitmap_mode;
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/*
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* If true, host state has been stored in vmx->loaded_vmcs for
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* the CPU registers that only need to be switched when transitioning
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* to/from the kernel, and the registers have been loaded with guest
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* values. If false, host state is loaded in the CPU registers
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* and vmx->loaded_vmcs->host_state is invalid.
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*/
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bool guest_state_loaded;
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unsigned long exit_qualification;
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u32 exit_intr_info;
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u32 idt_vectoring_info;
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ulong rflags;
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struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
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int nr_uret_msrs;
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int nr_active_uret_msrs;
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bool guest_uret_msrs_loaded;
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#ifdef CONFIG_X86_64
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u64 msr_host_kernel_gs_base;
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u64 msr_guest_kernel_gs_base;
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#endif
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u64 spec_ctrl;
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u32 msr_ia32_umwait_control;
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u32 secondary_exec_control;
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/*
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* loaded_vmcs points to the VMCS currently used in this vcpu. For a
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* non-nested (L1) guest, it always points to vmcs01. For a nested
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* guest (L2), it points to a different VMCS.
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*/
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struct loaded_vmcs vmcs01;
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struct loaded_vmcs *loaded_vmcs;
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struct msr_autoload {
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struct vmx_msrs guest;
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struct vmx_msrs host;
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} msr_autoload;
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struct msr_autostore {
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struct vmx_msrs guest;
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} msr_autostore;
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struct {
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int vm86_active;
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ulong save_rflags;
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struct kvm_segment segs[8];
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} rmode;
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struct {
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u32 bitmask; /* 4 bits per segment (1 bit per field) */
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struct kvm_save_segment {
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u16 selector;
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unsigned long base;
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u32 limit;
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u32 ar;
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} seg[8];
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} segment_cache;
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int vpid;
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bool emulation_required;
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union vmx_exit_reason exit_reason;
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/* Posted interrupt descriptor */
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struct pi_desc pi_desc;
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/* Support for a guest hypervisor (nested VMX) */
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struct nested_vmx nested;
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/* Dynamic PLE window. */
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unsigned int ple_window;
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bool ple_window_dirty;
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bool req_immediate_exit;
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/* Support for PML */
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#define PML_ENTITY_NUM 512
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struct page *pml_pg;
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/* apic deadline value in host tsc */
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u64 hv_deadline_tsc;
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u64 current_tsc_ratio;
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unsigned long host_debugctlmsr;
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/*
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* Only bits masked by msr_ia32_feature_control_valid_bits can be set in
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* msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
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* in msr_ia32_feature_control_valid_bits.
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*/
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u64 msr_ia32_feature_control;
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u64 msr_ia32_feature_control_valid_bits;
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u64 ept_pointer;
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struct pt_desc pt_desc;
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/* Save desired MSR intercept (read: pass-through) state */
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#define MAX_POSSIBLE_PASSTHROUGH_MSRS 13
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struct {
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DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
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DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
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} shadow_msr_intercept;
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};
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enum ept_pointers_status {
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EPT_POINTERS_CHECK = 0,
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EPT_POINTERS_MATCH = 1,
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EPT_POINTERS_MISMATCH = 2
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};
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struct kvm_vmx {
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struct kvm kvm;
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unsigned int tss_addr;
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bool ept_identity_pagetable_done;
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gpa_t ept_identity_map_addr;
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enum ept_pointers_status ept_pointers_match;
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spinlock_t ept_pointer_lock;
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};
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bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
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void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
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struct loaded_vmcs *buddy);
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int allocate_vpid(void);
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void free_vpid(int vpid);
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void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
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void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
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void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
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unsigned long fs_base, unsigned long gs_base);
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int vmx_get_cpl(struct kvm_vcpu *vcpu);
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unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
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void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
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u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
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void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
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int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
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void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
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void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
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void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
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void ept_save_pdptrs(struct kvm_vcpu *vcpu);
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void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
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void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
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u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa,
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int root_level);
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void update_exception_bitmap(struct kvm_vcpu *vcpu);
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void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
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bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
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bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
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bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
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void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
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void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
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struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
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void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
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void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
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int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
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void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
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void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu,
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u32 msr, int type, bool value);
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static inline u8 vmx_get_rvi(void)
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{
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return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
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}
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#define BUILD_CONTROLS_SHADOW(lname, uname) \
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static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val) \
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{ \
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if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
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vmcs_write32(uname, val); \
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vmx->loaded_vmcs->controls_shadow.lname = val; \
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} \
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} \
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static inline u32 lname##_controls_get(struct vcpu_vmx *vmx) \
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{ \
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return vmx->loaded_vmcs->controls_shadow.lname; \
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} \
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static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val) \
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{ \
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lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
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} \
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static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
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{ \
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lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
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}
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BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
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BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
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BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
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BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
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BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
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static inline void vmx_register_cache_reset(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
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| (1 << VCPU_EXREG_RFLAGS)
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| (1 << VCPU_EXREG_PDPTR)
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| (1 << VCPU_EXREG_SEGMENTS)
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| (1 << VCPU_EXREG_CR0)
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| (1 << VCPU_EXREG_CR3)
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| (1 << VCPU_EXREG_CR4)
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| (1 << VCPU_EXREG_EXIT_INFO_1)
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| (1 << VCPU_EXREG_EXIT_INFO_2));
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vcpu->arch.regs_dirty = 0;
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}
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static inline u32 vmx_vmentry_ctrl(void)
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{
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u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
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if (vmx_pt_mode_is_system())
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vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
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VM_ENTRY_LOAD_IA32_RTIT_CTL);
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/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
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return vmentry_ctrl &
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~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
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}
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static inline u32 vmx_vmexit_ctrl(void)
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{
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u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
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if (vmx_pt_mode_is_system())
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vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
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VM_EXIT_CLEAR_IA32_RTIT_CTL);
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/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
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return vmexit_ctrl &
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~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
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}
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u32 vmx_exec_control(struct vcpu_vmx *vmx);
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u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx);
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static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
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{
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return container_of(kvm, struct kvm_vmx, kvm);
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}
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static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
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{
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return container_of(vcpu, struct vcpu_vmx, vcpu);
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}
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static inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) {
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kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
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vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
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}
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return vmx->exit_qualification;
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}
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static inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
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{
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struct vcpu_vmx *vmx = to_vmx(vcpu);
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if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) {
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kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
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vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
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}
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return vmx->exit_intr_info;
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}
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struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
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void free_vmcs(struct vmcs *vmcs);
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int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
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void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
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void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
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|
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static inline struct vmcs *alloc_vmcs(bool shadow)
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|
{
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|
return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
|
|
GFP_KERNEL_ACCOUNT);
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}
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|
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static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
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|
{
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vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
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|
vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
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}
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|
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static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
|
|
{
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|
return vmx->secondary_exec_control &
|
|
SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
|
|
}
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|
|
|
static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
|
|
{
|
|
if (!enable_ept)
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|
return true;
|
|
|
|
return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits;
|
|
}
|
|
|
|
static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
|
|
{
|
|
return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
|
|
(secondary_exec_controls_get(to_vmx(vcpu)) &
|
|
SECONDARY_EXEC_UNRESTRICTED_GUEST));
|
|
}
|
|
|
|
bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
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|
static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
|
|
{
|
|
return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
|
|
}
|
|
|
|
void dump_vmcs(void);
|
|
|
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#endif /* __KVM_X86_VMX_H */
|