Peter Zijlstra 32b62f4468 perf/x86/amd: Cleanup Fam10h NB event constraints ... Avoid allocating the AMD NB event constraints data structure when not needed. This gets rid of x86_max_cores usage and avoids allocating this on AMD Core Perfctr supporting hardware (which has separate MSRs for NB events). Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: aherrmann@suse.com Cc: Rui Huang <ray.huang@amd.com> Cc: Borislav Petkov <bp@alien8.de> Cc: jencce.kernel@gmail.com Link: http://lkml.kernel.org/r/20160320124629.GY6375@twins.programming.kicks-ass.net Signed-off-by: Thomas Gleixner <tglx@linutronix.de>		2016-03-29 10:45:04 +02:00
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core.c	perf/x86/amd: Cleanup Fam10h NB event constraints	2016-03-29 10:45:04 +02:00
ibs.c	perf/x86/ibs: Add IBS interrupt to the dynamic throttle	2016-03-21 09:08:16 +01:00
iommu.c	perf/x86/amd: Add support for new IOMMU performance events	2016-03-21 09:35:28 +01:00
iommu.h	…
power.c	perf/x86/amd/power: Add AMD accumulated power reporting mechanism	2016-03-21 09:37:15 +01:00
uncore.c	Merge branch 'perf/urgent' into perf/core, to queue up dependent patch	2016-02-17 10:37:36 +01:00