mirror of https://gitee.com/openkylin/linux.git
1045 lines
26 KiB
C
1045 lines
26 KiB
C
/*
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* Allwinner A1X SoCs pinctrl driver.
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*
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* Copyright (C) 2012 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/gpio/driver.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/export.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "../core.h"
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#include "pinctrl-sunxi.h"
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static struct irq_chip sunxi_pinctrl_edge_irq_chip;
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static struct irq_chip sunxi_pinctrl_level_irq_chip;
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static struct sunxi_pinctrl_group *
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sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
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{
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int i;
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for (i = 0; i < pctl->ngroups; i++) {
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struct sunxi_pinctrl_group *grp = pctl->groups + i;
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if (!strcmp(grp->name, group))
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return grp;
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}
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return NULL;
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}
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static struct sunxi_pinctrl_function *
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sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
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const char *name)
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{
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struct sunxi_pinctrl_function *func = pctl->functions;
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int i;
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for (i = 0; i < pctl->nfunctions; i++) {
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if (!func[i].name)
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break;
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if (!strcmp(func[i].name, name))
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return func + i;
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}
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return NULL;
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}
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static struct sunxi_desc_function *
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sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
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const char *pin_name,
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const char *func_name)
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{
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int i;
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for (i = 0; i < pctl->desc->npins; i++) {
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const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
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if (!strcmp(pin->pin.name, pin_name)) {
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struct sunxi_desc_function *func = pin->functions;
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while (func->name) {
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if (!strcmp(func->name, func_name))
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return func;
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func++;
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}
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}
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}
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return NULL;
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}
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static struct sunxi_desc_function *
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sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
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const u16 pin_num,
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const char *func_name)
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{
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int i;
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for (i = 0; i < pctl->desc->npins; i++) {
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const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
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if (pin->pin.number == pin_num) {
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struct sunxi_desc_function *func = pin->functions;
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while (func->name) {
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if (!strcmp(func->name, func_name))
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return func;
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func++;
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}
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}
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}
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return NULL;
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}
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static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->ngroups;
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}
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static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
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unsigned group)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->groups[group].name;
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}
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static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned group,
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const unsigned **pins,
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unsigned *num_pins)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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*pins = (unsigned *)&pctl->groups[group].pin;
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*num_pins = 1;
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return 0;
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}
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static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
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struct device_node *node,
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struct pinctrl_map **map,
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unsigned *num_maps)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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unsigned long *pinconfig;
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struct property *prop;
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const char *function;
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const char *group;
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int ret, nmaps, i = 0;
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u32 val;
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*map = NULL;
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*num_maps = 0;
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ret = of_property_read_string(node, "allwinner,function", &function);
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if (ret) {
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dev_err(pctl->dev,
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"missing allwinner,function property in node %s\n",
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node->name);
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return -EINVAL;
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}
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nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
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if (nmaps < 0) {
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dev_err(pctl->dev,
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"missing allwinner,pins property in node %s\n",
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node->name);
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return -EINVAL;
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}
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*map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
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if (!*map)
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return -ENOMEM;
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of_property_for_each_string(node, "allwinner,pins", prop, group) {
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struct sunxi_pinctrl_group *grp =
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sunxi_pinctrl_find_group_by_name(pctl, group);
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int j = 0, configlen = 0;
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if (!grp) {
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dev_err(pctl->dev, "unknown pin %s", group);
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continue;
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}
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if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
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grp->name,
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function)) {
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dev_err(pctl->dev, "unsupported function %s on pin %s",
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function, group);
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continue;
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}
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(*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
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(*map)[i].data.mux.group = group;
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(*map)[i].data.mux.function = function;
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i++;
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(*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
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(*map)[i].data.configs.group_or_pin = group;
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if (of_find_property(node, "allwinner,drive", NULL))
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configlen++;
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if (of_find_property(node, "allwinner,pull", NULL))
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configlen++;
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pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
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if (!pinconfig) {
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kfree(*map);
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return -ENOMEM;
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}
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if (!of_property_read_u32(node, "allwinner,drive", &val)) {
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u16 strength = (val + 1) * 10;
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pinconfig[j++] =
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pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
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strength);
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}
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if (!of_property_read_u32(node, "allwinner,pull", &val)) {
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enum pin_config_param pull = PIN_CONFIG_END;
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if (val == 1)
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pull = PIN_CONFIG_BIAS_PULL_UP;
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else if (val == 2)
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pull = PIN_CONFIG_BIAS_PULL_DOWN;
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pinconfig[j++] = pinconf_to_config_packed(pull, 0);
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}
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(*map)[i].data.configs.configs = pinconfig;
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(*map)[i].data.configs.num_configs = configlen;
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i++;
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}
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*num_maps = nmaps;
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return 0;
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}
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static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
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struct pinctrl_map *map,
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unsigned num_maps)
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{
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int i;
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for (i = 0; i < num_maps; i++) {
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if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
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kfree(map[i].data.configs.configs);
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}
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kfree(map);
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}
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static const struct pinctrl_ops sunxi_pctrl_ops = {
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.dt_node_to_map = sunxi_pctrl_dt_node_to_map,
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.dt_free_map = sunxi_pctrl_dt_free_map,
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.get_groups_count = sunxi_pctrl_get_groups_count,
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.get_group_name = sunxi_pctrl_get_group_name,
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.get_group_pins = sunxi_pctrl_get_group_pins,
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};
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static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
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unsigned group,
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unsigned long *config)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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*config = pctl->groups[group].config;
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return 0;
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}
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static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
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unsigned group,
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unsigned long *configs,
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unsigned num_configs)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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struct sunxi_pinctrl_group *g = &pctl->groups[group];
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unsigned long flags;
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unsigned pin = g->pin - pctl->desc->pin_base;
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u32 val, mask;
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u16 strength;
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u8 dlevel;
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int i;
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spin_lock_irqsave(&pctl->lock, flags);
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for (i = 0; i < num_configs; i++) {
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switch (pinconf_to_config_param(configs[i])) {
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case PIN_CONFIG_DRIVE_STRENGTH:
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strength = pinconf_to_config_argument(configs[i]);
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if (strength > 40) {
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spin_unlock_irqrestore(&pctl->lock, flags);
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return -EINVAL;
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}
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/*
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* We convert from mA to what the register expects:
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* 0: 10mA
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* 1: 20mA
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* 2: 30mA
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* 3: 40mA
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*/
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dlevel = strength / 10 - 1;
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val = readl(pctl->membase + sunxi_dlevel_reg(pin));
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mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(pin);
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writel((val & ~mask)
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| dlevel << sunxi_dlevel_offset(pin),
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pctl->membase + sunxi_dlevel_reg(pin));
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break;
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case PIN_CONFIG_BIAS_PULL_UP:
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val = readl(pctl->membase + sunxi_pull_reg(pin));
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mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
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writel((val & ~mask) | 1 << sunxi_pull_offset(pin),
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pctl->membase + sunxi_pull_reg(pin));
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break;
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case PIN_CONFIG_BIAS_PULL_DOWN:
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val = readl(pctl->membase + sunxi_pull_reg(pin));
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mask = PULL_PINS_MASK << sunxi_pull_offset(pin);
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writel((val & ~mask) | 2 << sunxi_pull_offset(pin),
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pctl->membase + sunxi_pull_reg(pin));
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break;
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default:
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break;
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}
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/* cache the config value */
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g->config = configs[i];
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} /* for each config */
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spin_unlock_irqrestore(&pctl->lock, flags);
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return 0;
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}
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static const struct pinconf_ops sunxi_pconf_ops = {
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.pin_config_group_get = sunxi_pconf_group_get,
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.pin_config_group_set = sunxi_pconf_group_set,
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};
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static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->nfunctions;
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}
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static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
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unsigned function)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->functions[function].name;
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}
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static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
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unsigned function,
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const char * const **groups,
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unsigned * const num_groups)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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*groups = pctl->functions[function].groups;
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*num_groups = pctl->functions[function].ngroups;
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return 0;
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}
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static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
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unsigned pin,
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u8 config)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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unsigned long flags;
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u32 val, mask;
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spin_lock_irqsave(&pctl->lock, flags);
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pin -= pctl->desc->pin_base;
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val = readl(pctl->membase + sunxi_mux_reg(pin));
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mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
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writel((val & ~mask) | config << sunxi_mux_offset(pin),
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pctl->membase + sunxi_mux_reg(pin));
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spin_unlock_irqrestore(&pctl->lock, flags);
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}
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static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
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unsigned function,
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unsigned group)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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struct sunxi_pinctrl_group *g = pctl->groups + group;
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struct sunxi_pinctrl_function *func = pctl->functions + function;
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struct sunxi_desc_function *desc =
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sunxi_pinctrl_desc_find_function_by_name(pctl,
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g->name,
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func->name);
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if (!desc)
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return -EINVAL;
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sunxi_pmx_set(pctldev, g->pin, desc->muxval);
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return 0;
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}
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static int
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sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset,
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bool input)
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{
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struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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struct sunxi_desc_function *desc;
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const char *func;
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if (input)
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func = "gpio_in";
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else
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func = "gpio_out";
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desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
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if (!desc)
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return -EINVAL;
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sunxi_pmx_set(pctldev, offset, desc->muxval);
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return 0;
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}
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static const struct pinmux_ops sunxi_pmx_ops = {
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.get_functions_count = sunxi_pmx_get_funcs_cnt,
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.get_function_name = sunxi_pmx_get_func_name,
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.get_function_groups = sunxi_pmx_get_func_groups,
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.set_mux = sunxi_pmx_set_mux,
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.gpio_set_direction = sunxi_pmx_gpio_set_direction,
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};
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static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
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unsigned offset)
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{
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return pinctrl_gpio_direction_input(chip->base + offset);
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}
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static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
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u32 reg = sunxi_data_reg(offset);
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u8 index = sunxi_data_offset(offset);
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bool set_mux = pctl->desc->irq_read_needs_mux &&
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gpiochip_line_is_irq(chip, offset);
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u32 pin = offset + chip->base;
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u32 val;
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if (set_mux)
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sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
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val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
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if (set_mux)
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sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
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return !!val;
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}
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static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
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u32 reg = sunxi_data_reg(offset);
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u8 index = sunxi_data_offset(offset);
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unsigned long flags;
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u32 regval;
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spin_lock_irqsave(&pctl->lock, flags);
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regval = readl(pctl->membase + reg);
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if (value)
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regval |= BIT(index);
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else
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regval &= ~(BIT(index));
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writel(regval, pctl->membase + reg);
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spin_unlock_irqrestore(&pctl->lock, flags);
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}
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static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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sunxi_pinctrl_gpio_set(chip, offset, value);
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return pinctrl_gpio_direction_output(chip->base + offset);
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}
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static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
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const struct of_phandle_args *gpiospec,
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u32 *flags)
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{
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int pin, base;
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base = PINS_PER_BANK * gpiospec->args[0];
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|
pin = base + gpiospec->args[1];
|
|
|
|
if (pin > gc->ngpio)
|
|
return -EINVAL;
|
|
|
|
if (flags)
|
|
*flags = gpiospec->args[2];
|
|
|
|
return pin;
|
|
}
|
|
|
|
static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
|
{
|
|
struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
|
|
struct sunxi_desc_function *desc;
|
|
unsigned pinnum = pctl->desc->pin_base + offset;
|
|
unsigned irqnum;
|
|
|
|
if (offset >= chip->ngpio)
|
|
return -ENXIO;
|
|
|
|
desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
|
|
if (!desc)
|
|
return -EINVAL;
|
|
|
|
irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
|
|
|
|
dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
|
|
chip->label, offset + chip->base, irqnum);
|
|
|
|
return irq_find_mapping(pctl->domain, irqnum);
|
|
}
|
|
|
|
static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
struct sunxi_desc_function *func;
|
|
int ret;
|
|
|
|
func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
|
|
pctl->irq_array[d->hwirq], "irq");
|
|
if (!func)
|
|
return -EINVAL;
|
|
|
|
ret = gpiochip_lock_as_irq(pctl->chip,
|
|
pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
|
|
if (ret) {
|
|
dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
|
|
irqd_to_hwirq(d));
|
|
return ret;
|
|
}
|
|
|
|
/* Change muxing to INT mode */
|
|
sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
|
|
gpiochip_unlock_as_irq(pctl->chip,
|
|
pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
|
|
}
|
|
|
|
static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
u32 reg = sunxi_irq_cfg_reg(d->hwirq, pctl->desc->irq_bank_base);
|
|
u8 index = sunxi_irq_cfg_offset(d->hwirq);
|
|
unsigned long flags;
|
|
u32 regval;
|
|
u8 mode;
|
|
|
|
switch (type) {
|
|
case IRQ_TYPE_EDGE_RISING:
|
|
mode = IRQ_EDGE_RISING;
|
|
break;
|
|
case IRQ_TYPE_EDGE_FALLING:
|
|
mode = IRQ_EDGE_FALLING;
|
|
break;
|
|
case IRQ_TYPE_EDGE_BOTH:
|
|
mode = IRQ_EDGE_BOTH;
|
|
break;
|
|
case IRQ_TYPE_LEVEL_HIGH:
|
|
mode = IRQ_LEVEL_HIGH;
|
|
break;
|
|
case IRQ_TYPE_LEVEL_LOW:
|
|
mode = IRQ_LEVEL_LOW;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
spin_lock_irqsave(&pctl->lock, flags);
|
|
|
|
if (type & IRQ_TYPE_LEVEL_MASK)
|
|
irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
|
|
handle_fasteoi_irq, NULL);
|
|
else
|
|
irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
|
|
handle_edge_irq, NULL);
|
|
|
|
regval = readl(pctl->membase + reg);
|
|
regval &= ~(IRQ_CFG_IRQ_MASK << index);
|
|
writel(regval | (mode << index), pctl->membase + reg);
|
|
|
|
spin_unlock_irqrestore(&pctl->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sunxi_pinctrl_irq_ack(struct irq_data *d)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
u32 status_reg = sunxi_irq_status_reg(d->hwirq,
|
|
pctl->desc->irq_bank_base);
|
|
u8 status_idx = sunxi_irq_status_offset(d->hwirq);
|
|
|
|
/* Clear the IRQ */
|
|
writel(1 << status_idx, pctl->membase + status_reg);
|
|
}
|
|
|
|
static void sunxi_pinctrl_irq_mask(struct irq_data *d)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
|
|
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
spin_lock_irqsave(&pctl->lock, flags);
|
|
|
|
/* Mask the IRQ */
|
|
val = readl(pctl->membase + reg);
|
|
writel(val & ~(1 << idx), pctl->membase + reg);
|
|
|
|
spin_unlock_irqrestore(&pctl->lock, flags);
|
|
}
|
|
|
|
static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
|
|
{
|
|
struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
|
|
u32 reg = sunxi_irq_ctrl_reg(d->hwirq, pctl->desc->irq_bank_base);
|
|
u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
spin_lock_irqsave(&pctl->lock, flags);
|
|
|
|
/* Unmask the IRQ */
|
|
val = readl(pctl->membase + reg);
|
|
writel(val | (1 << idx), pctl->membase + reg);
|
|
|
|
spin_unlock_irqrestore(&pctl->lock, flags);
|
|
}
|
|
|
|
static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
|
|
{
|
|
sunxi_pinctrl_irq_ack(d);
|
|
sunxi_pinctrl_irq_unmask(d);
|
|
}
|
|
|
|
static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
|
|
.name = "sunxi_pio_edge",
|
|
.irq_ack = sunxi_pinctrl_irq_ack,
|
|
.irq_mask = sunxi_pinctrl_irq_mask,
|
|
.irq_unmask = sunxi_pinctrl_irq_unmask,
|
|
.irq_request_resources = sunxi_pinctrl_irq_request_resources,
|
|
.irq_release_resources = sunxi_pinctrl_irq_release_resources,
|
|
.irq_set_type = sunxi_pinctrl_irq_set_type,
|
|
.flags = IRQCHIP_SKIP_SET_WAKE,
|
|
};
|
|
|
|
static struct irq_chip sunxi_pinctrl_level_irq_chip = {
|
|
.name = "sunxi_pio_level",
|
|
.irq_eoi = sunxi_pinctrl_irq_ack,
|
|
.irq_mask = sunxi_pinctrl_irq_mask,
|
|
.irq_unmask = sunxi_pinctrl_irq_unmask,
|
|
/* Define irq_enable / disable to avoid spurious irqs for drivers
|
|
* using these to suppress irqs while they clear the irq source */
|
|
.irq_enable = sunxi_pinctrl_irq_ack_unmask,
|
|
.irq_disable = sunxi_pinctrl_irq_mask,
|
|
.irq_request_resources = sunxi_pinctrl_irq_request_resources,
|
|
.irq_release_resources = sunxi_pinctrl_irq_release_resources,
|
|
.irq_set_type = sunxi_pinctrl_irq_set_type,
|
|
.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_EOI_THREADED |
|
|
IRQCHIP_EOI_IF_HANDLED,
|
|
};
|
|
|
|
static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
|
|
struct device_node *node,
|
|
const u32 *intspec,
|
|
unsigned int intsize,
|
|
unsigned long *out_hwirq,
|
|
unsigned int *out_type)
|
|
{
|
|
struct sunxi_pinctrl *pctl = d->host_data;
|
|
struct sunxi_desc_function *desc;
|
|
int pin, base;
|
|
|
|
if (intsize < 3)
|
|
return -EINVAL;
|
|
|
|
base = PINS_PER_BANK * intspec[0];
|
|
pin = pctl->desc->pin_base + base + intspec[1];
|
|
|
|
desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
|
|
if (!desc)
|
|
return -EINVAL;
|
|
|
|
*out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
|
|
*out_type = intspec[2];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
|
|
.xlate = sunxi_pinctrl_irq_of_xlate,
|
|
};
|
|
|
|
static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
|
|
{
|
|
unsigned int irq = irq_desc_get_irq(desc);
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
|
|
unsigned long bank, reg, val;
|
|
|
|
for (bank = 0; bank < pctl->desc->irq_banks; bank++)
|
|
if (irq == pctl->irq[bank])
|
|
break;
|
|
|
|
if (bank == pctl->desc->irq_banks)
|
|
return;
|
|
|
|
reg = sunxi_irq_status_reg_from_bank(bank, pctl->desc->irq_bank_base);
|
|
val = readl(pctl->membase + reg);
|
|
|
|
if (val) {
|
|
int irqoffset;
|
|
|
|
chained_irq_enter(chip, desc);
|
|
for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) {
|
|
int pin_irq = irq_find_mapping(pctl->domain,
|
|
bank * IRQ_PER_BANK + irqoffset);
|
|
generic_handle_irq(pin_irq);
|
|
}
|
|
chained_irq_exit(chip, desc);
|
|
}
|
|
}
|
|
|
|
static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
|
|
const char *name)
|
|
{
|
|
struct sunxi_pinctrl_function *func = pctl->functions;
|
|
|
|
while (func->name) {
|
|
/* function already there */
|
|
if (strcmp(func->name, name) == 0) {
|
|
func->ngroups++;
|
|
return -EEXIST;
|
|
}
|
|
func++;
|
|
}
|
|
|
|
func->name = name;
|
|
func->ngroups = 1;
|
|
|
|
pctl->nfunctions++;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_pinctrl_build_state(struct platform_device *pdev)
|
|
{
|
|
struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
|
|
int i;
|
|
|
|
pctl->ngroups = pctl->desc->npins;
|
|
|
|
/* Allocate groups */
|
|
pctl->groups = devm_kzalloc(&pdev->dev,
|
|
pctl->ngroups * sizeof(*pctl->groups),
|
|
GFP_KERNEL);
|
|
if (!pctl->groups)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
struct sunxi_pinctrl_group *group = pctl->groups + i;
|
|
|
|
group->name = pin->pin.name;
|
|
group->pin = pin->pin.number;
|
|
}
|
|
|
|
/*
|
|
* We suppose that we won't have any more functions than pins,
|
|
* we'll reallocate that later anyway
|
|
*/
|
|
pctl->functions = devm_kzalloc(&pdev->dev,
|
|
pctl->desc->npins * sizeof(*pctl->functions),
|
|
GFP_KERNEL);
|
|
if (!pctl->functions)
|
|
return -ENOMEM;
|
|
|
|
/* Count functions and their associated groups */
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
struct sunxi_desc_function *func = pin->functions;
|
|
|
|
while (func->name) {
|
|
/* Create interrupt mapping while we're at it */
|
|
if (!strcmp(func->name, "irq")) {
|
|
int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
|
|
pctl->irq_array[irqnum] = pin->pin.number;
|
|
}
|
|
|
|
sunxi_pinctrl_add_function(pctl, func->name);
|
|
func++;
|
|
}
|
|
}
|
|
|
|
pctl->functions = krealloc(pctl->functions,
|
|
pctl->nfunctions * sizeof(*pctl->functions),
|
|
GFP_KERNEL);
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
struct sunxi_desc_function *func = pin->functions;
|
|
|
|
while (func->name) {
|
|
struct sunxi_pinctrl_function *func_item;
|
|
const char **func_grp;
|
|
|
|
func_item = sunxi_pinctrl_find_function_by_name(pctl,
|
|
func->name);
|
|
if (!func_item)
|
|
return -EINVAL;
|
|
|
|
if (!func_item->groups) {
|
|
func_item->groups =
|
|
devm_kzalloc(&pdev->dev,
|
|
func_item->ngroups * sizeof(*func_item->groups),
|
|
GFP_KERNEL);
|
|
if (!func_item->groups)
|
|
return -ENOMEM;
|
|
}
|
|
|
|
func_grp = func_item->groups;
|
|
while (*func_grp)
|
|
func_grp++;
|
|
|
|
*func_grp = pin->pin.name;
|
|
func++;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int sunxi_pinctrl_init(struct platform_device *pdev,
|
|
const struct sunxi_pinctrl_desc *desc)
|
|
{
|
|
struct device_node *node = pdev->dev.of_node;
|
|
struct pinctrl_desc *pctrl_desc;
|
|
struct pinctrl_pin_desc *pins;
|
|
struct sunxi_pinctrl *pctl;
|
|
struct resource *res;
|
|
int i, ret, last_pin;
|
|
struct clk *clk;
|
|
|
|
pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
|
|
if (!pctl)
|
|
return -ENOMEM;
|
|
platform_set_drvdata(pdev, pctl);
|
|
|
|
spin_lock_init(&pctl->lock);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
pctl->membase = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(pctl->membase))
|
|
return PTR_ERR(pctl->membase);
|
|
|
|
pctl->dev = &pdev->dev;
|
|
pctl->desc = desc;
|
|
|
|
pctl->irq_array = devm_kcalloc(&pdev->dev,
|
|
IRQ_PER_BANK * pctl->desc->irq_banks,
|
|
sizeof(*pctl->irq_array),
|
|
GFP_KERNEL);
|
|
if (!pctl->irq_array)
|
|
return -ENOMEM;
|
|
|
|
ret = sunxi_pinctrl_build_state(pdev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
pins = devm_kzalloc(&pdev->dev,
|
|
pctl->desc->npins * sizeof(*pins),
|
|
GFP_KERNEL);
|
|
if (!pins)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++)
|
|
pins[i] = pctl->desc->pins[i].pin;
|
|
|
|
pctrl_desc = devm_kzalloc(&pdev->dev,
|
|
sizeof(*pctrl_desc),
|
|
GFP_KERNEL);
|
|
if (!pctrl_desc)
|
|
return -ENOMEM;
|
|
|
|
pctrl_desc->name = dev_name(&pdev->dev);
|
|
pctrl_desc->owner = THIS_MODULE;
|
|
pctrl_desc->pins = pins;
|
|
pctrl_desc->npins = pctl->desc->npins;
|
|
pctrl_desc->confops = &sunxi_pconf_ops;
|
|
pctrl_desc->pctlops = &sunxi_pctrl_ops;
|
|
pctrl_desc->pmxops = &sunxi_pmx_ops;
|
|
|
|
pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
|
|
if (IS_ERR(pctl->pctl_dev)) {
|
|
dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
|
|
return PTR_ERR(pctl->pctl_dev);
|
|
}
|
|
|
|
pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
|
|
if (!pctl->chip)
|
|
return -ENOMEM;
|
|
|
|
last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
|
|
pctl->chip->owner = THIS_MODULE;
|
|
pctl->chip->request = gpiochip_generic_request,
|
|
pctl->chip->free = gpiochip_generic_free,
|
|
pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input,
|
|
pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output,
|
|
pctl->chip->get = sunxi_pinctrl_gpio_get,
|
|
pctl->chip->set = sunxi_pinctrl_gpio_set,
|
|
pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate,
|
|
pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq,
|
|
pctl->chip->of_gpio_n_cells = 3,
|
|
pctl->chip->can_sleep = false,
|
|
pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
|
|
pctl->desc->pin_base;
|
|
pctl->chip->label = dev_name(&pdev->dev);
|
|
pctl->chip->parent = &pdev->dev;
|
|
pctl->chip->base = pctl->desc->pin_base;
|
|
|
|
ret = gpiochip_add_data(pctl->chip, pctl);
|
|
if (ret)
|
|
return ret;
|
|
|
|
for (i = 0; i < pctl->desc->npins; i++) {
|
|
const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
|
|
|
|
ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
|
|
pin->pin.number - pctl->desc->pin_base,
|
|
pin->pin.number, 1);
|
|
if (ret)
|
|
goto gpiochip_error;
|
|
}
|
|
|
|
clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(clk)) {
|
|
ret = PTR_ERR(clk);
|
|
goto gpiochip_error;
|
|
}
|
|
|
|
ret = clk_prepare_enable(clk);
|
|
if (ret)
|
|
goto gpiochip_error;
|
|
|
|
pctl->irq = devm_kcalloc(&pdev->dev,
|
|
pctl->desc->irq_banks,
|
|
sizeof(*pctl->irq),
|
|
GFP_KERNEL);
|
|
if (!pctl->irq) {
|
|
ret = -ENOMEM;
|
|
goto clk_error;
|
|
}
|
|
|
|
for (i = 0; i < pctl->desc->irq_banks; i++) {
|
|
pctl->irq[i] = platform_get_irq(pdev, i);
|
|
if (pctl->irq[i] < 0) {
|
|
ret = pctl->irq[i];
|
|
goto clk_error;
|
|
}
|
|
}
|
|
|
|
pctl->domain = irq_domain_add_linear(node,
|
|
pctl->desc->irq_banks * IRQ_PER_BANK,
|
|
&sunxi_pinctrl_irq_domain_ops,
|
|
pctl);
|
|
if (!pctl->domain) {
|
|
dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
|
|
ret = -ENOMEM;
|
|
goto clk_error;
|
|
}
|
|
|
|
for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
|
|
int irqno = irq_create_mapping(pctl->domain, i);
|
|
|
|
irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
|
|
handle_edge_irq);
|
|
irq_set_chip_data(irqno, pctl);
|
|
}
|
|
|
|
for (i = 0; i < pctl->desc->irq_banks; i++) {
|
|
/* Mask and clear all IRQs before registering a handler */
|
|
writel(0, pctl->membase + sunxi_irq_ctrl_reg_from_bank(i,
|
|
pctl->desc->irq_bank_base));
|
|
writel(0xffffffff,
|
|
pctl->membase + sunxi_irq_status_reg_from_bank(i,
|
|
pctl->desc->irq_bank_base));
|
|
|
|
irq_set_chained_handler_and_data(pctl->irq[i],
|
|
sunxi_pinctrl_irq_handler,
|
|
pctl);
|
|
}
|
|
|
|
dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
|
|
|
|
return 0;
|
|
|
|
clk_error:
|
|
clk_disable_unprepare(clk);
|
|
gpiochip_error:
|
|
gpiochip_remove(pctl->chip);
|
|
return ret;
|
|
}
|