mirror of https://gitee.com/openkylin/linux.git
725 lines
20 KiB
C
725 lines
20 KiB
C
/*
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* Marvell Armada 37xx SoC Peripheral clocks
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*
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* Copyright (C) 2016 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2 or later. This program is licensed "as is"
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* without any warranty of any kind, whether express or implied.
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*
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* Most of the peripheral clocks can be modelled like this:
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* _____ _______ _______
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* TBG-A-P --| | | | | | ______
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* TBG-B-P --| Mux |--| /div1 |--| /div2 |--| Gate |--> perip_clk
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* TBG-A-S --| | | | | | |______|
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* TBG-B-S --|_____| |_______| |_______|
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*
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* However some clocks may use only one or two block or and use the
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* xtal clock as parent.
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*/
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#define TBG_SEL 0x0
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#define DIV_SEL0 0x4
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#define DIV_SEL1 0x8
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#define DIV_SEL2 0xC
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#define CLK_SEL 0x10
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#define CLK_DIS 0x14
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#define LOAD_LEVEL_NR 4
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#define ARMADA_37XX_NB_L0L1 0x18
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#define ARMADA_37XX_NB_L2L3 0x1C
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#define ARMADA_37XX_NB_TBG_DIV_OFF 13
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#define ARMADA_37XX_NB_TBG_DIV_MASK 0x7
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#define ARMADA_37XX_NB_CLK_SEL_OFF 11
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#define ARMADA_37XX_NB_CLK_SEL_MASK 0x1
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#define ARMADA_37XX_NB_TBG_SEL_OFF 9
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#define ARMADA_37XX_NB_TBG_SEL_MASK 0x3
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#define ARMADA_37XX_NB_CONFIG_SHIFT 16
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#define ARMADA_37XX_NB_DYN_MOD 0x24
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#define ARMADA_37XX_NB_DFS_EN 31
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#define ARMADA_37XX_NB_CPU_LOAD 0x30
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#define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3
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#define ARMADA_37XX_DVFS_LOAD_0 0
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#define ARMADA_37XX_DVFS_LOAD_1 1
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#define ARMADA_37XX_DVFS_LOAD_2 2
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#define ARMADA_37XX_DVFS_LOAD_3 3
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struct clk_periph_driver_data {
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struct clk_hw_onecell_data *hw_data;
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spinlock_t lock;
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};
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struct clk_double_div {
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struct clk_hw hw;
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void __iomem *reg1;
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u8 shift1;
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void __iomem *reg2;
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u8 shift2;
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};
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struct clk_pm_cpu {
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struct clk_hw hw;
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void __iomem *reg_mux;
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u8 shift_mux;
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u32 mask_mux;
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void __iomem *reg_div;
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u8 shift_div;
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struct regmap *nb_pm_base;
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};
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#define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw)
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#define to_clk_pm_cpu(_hw) container_of(_hw, struct clk_pm_cpu, hw)
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struct clk_periph_data {
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const char *name;
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const char * const *parent_names;
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int num_parents;
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struct clk_hw *mux_hw;
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struct clk_hw *rate_hw;
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struct clk_hw *gate_hw;
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struct clk_hw *muxrate_hw;
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bool is_double_div;
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};
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static const struct clk_div_table clk_table6[] = {
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{ .val = 1, .div = 1, },
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{ .val = 2, .div = 2, },
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{ .val = 3, .div = 3, },
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{ .val = 4, .div = 4, },
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{ .val = 5, .div = 5, },
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{ .val = 6, .div = 6, },
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{ .val = 0, .div = 0, }, /* last entry */
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};
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static const struct clk_div_table clk_table1[] = {
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{ .val = 0, .div = 1, },
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{ .val = 1, .div = 2, },
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{ .val = 0, .div = 0, }, /* last entry */
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};
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static const struct clk_div_table clk_table2[] = {
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{ .val = 0, .div = 2, },
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{ .val = 1, .div = 4, },
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{ .val = 0, .div = 0, }, /* last entry */
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};
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static const struct clk_ops clk_double_div_ops;
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static const struct clk_ops clk_pm_cpu_ops;
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#define PERIPH_GATE(_name, _bit) \
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struct clk_gate gate_##_name = { \
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.reg = (void *)CLK_DIS, \
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.bit_idx = _bit, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_gate_ops, \
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} \
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};
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#define PERIPH_MUX(_name, _shift) \
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struct clk_mux mux_##_name = { \
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.reg = (void *)TBG_SEL, \
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.shift = _shift, \
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.mask = 3, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_mux_ro_ops, \
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} \
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};
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#define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \
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struct clk_double_div rate_##_name = { \
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.reg1 = (void *)_reg1, \
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.reg2 = (void *)_reg2, \
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.shift1 = _shift1, \
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.shift2 = _shift2, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_double_div_ops, \
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} \
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};
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#define PERIPH_DIV(_name, _reg, _shift, _table) \
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struct clk_divider rate_##_name = { \
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.reg = (void *)_reg, \
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.table = _table, \
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.shift = _shift, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_divider_ro_ops, \
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} \
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};
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#define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \
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struct clk_pm_cpu muxrate_##_name = { \
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.reg_mux = (void *)TBG_SEL, \
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.mask_mux = 3, \
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.shift_mux = _shift1, \
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.reg_div = (void *)_reg, \
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.shift_div = _shift2, \
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.hw.init = &(struct clk_init_data){ \
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.ops = &clk_pm_cpu_ops, \
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} \
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};
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#define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\
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static PERIPH_GATE(_name, _bit); \
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static PERIPH_MUX(_name, _shift); \
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static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
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#define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \
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static PERIPH_GATE(_name, _bit); \
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static PERIPH_MUX(_name, _shift); \
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static PERIPH_DIV(_name, _reg, _shift1, _table);
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#define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \
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static PERIPH_GATE(_name, _bit); \
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static PERIPH_DIV(_name, _reg, _shift, _table);
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#define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\
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static PERIPH_MUX(_name, _shift); \
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static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
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#define REF_CLK_FULL(_name) \
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{ .name = #_name, \
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.parent_names = (const char *[]){ "TBG-A-P", \
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"TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
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.num_parents = 4, \
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.mux_hw = &mux_##_name.hw, \
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.gate_hw = &gate_##_name.hw, \
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.rate_hw = &rate_##_name.hw, \
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}
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#define REF_CLK_FULL_DD(_name) \
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{ .name = #_name, \
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.parent_names = (const char *[]){ "TBG-A-P", \
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"TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
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.num_parents = 4, \
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.mux_hw = &mux_##_name.hw, \
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.gate_hw = &gate_##_name.hw, \
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.rate_hw = &rate_##_name.hw, \
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.is_double_div = true, \
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}
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#define REF_CLK_GATE(_name, _parent_name) \
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{ .name = #_name, \
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.parent_names = (const char *[]){ _parent_name}, \
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.num_parents = 1, \
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.gate_hw = &gate_##_name.hw, \
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}
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#define REF_CLK_GATE_DIV(_name, _parent_name) \
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{ .name = #_name, \
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.parent_names = (const char *[]){ _parent_name}, \
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.num_parents = 1, \
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.gate_hw = &gate_##_name.hw, \
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.rate_hw = &rate_##_name.hw, \
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}
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#define REF_CLK_PM_CPU(_name) \
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{ .name = #_name, \
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.parent_names = (const char *[]){ "TBG-A-P", \
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"TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
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.num_parents = 4, \
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.muxrate_hw = &muxrate_##_name.hw, \
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}
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#define REF_CLK_MUX_DD(_name) \
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{ .name = #_name, \
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.parent_names = (const char *[]){ "TBG-A-P", \
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"TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
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.num_parents = 4, \
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.mux_hw = &mux_##_name.hw, \
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.rate_hw = &rate_##_name.hw, \
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.is_double_div = true, \
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}
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/* NB periph clocks */
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PERIPH_CLK_FULL_DD(mmc, 2, 0, DIV_SEL2, DIV_SEL2, 16, 13);
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PERIPH_CLK_FULL_DD(sata_host, 3, 2, DIV_SEL2, DIV_SEL2, 10, 7);
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PERIPH_CLK_FULL_DD(sec_at, 6, 4, DIV_SEL1, DIV_SEL1, 3, 0);
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PERIPH_CLK_FULL_DD(sec_dap, 7, 6, DIV_SEL1, DIV_SEL1, 9, 6);
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PERIPH_CLK_FULL_DD(tscem, 8, 8, DIV_SEL1, DIV_SEL1, 15, 12);
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PERIPH_CLK_FULL(tscem_tmx, 10, 10, DIV_SEL1, 18, clk_table6);
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static PERIPH_GATE(avs, 11);
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PERIPH_CLK_FULL_DD(pwm, 13, 14, DIV_SEL0, DIV_SEL0, 3, 0);
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PERIPH_CLK_FULL_DD(sqf, 12, 12, DIV_SEL1, DIV_SEL1, 27, 24);
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static PERIPH_GATE(i2c_2, 16);
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static PERIPH_GATE(i2c_1, 17);
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PERIPH_CLK_GATE_DIV(ddr_phy, 19, DIV_SEL0, 18, clk_table2);
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PERIPH_CLK_FULL_DD(ddr_fclk, 21, 16, DIV_SEL0, DIV_SEL0, 15, 12);
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PERIPH_CLK_FULL(trace, 22, 18, DIV_SEL0, 20, clk_table6);
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PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL0, 23, clk_table6);
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PERIPH_CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19);
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static PERIPH_PM_CPU(cpu, 22, DIV_SEL0, 28);
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static struct clk_periph_data data_nb[] = {
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REF_CLK_FULL_DD(mmc),
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REF_CLK_FULL_DD(sata_host),
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REF_CLK_FULL_DD(sec_at),
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REF_CLK_FULL_DD(sec_dap),
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REF_CLK_FULL_DD(tscem),
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REF_CLK_FULL(tscem_tmx),
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REF_CLK_GATE(avs, "xtal"),
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REF_CLK_FULL_DD(sqf),
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REF_CLK_FULL_DD(pwm),
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REF_CLK_GATE(i2c_2, "xtal"),
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REF_CLK_GATE(i2c_1, "xtal"),
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REF_CLK_GATE_DIV(ddr_phy, "TBG-A-S"),
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REF_CLK_FULL_DD(ddr_fclk),
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REF_CLK_FULL(trace),
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REF_CLK_FULL(counter),
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REF_CLK_FULL_DD(eip97),
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REF_CLK_PM_CPU(cpu),
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{ },
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};
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/* SB periph clocks */
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PERIPH_CLK_MUX_DD(gbe_50, 6, DIV_SEL2, DIV_SEL2, 6, 9);
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PERIPH_CLK_MUX_DD(gbe_core, 8, DIV_SEL1, DIV_SEL1, 18, 21);
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PERIPH_CLK_MUX_DD(gbe_125, 10, DIV_SEL1, DIV_SEL1, 6, 9);
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static PERIPH_GATE(gbe1_50, 0);
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static PERIPH_GATE(gbe0_50, 1);
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static PERIPH_GATE(gbe1_125, 2);
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static PERIPH_GATE(gbe0_125, 3);
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PERIPH_CLK_GATE_DIV(gbe1_core, 4, DIV_SEL1, 13, clk_table1);
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PERIPH_CLK_GATE_DIV(gbe0_core, 5, DIV_SEL1, 14, clk_table1);
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PERIPH_CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, clk_table1);
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PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6);
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PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12);
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PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18);
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static struct clk_periph_data data_sb[] = {
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REF_CLK_MUX_DD(gbe_50),
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REF_CLK_MUX_DD(gbe_core),
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REF_CLK_MUX_DD(gbe_125),
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REF_CLK_GATE(gbe1_50, "gbe_50"),
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REF_CLK_GATE(gbe0_50, "gbe_50"),
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REF_CLK_GATE(gbe1_125, "gbe_125"),
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REF_CLK_GATE(gbe0_125, "gbe_125"),
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REF_CLK_GATE_DIV(gbe1_core, "gbe_core"),
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REF_CLK_GATE_DIV(gbe0_core, "gbe_core"),
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REF_CLK_GATE_DIV(gbe_bm, "gbe_core"),
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REF_CLK_FULL_DD(sdio),
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REF_CLK_FULL_DD(usb32_usb2_sys),
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REF_CLK_FULL_DD(usb32_ss_sys),
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{ },
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};
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static unsigned int get_div(void __iomem *reg, int shift)
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{
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u32 val;
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val = (readl(reg) >> shift) & 0x7;
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if (val > 6)
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return 0;
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return val;
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}
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static unsigned long clk_double_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_double_div *double_div = to_clk_double_div(hw);
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unsigned int div;
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div = get_div(double_div->reg1, double_div->shift1);
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div *= get_div(double_div->reg2, double_div->shift2);
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return DIV_ROUND_UP_ULL((u64)parent_rate, div);
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}
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static const struct clk_ops clk_double_div_ops = {
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.recalc_rate = clk_double_div_recalc_rate,
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};
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static void armada_3700_pm_dvfs_update_regs(unsigned int load_level,
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unsigned int *reg,
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unsigned int *offset)
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{
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if (load_level <= ARMADA_37XX_DVFS_LOAD_1)
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*reg = ARMADA_37XX_NB_L0L1;
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else
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*reg = ARMADA_37XX_NB_L2L3;
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if (load_level == ARMADA_37XX_DVFS_LOAD_0 ||
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load_level == ARMADA_37XX_DVFS_LOAD_2)
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*offset += ARMADA_37XX_NB_CONFIG_SHIFT;
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}
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static bool armada_3700_pm_dvfs_is_enabled(struct regmap *base)
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{
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unsigned int val, reg = ARMADA_37XX_NB_DYN_MOD;
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if (IS_ERR(base))
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return false;
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regmap_read(base, reg, &val);
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return !!(val & BIT(ARMADA_37XX_NB_DFS_EN));
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}
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static unsigned int armada_3700_pm_dvfs_get_cpu_div(struct regmap *base)
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{
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unsigned int reg = ARMADA_37XX_NB_CPU_LOAD;
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unsigned int offset = ARMADA_37XX_NB_TBG_DIV_OFF;
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unsigned int load_level, div;
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/*
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* This function is always called after the function
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* armada_3700_pm_dvfs_is_enabled, so no need to check again
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* if the base is valid.
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*/
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regmap_read(base, reg, &load_level);
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/*
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* The register and the offset inside this register accessed to
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* read the current divider depend on the load level
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*/
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load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
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armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
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regmap_read(base, reg, &div);
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return (div >> offset) & ARMADA_37XX_NB_TBG_DIV_MASK;
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}
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static unsigned int armada_3700_pm_dvfs_get_cpu_parent(struct regmap *base)
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{
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unsigned int reg = ARMADA_37XX_NB_CPU_LOAD;
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unsigned int offset = ARMADA_37XX_NB_TBG_SEL_OFF;
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unsigned int load_level, sel;
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/*
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* This function is always called after the function
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* armada_3700_pm_dvfs_is_enabled, so no need to check again
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* if the base is valid
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*/
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regmap_read(base, reg, &load_level);
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/*
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* The register and the offset inside this register accessed to
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* read the current divider depend on the load level
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*/
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load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
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armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
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regmap_read(base, reg, &sel);
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return (sel >> offset) & ARMADA_37XX_NB_TBG_SEL_MASK;
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}
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static u8 clk_pm_cpu_get_parent(struct clk_hw *hw)
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{
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struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
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int num_parents = clk_hw_get_num_parents(hw);
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u32 val;
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if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base)) {
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val = armada_3700_pm_dvfs_get_cpu_parent(pm_cpu->nb_pm_base);
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} else {
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val = readl(pm_cpu->reg_mux) >> pm_cpu->shift_mux;
|
|
val &= pm_cpu->mask_mux;
|
|
}
|
|
|
|
if (val >= num_parents)
|
|
return -EINVAL;
|
|
|
|
return val;
|
|
}
|
|
|
|
static int clk_pm_cpu_set_parent(struct clk_hw *hw, u8 index)
|
|
{
|
|
struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
|
|
struct regmap *base = pm_cpu->nb_pm_base;
|
|
int load_level;
|
|
|
|
/*
|
|
* We set the clock parent only if the DVFS is available but
|
|
* not enabled.
|
|
*/
|
|
if (IS_ERR(base) || armada_3700_pm_dvfs_is_enabled(base))
|
|
return -EINVAL;
|
|
|
|
/* Set the parent clock for all the load level */
|
|
for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
|
|
unsigned int reg, mask, val,
|
|
offset = ARMADA_37XX_NB_TBG_SEL_OFF;
|
|
|
|
armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
|
|
|
|
val = index << offset;
|
|
mask = ARMADA_37XX_NB_TBG_SEL_MASK << offset;
|
|
regmap_update_bits(base, reg, mask, val);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long clk_pm_cpu_recalc_rate(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
|
|
unsigned int div;
|
|
|
|
if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base))
|
|
div = armada_3700_pm_dvfs_get_cpu_div(pm_cpu->nb_pm_base);
|
|
else
|
|
div = get_div(pm_cpu->reg_div, pm_cpu->shift_div);
|
|
return DIV_ROUND_UP_ULL((u64)parent_rate, div);
|
|
}
|
|
|
|
static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long *parent_rate)
|
|
{
|
|
struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
|
|
struct regmap *base = pm_cpu->nb_pm_base;
|
|
unsigned int div = *parent_rate / rate;
|
|
unsigned int load_level;
|
|
/* only available when DVFS is enabled */
|
|
if (!armada_3700_pm_dvfs_is_enabled(base))
|
|
return -EINVAL;
|
|
|
|
for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
|
|
unsigned int reg, val, offset = ARMADA_37XX_NB_TBG_DIV_OFF;
|
|
|
|
armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
|
|
|
|
regmap_read(base, reg, &val);
|
|
|
|
val >>= offset;
|
|
val &= ARMADA_37XX_NB_TBG_DIV_MASK;
|
|
if (val == div)
|
|
/*
|
|
* We found a load level matching the target
|
|
* divider, switch to this load level and
|
|
* return.
|
|
*/
|
|
return *parent_rate / div;
|
|
}
|
|
|
|
/* We didn't find any valid divider */
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
|
|
struct regmap *base = pm_cpu->nb_pm_base;
|
|
unsigned int div = parent_rate / rate;
|
|
unsigned int load_level;
|
|
|
|
/* only available when DVFS is enabled */
|
|
if (!armada_3700_pm_dvfs_is_enabled(base))
|
|
return -EINVAL;
|
|
|
|
for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
|
|
unsigned int reg, mask, val,
|
|
offset = ARMADA_37XX_NB_TBG_DIV_OFF;
|
|
|
|
armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
|
|
|
|
regmap_read(base, reg, &val);
|
|
val >>= offset;
|
|
val &= ARMADA_37XX_NB_TBG_DIV_MASK;
|
|
|
|
if (val == div) {
|
|
/*
|
|
* We found a load level matching the target
|
|
* divider, switch to this load level and
|
|
* return.
|
|
*/
|
|
reg = ARMADA_37XX_NB_CPU_LOAD;
|
|
mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
|
|
regmap_update_bits(base, reg, mask, load_level);
|
|
|
|
return rate;
|
|
}
|
|
}
|
|
|
|
/* We didn't find any valid divider */
|
|
return -EINVAL;
|
|
}
|
|
|
|
static const struct clk_ops clk_pm_cpu_ops = {
|
|
.get_parent = clk_pm_cpu_get_parent,
|
|
.set_parent = clk_pm_cpu_set_parent,
|
|
.round_rate = clk_pm_cpu_round_rate,
|
|
.set_rate = clk_pm_cpu_set_rate,
|
|
.recalc_rate = clk_pm_cpu_recalc_rate,
|
|
};
|
|
|
|
static const struct of_device_id armada_3700_periph_clock_of_match[] = {
|
|
{ .compatible = "marvell,armada-3700-periph-clock-nb",
|
|
.data = data_nb, },
|
|
{ .compatible = "marvell,armada-3700-periph-clock-sb",
|
|
.data = data_sb, },
|
|
{ }
|
|
};
|
|
|
|
static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
|
|
void __iomem *reg, spinlock_t *lock,
|
|
struct device *dev, struct clk_hw **hw)
|
|
{
|
|
const struct clk_ops *mux_ops = NULL, *gate_ops = NULL,
|
|
*rate_ops = NULL;
|
|
struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *rate_hw = NULL;
|
|
|
|
if (data->mux_hw) {
|
|
struct clk_mux *mux;
|
|
|
|
mux_hw = data->mux_hw;
|
|
mux = to_clk_mux(mux_hw);
|
|
mux->lock = lock;
|
|
mux_ops = mux_hw->init->ops;
|
|
mux->reg = reg + (u64)mux->reg;
|
|
}
|
|
|
|
if (data->gate_hw) {
|
|
struct clk_gate *gate;
|
|
|
|
gate_hw = data->gate_hw;
|
|
gate = to_clk_gate(gate_hw);
|
|
gate->lock = lock;
|
|
gate_ops = gate_hw->init->ops;
|
|
gate->reg = reg + (u64)gate->reg;
|
|
gate->flags = CLK_GATE_SET_TO_DISABLE;
|
|
}
|
|
|
|
if (data->rate_hw) {
|
|
rate_hw = data->rate_hw;
|
|
rate_ops = rate_hw->init->ops;
|
|
if (data->is_double_div) {
|
|
struct clk_double_div *rate;
|
|
|
|
rate = to_clk_double_div(rate_hw);
|
|
rate->reg1 = reg + (u64)rate->reg1;
|
|
rate->reg2 = reg + (u64)rate->reg2;
|
|
} else {
|
|
struct clk_divider *rate = to_clk_divider(rate_hw);
|
|
const struct clk_div_table *clkt;
|
|
int table_size = 0;
|
|
|
|
rate->reg = reg + (u64)rate->reg;
|
|
for (clkt = rate->table; clkt->div; clkt++)
|
|
table_size++;
|
|
rate->width = order_base_2(table_size);
|
|
rate->lock = lock;
|
|
}
|
|
}
|
|
|
|
if (data->muxrate_hw) {
|
|
struct clk_pm_cpu *pmcpu_clk;
|
|
struct clk_hw *muxrate_hw = data->muxrate_hw;
|
|
struct regmap *map;
|
|
|
|
pmcpu_clk = to_clk_pm_cpu(muxrate_hw);
|
|
pmcpu_clk->reg_mux = reg + (u64)pmcpu_clk->reg_mux;
|
|
pmcpu_clk->reg_div = reg + (u64)pmcpu_clk->reg_div;
|
|
|
|
mux_hw = muxrate_hw;
|
|
rate_hw = muxrate_hw;
|
|
mux_ops = muxrate_hw->init->ops;
|
|
rate_ops = muxrate_hw->init->ops;
|
|
|
|
map = syscon_regmap_lookup_by_compatible(
|
|
"marvell,armada-3700-nb-pm");
|
|
pmcpu_clk->nb_pm_base = map;
|
|
}
|
|
|
|
*hw = clk_hw_register_composite(dev, data->name, data->parent_names,
|
|
data->num_parents, mux_hw,
|
|
mux_ops, rate_hw, rate_ops,
|
|
gate_hw, gate_ops, CLK_IGNORE_UNUSED);
|
|
|
|
return PTR_ERR_OR_ZERO(*hw);
|
|
}
|
|
|
|
static int armada_3700_periph_clock_probe(struct platform_device *pdev)
|
|
{
|
|
struct clk_periph_driver_data *driver_data;
|
|
struct device_node *np = pdev->dev.of_node;
|
|
const struct clk_periph_data *data;
|
|
struct device *dev = &pdev->dev;
|
|
int num_periph = 0, i, ret;
|
|
struct resource *res;
|
|
void __iomem *reg;
|
|
|
|
data = of_device_get_match_data(dev);
|
|
if (!data)
|
|
return -ENODEV;
|
|
|
|
while (data[num_periph].name)
|
|
num_periph++;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
reg = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(reg))
|
|
return PTR_ERR(reg);
|
|
|
|
driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL);
|
|
if (!driver_data)
|
|
return -ENOMEM;
|
|
|
|
driver_data->hw_data = devm_kzalloc(dev,
|
|
struct_size(driver_data->hw_data,
|
|
hws, num_periph),
|
|
GFP_KERNEL);
|
|
if (!driver_data->hw_data)
|
|
return -ENOMEM;
|
|
driver_data->hw_data->num = num_periph;
|
|
|
|
spin_lock_init(&driver_data->lock);
|
|
|
|
for (i = 0; i < num_periph; i++) {
|
|
struct clk_hw **hw = &driver_data->hw_data->hws[i];
|
|
|
|
if (armada_3700_add_composite_clk(&data[i], reg,
|
|
&driver_data->lock, dev, hw))
|
|
dev_err(dev, "Can't register periph clock %s\n",
|
|
data[i].name);
|
|
}
|
|
|
|
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
|
|
driver_data->hw_data);
|
|
if (ret) {
|
|
for (i = 0; i < num_periph; i++)
|
|
clk_hw_unregister(driver_data->hw_data->hws[i]);
|
|
return ret;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, driver_data);
|
|
return 0;
|
|
}
|
|
|
|
static int armada_3700_periph_clock_remove(struct platform_device *pdev)
|
|
{
|
|
struct clk_periph_driver_data *data = platform_get_drvdata(pdev);
|
|
struct clk_hw_onecell_data *hw_data = data->hw_data;
|
|
int i;
|
|
|
|
of_clk_del_provider(pdev->dev.of_node);
|
|
|
|
for (i = 0; i < hw_data->num; i++)
|
|
clk_hw_unregister(hw_data->hws[i]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver armada_3700_periph_clock_driver = {
|
|
.probe = armada_3700_periph_clock_probe,
|
|
.remove = armada_3700_periph_clock_remove,
|
|
.driver = {
|
|
.name = "marvell-armada-3700-periph-clock",
|
|
.of_match_table = armada_3700_periph_clock_of_match,
|
|
},
|
|
};
|
|
|
|
builtin_platform_driver(armada_3700_periph_clock_driver);
|