mirror of https://gitee.com/openkylin/linux.git
476490a945
Thanks to Ville Syrjälä for pointing me towards the cause of this issue. Unfortunately one of the sideaffects of having the refclk for a DPLL set to SSC is that as long as it's set to SSC, the GPU will prevent us from powering down any of the pipes or transcoders using it. A couple of BIOSes enable SSC in both PCH_DREF_CONTROL and in the DPLL configurations. This causes issues on the first modeset, since we don't expect SSC to be left on and as a result, can't successfully power down the pipes or the transcoders using it. Here's an example from this Dell OptiPlex 990: [drm:intel_modeset_init] SSC enabled by BIOS, overriding VBT which says disabled [drm:intel_modeset_init] 2 display pipes available. [drm:intel_update_cdclk] Current CD clock rate: 400000 kHz [drm:intel_update_max_cdclk] Max CD clock rate: 400000 kHz [drm:intel_update_max_cdclk] Max dotclock rate: 360000 kHz vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem [drm:intel_crt_reset] crt adpa set to 0xf40000 [drm:intel_dp_init_connector] Adding DP connector on port C [drm:intel_dp_aux_init] registering DPDDC-C bus for card0-DP-1 [drm:ironlake_init_pch_refclk] has_panel 0 has_lvds 0 has_ck505 0 [drm:ironlake_init_pch_refclk] Disabling SSC entirely … later we try committing the first modeset … [drm:intel_dump_pipe_config] [CRTC:26][modeset] config ffff88041b02e800 for pipe A [drm:intel_dump_pipe_config] cpu_transcoder: A … [drm:intel_dump_pipe_config] dpll_hw_state: dpll: 0xc4016001, dpll_md: 0x0, fp0: 0x20e08, fp1: 0x30d07 [drm:intel_dump_pipe_config] planes on this crtc [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 0.0 idx: 0 enabled [drm:intel_dump_pipe_config] FB:42, fb = 800x600 format = 0x34325258 [drm:intel_dump_pipe_config] scaler:0 src (0, 0) 800x600 dst (0, 0) 800x600 [drm:intel_dump_pipe_config] CURSOR PLANE:25 plane: 0.1 idx: 1 disabled, scaler_id = 0 [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 0.1 idx: 2 disabled, scaler_id = 0 [drm:intel_get_shared_dpll] CRTC:26 allocated PCH DPLL A [drm:intel_get_shared_dpll] using PCH DPLL A for pipe A [drm:ilk_audio_codec_disable] Disable audio codec on port C, pipe A [drm:intel_disable_pipe] disabling pipe A ------------[ cut here ]------------ WARNING: CPU: 1 PID: 130 at drivers/gpu/drm/i915/intel_display.c:1146 intel_disable_pipe+0x297/0x2d0 [i915] pipe_off wait timed out … ---[ end trace 94fc8aa03ae139e8 ]--- [drm:intel_dp_link_down] [drm:ironlake_crtc_disable [i915]] *ERROR* failed to disable transcoder A Later modesets succeed since they reset the DPLL's configuration anyway, but this is enough to get stuck with a big fat warning in dmesg. A better solution would be to add refcounts for the SSC source, but for now leaving the source clock on should suffice. Changes since v4: - Fix calculation of final for systems with LVDS panels (fixes BUG() on CI test suite) Changes since v3: - Move temp variable into loop - Move checks for using_ssc_source to after we've figured out has_ck505 - Add using_ssc_source to debug output Changes since v2: - Fix debug output for when we disable the CPU source Changes since v1: - Leave the SSC source clock on instead of just shutting it off on all of the DPLL configurations. Cc: stable@vger.kernel.org Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Lyude <cpaul@redhat.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1465916649-10228-1-git-send-email-cpaul@redhat.com Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
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| .. | ||
| Kconfig | ||
| Kconfig.debug | ||
| Makefile | ||
| dvo.h | ||
| dvo_ch7xxx.c | ||
| dvo_ch7017.c | ||
| dvo_ivch.c | ||
| dvo_ns2501.c | ||
| dvo_sil164.c | ||
| dvo_tfp410.c | ||
| i915_cmd_parser.c | ||
| i915_debugfs.c | ||
| i915_dma.c | ||
| i915_drv.c | ||
| i915_drv.h | ||
| i915_gem.c | ||
| i915_gem.h | ||
| i915_gem_batch_pool.c | ||
| i915_gem_batch_pool.h | ||
| i915_gem_context.c | ||
| i915_gem_debug.c | ||
| i915_gem_dmabuf.c | ||
| i915_gem_evict.c | ||
| i915_gem_execbuffer.c | ||
| i915_gem_fence.c | ||
| i915_gem_gtt.c | ||
| i915_gem_gtt.h | ||
| i915_gem_render_state.c | ||
| i915_gem_render_state.h | ||
| i915_gem_shrinker.c | ||
| i915_gem_stolen.c | ||
| i915_gem_tiling.c | ||
| i915_gem_userptr.c | ||
| i915_gpu_error.c | ||
| i915_guc_reg.h | ||
| i915_guc_submission.c | ||
| i915_ioc32.c | ||
| i915_irq.c | ||
| i915_params.c | ||
| i915_params.h | ||
| i915_reg.h | ||
| i915_suspend.c | ||
| i915_sysfs.c | ||
| i915_trace.h | ||
| i915_trace_points.c | ||
| i915_vgpu.c | ||
| i915_vgpu.h | ||
| intel_acpi.c | ||
| intel_atomic.c | ||
| intel_atomic_plane.c | ||
| intel_audio.c | ||
| intel_bios.c | ||
| intel_bios.h | ||
| intel_color.c | ||
| intel_crt.c | ||
| intel_csr.c | ||
| intel_ddi.c | ||
| intel_display.c | ||
| intel_dp.c | ||
| intel_dp_link_training.c | ||
| intel_dp_mst.c | ||
| intel_dpll_mgr.c | ||
| intel_dpll_mgr.h | ||
| intel_drv.h | ||
| intel_dsi.c | ||
| intel_dsi.h | ||
| intel_dsi_panel_vbt.c | ||
| intel_dsi_pll.c | ||
| intel_dvo.c | ||
| intel_fbc.c | ||
| intel_fbdev.c | ||
| intel_fifo_underrun.c | ||
| intel_frontbuffer.c | ||
| intel_guc.h | ||
| intel_guc_fwif.h | ||
| intel_guc_loader.c | ||
| intel_hdmi.c | ||
| intel_hotplug.c | ||
| intel_i2c.c | ||
| intel_lrc.c | ||
| intel_lrc.h | ||
| intel_lvds.c | ||
| intel_mocs.c | ||
| intel_mocs.h | ||
| intel_modes.c | ||
| intel_opregion.c | ||
| intel_overlay.c | ||
| intel_panel.c | ||
| intel_pm.c | ||
| intel_psr.c | ||
| intel_renderstate.h | ||
| intel_renderstate_gen6.c | ||
| intel_renderstate_gen7.c | ||
| intel_renderstate_gen8.c | ||
| intel_renderstate_gen9.c | ||
| intel_ringbuffer.c | ||
| intel_ringbuffer.h | ||
| intel_runtime_pm.c | ||
| intel_sdvo.c | ||
| intel_sdvo_regs.h | ||
| intel_sideband.c | ||
| intel_sprite.c | ||
| intel_tv.c | ||
| intel_uncore.c | ||
| intel_vbt_defs.h | ||