mirror of https://gitee.com/openkylin/linux.git
487 lines
13 KiB
C
487 lines
13 KiB
C
/*
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* include/asm-x86_64/processor.h
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*
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* Copyright (C) 1994 Linus Torvalds
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*/
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#ifndef __ASM_X86_64_PROCESSOR_H
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#define __ASM_X86_64_PROCESSOR_H
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/types.h>
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#include <asm/sigcontext.h>
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#include <asm/cpufeature.h>
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#include <linux/config.h>
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#include <linux/threads.h>
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#include <asm/msr.h>
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#include <asm/current.h>
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#include <asm/system.h>
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#include <asm/mmsegment.h>
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#include <asm/percpu.h>
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#include <linux/personality.h>
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#include <linux/cpumask.h>
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#define TF_MASK 0x00000100
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#define IF_MASK 0x00000200
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#define IOPL_MASK 0x00003000
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#define NT_MASK 0x00004000
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#define VM_MASK 0x00020000
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#define AC_MASK 0x00040000
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#define VIF_MASK 0x00080000 /* virtual interrupt flag */
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#define VIP_MASK 0x00100000 /* virtual interrupt pending */
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#define ID_MASK 0x00200000
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#define desc_empty(desc) \
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(!((desc)->a | (desc)->b))
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#define desc_equal(desc1, desc2) \
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(((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
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/*
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* Default implementation of macro that returns current
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* instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
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/*
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* CPU type and hardware bug flags. Kept separately for each CPU.
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*/
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struct cpuinfo_x86 {
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__u8 x86; /* CPU family */
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__u8 x86_vendor; /* CPU vendor */
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__u8 x86_model;
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__u8 x86_mask;
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int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
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__u32 x86_capability[NCAPINTS];
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char x86_vendor_id[16];
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char x86_model_id[64];
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int x86_cache_size; /* in KB */
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int x86_clflush_size;
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int x86_cache_alignment;
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int x86_tlbsize; /* number of 4K pages in DTLB/ITLB combined(in pages)*/
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__u8 x86_virt_bits, x86_phys_bits;
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__u8 x86_max_cores; /* cpuid returned max cores value */
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__u32 x86_power;
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__u32 extended_cpuid_level; /* Max extended CPUID function supported */
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unsigned long loops_per_jiffy;
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#ifdef CONFIG_SMP
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cpumask_t llc_shared_map; /* cpus sharing the last level cache */
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#endif
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__u8 apicid;
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__u8 booted_cores; /* number of cores as seen by OS */
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} ____cacheline_aligned;
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#define X86_VENDOR_INTEL 0
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#define X86_VENDOR_CYRIX 1
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#define X86_VENDOR_AMD 2
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#define X86_VENDOR_UMC 3
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#define X86_VENDOR_NEXGEN 4
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#define X86_VENDOR_CENTAUR 5
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#define X86_VENDOR_RISE 6
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#define X86_VENDOR_TRANSMETA 7
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#define X86_VENDOR_NUM 8
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#define X86_VENDOR_UNKNOWN 0xff
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#ifdef CONFIG_SMP
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extern struct cpuinfo_x86 cpu_data[];
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#define current_cpu_data cpu_data[smp_processor_id()]
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#else
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#define cpu_data (&boot_cpu_data)
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#define current_cpu_data boot_cpu_data
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#endif
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extern char ignore_irq13;
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extern void identify_cpu(struct cpuinfo_x86 *);
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extern void print_cpu_info(struct cpuinfo_x86 *);
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extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
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/*
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* EFLAGS bits
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*/
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#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
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#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
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#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
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#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
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#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
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#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
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#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
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#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
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#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
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#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
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#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
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#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
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#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
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#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
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#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
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#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
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#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
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/*
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* Intel CPU features in CR4
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*/
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#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
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#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
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#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
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#define X86_CR4_DE 0x0008 /* enable debugging extensions */
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#define X86_CR4_PSE 0x0010 /* enable page size extensions */
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#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
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#define X86_CR4_MCE 0x0040 /* Machine check enable */
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#define X86_CR4_PGE 0x0080 /* enable global pages */
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#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
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#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
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#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
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/*
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* Save the cr4 feature set we're using (ie
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* Pentium 4MB enable and PPro Global page
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* enable), so that any CPU's that boot up
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* after us can get the correct flags.
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*/
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extern unsigned long mmu_cr4_features;
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static inline void set_in_cr4 (unsigned long mask)
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{
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mmu_cr4_features |= mask;
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__asm__("movq %%cr4,%%rax\n\t"
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"orq %0,%%rax\n\t"
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"movq %%rax,%%cr4\n"
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: : "irg" (mask)
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:"ax");
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}
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static inline void clear_in_cr4 (unsigned long mask)
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{
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mmu_cr4_features &= ~mask;
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__asm__("movq %%cr4,%%rax\n\t"
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"andq %0,%%rax\n\t"
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"movq %%rax,%%cr4\n"
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: : "irg" (~mask)
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:"ax");
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}
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/*
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* User space process size. 47bits minus one guard page.
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*/
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#define TASK_SIZE64 (0x800000000000UL - 4096)
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/* This decides where the kernel will search for a free chunk of vm
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* space during mmap's.
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*/
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#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? 0xc0000000 : 0xFFFFe000)
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#define TASK_SIZE (test_thread_flag(TIF_IA32) ? IA32_PAGE_OFFSET : TASK_SIZE64)
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#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? IA32_PAGE_OFFSET : TASK_SIZE64)
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#define TASK_UNMAPPED_BASE PAGE_ALIGN(TASK_SIZE/3)
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/*
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* Size of io_bitmap.
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*/
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#define IO_BITMAP_BITS 65536
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#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
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#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
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#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
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#define INVALID_IO_BITMAP_OFFSET 0x8000
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struct i387_fxsave_struct {
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u16 cwd;
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u16 swd;
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u16 twd;
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u16 fop;
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u64 rip;
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u64 rdp;
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u32 mxcsr;
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u32 mxcsr_mask;
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u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
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u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 128 bytes */
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u32 padding[24];
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} __attribute__ ((aligned (16)));
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union i387_union {
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struct i387_fxsave_struct fxsave;
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};
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struct tss_struct {
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u32 reserved1;
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u64 rsp0;
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u64 rsp1;
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u64 rsp2;
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u64 reserved2;
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u64 ist[7];
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u32 reserved3;
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u32 reserved4;
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u16 reserved5;
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u16 io_bitmap_base;
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/*
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* The extra 1 is there because the CPU will access an
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* additional byte beyond the end of the IO permission
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* bitmap. The extra byte must be all 1 bits, and must
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* be within the limit. Thus we have:
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*
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* 128 bytes, the bitmap itself, for ports 0..0x3ff
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* 8 bytes, for an extra "long" of ~0UL
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*/
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unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
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} __attribute__((packed)) ____cacheline_aligned;
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extern struct cpuinfo_x86 boot_cpu_data;
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DECLARE_PER_CPU(struct tss_struct,init_tss);
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#ifdef CONFIG_X86_VSMP
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#define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
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#define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
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#else
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#define ARCH_MIN_TASKALIGN 16
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#define ARCH_MIN_MMSTRUCT_ALIGN 0
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#endif
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struct thread_struct {
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unsigned long rsp0;
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unsigned long rsp;
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unsigned long userrsp; /* Copy from PDA */
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unsigned long fs;
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unsigned long gs;
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unsigned short es, ds, fsindex, gsindex;
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/* Hardware debugging registers */
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unsigned long debugreg0;
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unsigned long debugreg1;
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unsigned long debugreg2;
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unsigned long debugreg3;
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unsigned long debugreg6;
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unsigned long debugreg7;
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/* fault info */
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unsigned long cr2, trap_no, error_code;
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/* floating point info */
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union i387_union i387 __attribute__((aligned(16)));
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/* IO permissions. the bitmap could be moved into the GDT, that would make
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switch faster for a limited number of ioperm using tasks. -AK */
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int ioperm;
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unsigned long *io_bitmap_ptr;
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unsigned io_bitmap_max;
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/* cached TLS descriptors. */
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u64 tls_array[GDT_ENTRY_TLS_ENTRIES];
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} __attribute__((aligned(16)));
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#define INIT_THREAD { \
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.rsp0 = (unsigned long)&init_stack + sizeof(init_stack) \
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}
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#define INIT_TSS { \
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.rsp0 = (unsigned long)&init_stack + sizeof(init_stack) \
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}
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#define INIT_MMAP \
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{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, NULL, NULL }
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#define start_thread(regs,new_rip,new_rsp) do { \
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asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \
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load_gs_index(0); \
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(regs)->rip = (new_rip); \
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(regs)->rsp = (new_rsp); \
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write_pda(oldrsp, (new_rsp)); \
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(regs)->cs = __USER_CS; \
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(regs)->ss = __USER_DS; \
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(regs)->eflags = 0x200; \
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set_fs(USER_DS); \
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} while(0)
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#define get_debugreg(var, register) \
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__asm__("movq %%db" #register ", %0" \
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:"=r" (var))
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#define set_debugreg(value, register) \
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__asm__("movq %0,%%db" #register \
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: /* no output */ \
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:"r" (value))
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struct task_struct;
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struct mm_struct;
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/* Free all resources held by a thread. */
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extern void release_thread(struct task_struct *);
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/* Prepare to copy thread state - unlazy all lazy status */
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extern void prepare_to_copy(struct task_struct *tsk);
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/*
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* create a kernel thread without removing it from tasklists
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*/
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extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
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/*
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* Return saved PC of a blocked thread.
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* What is this good for? it will be always the scheduler or ret_from_fork.
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*/
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#define thread_saved_pc(t) (*(unsigned long *)((t)->thread.rsp - 8))
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extern unsigned long get_wchan(struct task_struct *p);
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#define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.rsp0 - 1)
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#define KSTK_EIP(tsk) (task_pt_regs(tsk)->rip)
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#define KSTK_ESP(tsk) -1 /* sorry. doesn't work for syscall. */
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struct microcode_header {
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unsigned int hdrver;
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unsigned int rev;
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unsigned int date;
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unsigned int sig;
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unsigned int cksum;
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unsigned int ldrver;
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unsigned int pf;
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unsigned int datasize;
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unsigned int totalsize;
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unsigned int reserved[3];
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};
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struct microcode {
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struct microcode_header hdr;
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unsigned int bits[0];
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};
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typedef struct microcode microcode_t;
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typedef struct microcode_header microcode_header_t;
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/* microcode format is extended from prescott processors */
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struct extended_signature {
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unsigned int sig;
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unsigned int pf;
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unsigned int cksum;
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};
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struct extended_sigtable {
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unsigned int count;
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unsigned int cksum;
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unsigned int reserved[3];
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struct extended_signature sigs[0];
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};
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/* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
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#define MICROCODE_IOCFREE _IO('6',0)
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#define ASM_NOP1 K8_NOP1
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#define ASM_NOP2 K8_NOP2
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#define ASM_NOP3 K8_NOP3
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#define ASM_NOP4 K8_NOP4
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#define ASM_NOP5 K8_NOP5
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#define ASM_NOP6 K8_NOP6
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#define ASM_NOP7 K8_NOP7
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#define ASM_NOP8 K8_NOP8
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/* Opteron nops */
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#define K8_NOP1 ".byte 0x90\n"
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#define K8_NOP2 ".byte 0x66,0x90\n"
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#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
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#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
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#define K8_NOP5 K8_NOP3 K8_NOP2
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#define K8_NOP6 K8_NOP3 K8_NOP3
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#define K8_NOP7 K8_NOP4 K8_NOP3
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#define K8_NOP8 K8_NOP4 K8_NOP4
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#define ASM_NOP_MAX 8
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/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
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static inline void rep_nop(void)
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{
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__asm__ __volatile__("rep;nop": : :"memory");
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}
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/* Stop speculative execution */
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static inline void sync_core(void)
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{
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int tmp;
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asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
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}
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#define cpu_has_fpu 1
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#define ARCH_HAS_PREFETCH
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static inline void prefetch(void *x)
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{
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asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
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}
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#define ARCH_HAS_PREFETCHW 1
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static inline void prefetchw(void *x)
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{
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alternative_input("prefetcht0 (%1)",
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"prefetchw (%1)",
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X86_FEATURE_3DNOW,
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"r" (x));
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}
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#define ARCH_HAS_SPINLOCK_PREFETCH 1
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#define spin_lock_prefetch(x) prefetchw(x)
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#define cpu_relax() rep_nop()
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/*
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* NSC/Cyrix CPU configuration register indexes
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*/
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#define CX86_CCR0 0xc0
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#define CX86_CCR1 0xc1
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#define CX86_CCR2 0xc2
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#define CX86_CCR3 0xc3
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#define CX86_CCR4 0xe8
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#define CX86_CCR5 0xe9
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#define CX86_CCR6 0xea
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#define CX86_CCR7 0xeb
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#define CX86_DIR0 0xfe
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#define CX86_DIR1 0xff
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#define CX86_ARR_BASE 0xc4
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#define CX86_RCR_BASE 0xdc
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/*
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* NSC/Cyrix CPU indexed register access macros
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*/
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#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
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#define setCx86(reg, data) do { \
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outb((reg), 0x22); \
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outb((data), 0x23); \
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} while (0)
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static inline void serialize_cpu(void)
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{
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__asm__ __volatile__ ("cpuid" : : : "ax", "bx", "cx", "dx");
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}
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static inline void __monitor(const void *eax, unsigned long ecx,
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unsigned long edx)
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{
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/* "monitor %eax,%ecx,%edx;" */
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asm volatile(
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".byte 0x0f,0x01,0xc8;"
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: :"a" (eax), "c" (ecx), "d"(edx));
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}
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static inline void __mwait(unsigned long eax, unsigned long ecx)
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{
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/* "mwait %eax,%ecx;" */
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asm volatile(
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".byte 0x0f,0x01,0xc9;"
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: :"a" (eax), "c" (ecx));
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}
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#define stack_current() \
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({ \
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struct thread_info *ti; \
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asm("andq %%rsp,%0; ":"=r" (ti) : "0" (CURRENT_MASK)); \
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ti->task; \
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})
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#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
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extern unsigned long boot_option_idle_override;
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/* Boot loader type from the setup header */
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extern int bootloader_type;
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#define HAVE_ARCH_PICK_MMAP_LAYOUT 1
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#endif /* __ASM_X86_64_PROCESSOR_H */
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