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61 lines
1.7 KiB
Plaintext
61 lines
1.7 KiB
Plaintext
* Allwinner A1X Pin Controller
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The pins controlled by sunXi pin controller are organized in banks,
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each bank has 32 pins. Each pin has 7 multiplexing functions, with
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the first two functions being GPIO in and out. The configuration on
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the pins includes drive strength and pull-up.
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Required properties:
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- compatible: "allwinner,<soc>-pinctrl". Supported SoCs for now are:
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sun5i-a13.
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- reg: Should contain the register physical address and length for the
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pin controller.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices.
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A pinctrl node should contain at least one subnodes representing the
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pinctrl groups available on the machine. Each subnode will list the
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pins it needs, and how they should be configured, with regard to muxer
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configuration, drive strength and pullups. If one of these options is
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not set, its actual value will be unspecified.
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Required subnode-properties:
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- allwinner,pins: List of strings containing the pin name.
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- allwinner,function: Function to mux the pins listed above to.
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Optional subnode-properties:
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- allwinner,drive: Integer. Represents the current sent to the pin
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0: 10 mA
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1: 20 mA
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2: 30 mA
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3: 40 mA
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- allwinner,pull: Integer.
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0: No resistor
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1: Pull-up resistor
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2: Pull-down resistor
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Examples:
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pinctrl@01c20800 {
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compatible = "allwinner,sun5i-a13-pinctrl";
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reg = <0x01c20800 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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uart1_pins_a: uart1@0 {
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allwinner,pins = "PE10", "PE11";
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allwinner,function = "uart1";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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uart1_pins_b: uart1@1 {
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allwinner,pins = "PG3", "PG4";
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allwinner,function = "uart1";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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};
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