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52 lines
1.6 KiB
Plaintext
52 lines
1.6 KiB
Plaintext
* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
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The Low-Power Clock Gate (LPCG) modules contain a local programming
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model to control the clock gates for the peripherals. An LPCG module
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is used to locally gate the clocks for the associated peripheral.
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Note:
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This level of clock gating is provided after the clocks are generated
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by the SCU resources and clock controls. Thus even if the clock is
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enabled by these control bits, it might still not be running based
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on the base resource.
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Required properties:
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- compatible: Should be one of:
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"fsl,imx8qxp-lpcg-adma",
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"fsl,imx8qxp-lpcg-conn",
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"fsl,imx8qxp-lpcg-dc",
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"fsl,imx8qxp-lpcg-dsp",
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"fsl,imx8qxp-lpcg-gpu",
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"fsl,imx8qxp-lpcg-hsio",
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"fsl,imx8qxp-lpcg-img",
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"fsl,imx8qxp-lpcg-lsio",
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"fsl,imx8qxp-lpcg-vpu"
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- reg: Address and length of the register set
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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See the full list of clock IDs from:
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include/dt-bindings/clock/imx8qxp-clock.h
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Examples:
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#include <dt-bindings/clock/imx8qxp-clock.h>
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conn_lpcg: clock-controller@5b200000 {
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compatible = "fsl,imx8qxp-lpcg-conn";
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reg = <0x5b200000 0xb0000>;
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#clock-cells = <1>;
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};
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usdhc1: mmc@5b010000 {
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compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x5b010000 0x10000>;
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clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>,
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<&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>,
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<&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>;
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clock-names = "ipg", "per", "ahb";
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};
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