mirror of https://gitee.com/openkylin/linux.git
367 lines
9.0 KiB
C
367 lines
9.0 KiB
C
/*
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* Broadcom BCM7038 style Level 1 interrupt controller driver
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*
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* Copyright (C) 2014 Broadcom Corporation
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* Author: Kevin Cernekee
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/bitops.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#define IRQS_PER_WORD 32
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#define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
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#define MAX_WORDS 8
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struct bcm7038_l1_cpu;
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struct bcm7038_l1_chip {
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raw_spinlock_t lock;
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unsigned int n_words;
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struct irq_domain *domain;
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struct bcm7038_l1_cpu *cpus[NR_CPUS];
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u8 affinity[MAX_WORDS * IRQS_PER_WORD];
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};
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struct bcm7038_l1_cpu {
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void __iomem *map_base;
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u32 mask_cache[0];
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};
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/*
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* STATUS/MASK_STATUS/MASK_SET/MASK_CLEAR are packed one right after another:
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*
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* 7038:
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* 0x1000_1400: W0_STATUS
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* 0x1000_1404: W1_STATUS
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* 0x1000_1408: W0_MASK_STATUS
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* 0x1000_140c: W1_MASK_STATUS
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* 0x1000_1410: W0_MASK_SET
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* 0x1000_1414: W1_MASK_SET
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* 0x1000_1418: W0_MASK_CLEAR
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* 0x1000_141c: W1_MASK_CLEAR
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*
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* 7445:
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* 0xf03e_1500: W0_STATUS
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* 0xf03e_1504: W1_STATUS
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* 0xf03e_1508: W2_STATUS
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* 0xf03e_150c: W3_STATUS
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* 0xf03e_1510: W4_STATUS
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* 0xf03e_1514: W0_MASK_STATUS
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* 0xf03e_1518: W1_MASK_STATUS
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* [...]
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*/
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static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
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unsigned int word)
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{
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return (0 * intc->n_words + word) * sizeof(u32);
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}
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static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc,
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unsigned int word)
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{
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return (1 * intc->n_words + word) * sizeof(u32);
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}
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static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
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unsigned int word)
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{
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return (2 * intc->n_words + word) * sizeof(u32);
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}
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static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
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unsigned int word)
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{
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return (3 * intc->n_words + word) * sizeof(u32);
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}
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static inline u32 l1_readl(void __iomem *reg)
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{
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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return ioread32be(reg);
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else
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return readl(reg);
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}
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static inline void l1_writel(u32 val, void __iomem *reg)
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{
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if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
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iowrite32be(val, reg);
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else
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writel(val, reg);
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}
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static void bcm7038_l1_irq_handle(struct irq_desc *desc)
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{
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struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
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struct bcm7038_l1_cpu *cpu;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int idx;
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#ifdef CONFIG_SMP
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cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
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#else
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cpu = intc->cpus[0];
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#endif
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chained_irq_enter(chip, desc);
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for (idx = 0; idx < intc->n_words; idx++) {
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int base = idx * IRQS_PER_WORD;
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unsigned long pending, flags;
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int hwirq;
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raw_spin_lock_irqsave(&intc->lock, flags);
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pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
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~cpu->mask_cache[idx];
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raw_spin_unlock_irqrestore(&intc->lock, flags);
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for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
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generic_handle_irq(irq_find_mapping(intc->domain,
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base + hwirq));
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}
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}
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chained_irq_exit(chip, desc);
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}
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static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
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{
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struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
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u32 word = d->hwirq / IRQS_PER_WORD;
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u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
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intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
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l1_writel(mask, intc->cpus[cpu_idx]->map_base +
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reg_mask_clr(intc, word));
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}
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static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
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{
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struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
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u32 word = d->hwirq / IRQS_PER_WORD;
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u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
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intc->cpus[cpu_idx]->mask_cache[word] |= mask;
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l1_writel(mask, intc->cpus[cpu_idx]->map_base +
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reg_mask_set(intc, word));
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}
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static void bcm7038_l1_unmask(struct irq_data *d)
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{
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struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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raw_spin_lock_irqsave(&intc->lock, flags);
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__bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
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raw_spin_unlock_irqrestore(&intc->lock, flags);
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}
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static void bcm7038_l1_mask(struct irq_data *d)
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{
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struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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raw_spin_lock_irqsave(&intc->lock, flags);
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__bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
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raw_spin_unlock_irqrestore(&intc->lock, flags);
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}
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static int bcm7038_l1_set_affinity(struct irq_data *d,
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const struct cpumask *dest,
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bool force)
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{
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struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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irq_hw_number_t hw = d->hwirq;
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u32 word = hw / IRQS_PER_WORD;
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u32 mask = BIT(hw % IRQS_PER_WORD);
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unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
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bool was_disabled;
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raw_spin_lock_irqsave(&intc->lock, flags);
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was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
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mask);
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__bcm7038_l1_mask(d, intc->affinity[hw]);
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intc->affinity[hw] = first_cpu;
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if (!was_disabled)
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__bcm7038_l1_unmask(d, first_cpu);
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raw_spin_unlock_irqrestore(&intc->lock, flags);
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irq_data_update_effective_affinity(d, cpumask_of(first_cpu));
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return 0;
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}
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#ifdef CONFIG_SMP
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static void bcm7038_l1_cpu_offline(struct irq_data *d)
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{
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struct cpumask *mask = irq_data_get_affinity_mask(d);
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int cpu = smp_processor_id();
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cpumask_t new_affinity;
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/* This CPU was not on the affinity mask */
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if (!cpumask_test_cpu(cpu, mask))
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return;
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if (cpumask_weight(mask) > 1) {
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/*
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* Multiple CPU affinity, remove this CPU from the affinity
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* mask
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*/
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cpumask_copy(&new_affinity, mask);
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cpumask_clear_cpu(cpu, &new_affinity);
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} else {
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/* Only CPU, put on the lowest online CPU */
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cpumask_clear(&new_affinity);
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cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
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}
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irq_set_affinity_locked(d, &new_affinity, false);
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}
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#endif
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static int __init bcm7038_l1_init_one(struct device_node *dn,
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unsigned int idx,
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struct bcm7038_l1_chip *intc)
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{
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struct resource res;
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resource_size_t sz;
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struct bcm7038_l1_cpu *cpu;
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unsigned int i, n_words, parent_irq;
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if (of_address_to_resource(dn, idx, &res))
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return -EINVAL;
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sz = resource_size(&res);
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n_words = sz / REG_BYTES_PER_IRQ_WORD;
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if (n_words > MAX_WORDS)
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return -EINVAL;
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else if (!intc->n_words)
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intc->n_words = n_words;
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else if (intc->n_words != n_words)
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return -EINVAL;
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cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
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GFP_KERNEL);
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if (!cpu)
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return -ENOMEM;
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cpu->map_base = ioremap(res.start, sz);
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if (!cpu->map_base)
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return -ENOMEM;
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for (i = 0; i < n_words; i++) {
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l1_writel(0xffffffff, cpu->map_base + reg_mask_set(intc, i));
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cpu->mask_cache[i] = 0xffffffff;
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}
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parent_irq = irq_of_parse_and_map(dn, idx);
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if (!parent_irq) {
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pr_err("failed to map parent interrupt %d\n", parent_irq);
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return -EINVAL;
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}
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irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
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intc);
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return 0;
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}
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static struct irq_chip bcm7038_l1_irq_chip = {
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.name = "bcm7038-l1",
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.irq_mask = bcm7038_l1_mask,
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.irq_unmask = bcm7038_l1_unmask,
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.irq_set_affinity = bcm7038_l1_set_affinity,
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#ifdef CONFIG_SMP
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.irq_cpu_offline = bcm7038_l1_cpu_offline,
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#endif
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};
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static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw_irq)
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{
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irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
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irq_set_chip_data(virq, d->host_data);
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irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
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return 0;
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}
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static const struct irq_domain_ops bcm7038_l1_domain_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = bcm7038_l1_map,
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};
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int __init bcm7038_l1_of_init(struct device_node *dn,
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struct device_node *parent)
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{
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struct bcm7038_l1_chip *intc;
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int idx, ret;
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intc = kzalloc(sizeof(*intc), GFP_KERNEL);
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if (!intc)
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return -ENOMEM;
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raw_spin_lock_init(&intc->lock);
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for_each_possible_cpu(idx) {
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ret = bcm7038_l1_init_one(dn, idx, intc);
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if (ret < 0) {
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if (idx)
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break;
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pr_err("failed to remap intc L1 registers\n");
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goto out_free;
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}
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}
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intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
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&bcm7038_l1_domain_ops,
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intc);
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if (!intc->domain) {
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ret = -ENOMEM;
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goto out_unmap;
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}
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pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n",
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dn, IRQS_PER_WORD * intc->n_words);
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return 0;
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out_unmap:
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for_each_possible_cpu(idx) {
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struct bcm7038_l1_cpu *cpu = intc->cpus[idx];
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if (cpu) {
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if (cpu->map_base)
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iounmap(cpu->map_base);
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kfree(cpu);
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}
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}
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out_free:
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kfree(intc);
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return ret;
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}
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IRQCHIP_DECLARE(bcm7038_l1, "brcm,bcm7038-l1-intc", bcm7038_l1_of_init);
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