mirror of https://gitee.com/openkylin/linux.git
165 lines
4.4 KiB
C
165 lines
4.4 KiB
C
/*
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* IRQ vector handles
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*
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* Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/ptrace.h>
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#include <linux/time.h>
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#include <asm/irq_cpu.h>
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#include <msp_int.h>
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/* SLP bases systems */
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extern void msp_slp_irq_init(void);
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extern void msp_slp_irq_dispatch(void);
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/* CIC based systems */
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extern void msp_cic_irq_init(void);
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extern void msp_cic_irq_dispatch(void);
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/* VSMP support init */
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extern void msp_vsmp_int_init(void);
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/* vectored interrupt implementation */
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/* SW0/1 interrupts are used for SMP/SMTC */
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static inline void mac0_int_dispatch(void) { do_IRQ(MSP_INT_MAC0); }
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static inline void mac1_int_dispatch(void) { do_IRQ(MSP_INT_MAC1); }
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static inline void mac2_int_dispatch(void) { do_IRQ(MSP_INT_SAR); }
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static inline void usb_int_dispatch(void) { do_IRQ(MSP_INT_USB); }
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static inline void sec_int_dispatch(void) { do_IRQ(MSP_INT_SEC); }
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/*
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* The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded
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* hierarchical system. The first level are the direct MIPS interrupts
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* and are assigned the interrupt range 0-7. The second level is the SLM
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* interrupt controller and is assigned the range 8-39. The third level
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* comprises the Peripherial block, the PCI block, the PCI MSI block and
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* the SLP. The PCI interrupts and the SLP errors are handled by the
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* relevant subsystems so the core interrupt code needs only concern
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* itself with the Peripheral block. These are assigned interrupts in
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* the range 40-71.
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*/
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asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
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{
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u32 pending;
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pending = read_c0_status() & read_c0_cause();
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/*
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* jump to the correct interrupt routine
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* These are arranged in priority order and the timer
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* comes first!
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*/
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#ifdef CONFIG_IRQ_MSP_CIC /* break out the CIC stuff for now */
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if (pending & C_IRQ4) /* do the peripherals first, that's the timer */
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msp_cic_irq_dispatch();
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else if (pending & C_IRQ0)
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do_IRQ(MSP_INT_MAC0);
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else if (pending & C_IRQ1)
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do_IRQ(MSP_INT_MAC1);
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else if (pending & C_IRQ2)
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do_IRQ(MSP_INT_USB);
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else if (pending & C_IRQ3)
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do_IRQ(MSP_INT_SAR);
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else if (pending & C_IRQ5)
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do_IRQ(MSP_INT_SEC);
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#else
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if (pending & C_IRQ5)
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do_IRQ(MSP_INT_TIMER);
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else if (pending & C_IRQ0)
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do_IRQ(MSP_INT_MAC0);
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else if (pending & C_IRQ1)
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do_IRQ(MSP_INT_MAC1);
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else if (pending & C_IRQ3)
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do_IRQ(MSP_INT_VE);
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else if (pending & C_IRQ4)
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msp_slp_irq_dispatch();
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#endif
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else if (pending & C_SW0) /* do software after hardware */
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do_IRQ(MSP_INT_SW0);
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else if (pending & C_SW1)
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do_IRQ(MSP_INT_SW1);
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}
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static struct irqaction cic_cascade_msp = {
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.handler = no_action,
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.name = "MSP CIC cascade",
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.flags = IRQF_NO_THREAD,
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};
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static struct irqaction per_cascade_msp = {
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.handler = no_action,
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.name = "MSP PER cascade",
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.flags = IRQF_NO_THREAD,
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};
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void __init arch_init_irq(void)
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{
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/* assume we'll be using vectored interrupt mode except in UP mode*/
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#ifdef CONFIG_MIPS_MT
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BUG_ON(!cpu_has_vint);
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#endif
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/* initialize the 1st-level CPU based interrupt controller */
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mips_cpu_irq_init();
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#ifdef CONFIG_IRQ_MSP_CIC
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msp_cic_irq_init();
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#ifdef CONFIG_MIPS_MT
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set_vi_handler(MSP_INT_CIC, msp_cic_irq_dispatch);
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set_vi_handler(MSP_INT_MAC0, mac0_int_dispatch);
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set_vi_handler(MSP_INT_MAC1, mac1_int_dispatch);
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set_vi_handler(MSP_INT_SAR, mac2_int_dispatch);
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set_vi_handler(MSP_INT_USB, usb_int_dispatch);
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set_vi_handler(MSP_INT_SEC, sec_int_dispatch);
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#ifdef CONFIG_MIPS_MT_SMP
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msp_vsmp_int_init();
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#elif defined CONFIG_MIPS_MT_SMTC
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/*Set hwmask for all platform devices */
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irq_hwmask[MSP_INT_MAC0] = C_IRQ0;
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irq_hwmask[MSP_INT_MAC1] = C_IRQ1;
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irq_hwmask[MSP_INT_USB] = C_IRQ2;
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irq_hwmask[MSP_INT_SAR] = C_IRQ3;
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irq_hwmask[MSP_INT_SEC] = C_IRQ5;
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#endif /* CONFIG_MIPS_MT_SMP */
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#endif /* CONFIG_MIPS_MT */
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/* setup the cascaded interrupts */
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setup_irq(MSP_INT_CIC, &cic_cascade_msp);
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setup_irq(MSP_INT_PER, &per_cascade_msp);
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#else
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/* setup the 2nd-level SLP register based interrupt controller */
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/* VSMP /SMTC support support is not enabled for SLP */
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msp_slp_irq_init();
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/* setup the cascaded SLP/PER interrupts */
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setup_irq(MSP_INT_SLP, &cic_cascade_msp);
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setup_irq(MSP_INT_PER, &per_cascade_msp);
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#endif
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}
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