mirror of https://gitee.com/openkylin/linux.git
914 lines
26 KiB
C
914 lines
26 KiB
C
/*
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*
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* IPACX specific routines
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*
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* Author Joerg Petersohn
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* Derived from hisax_isac.c, isac.c, hscx.c and others
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include "hisax_if.h"
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#include "hisax.h"
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#include "isdnl1.h"
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#include "ipacx.h"
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#define DBUSY_TIMER_VALUE 80
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#define TIMER3_VALUE 7000
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#define MAX_DFRAME_LEN_L1 300
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#define B_FIFO_SIZE 64
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#define D_FIFO_SIZE 32
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// ipacx interrupt mask values
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#define _MASK_IMASK 0x2E // global mask
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#define _MASKB_IMASK 0x0B
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#define _MASKD_IMASK 0x03 // all on
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//----------------------------------------------------------
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// local function declarations
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//----------------------------------------------------------
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static void ph_command(struct IsdnCardState *cs, unsigned int command);
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static inline void cic_int(struct IsdnCardState *cs);
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static void dch_l2l1(struct PStack *st, int pr, void *arg);
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static void dbusy_timer_handler(struct timer_list *t);
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static void dch_empty_fifo(struct IsdnCardState *cs, int count);
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static void dch_fill_fifo(struct IsdnCardState *cs);
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static inline void dch_int(struct IsdnCardState *cs);
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static void dch_setstack(struct PStack *st, struct IsdnCardState *cs);
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static void dch_init(struct IsdnCardState *cs);
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static void bch_l2l1(struct PStack *st, int pr, void *arg);
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static void bch_empty_fifo(struct BCState *bcs, int count);
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static void bch_fill_fifo(struct BCState *bcs);
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static void bch_int(struct IsdnCardState *cs, u_char hscx);
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static void bch_mode(struct BCState *bcs, int mode, int bc);
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static void bch_close_state(struct BCState *bcs);
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static int bch_open_state(struct IsdnCardState *cs, struct BCState *bcs);
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static int bch_setstack(struct PStack *st, struct BCState *bcs);
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static void bch_init(struct IsdnCardState *cs, int hscx);
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static void clear_pending_ints(struct IsdnCardState *cs);
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//----------------------------------------------------------
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// Issue Layer 1 command to chip
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//----------------------------------------------------------
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static void
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ph_command(struct IsdnCardState *cs, unsigned int command)
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{
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if (cs->debug & L1_DEB_ISAC)
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debugl1(cs, "ph_command (%#x) in (%#x)", command,
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cs->dc.isac.ph_state);
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//###################################
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// printk(KERN_INFO "ph_command (%#x)\n", command);
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//###################################
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cs->writeisac(cs, IPACX_CIX0, (command << 4) | 0x0E);
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}
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//----------------------------------------------------------
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// Transceiver interrupt handler
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//----------------------------------------------------------
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static inline void
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cic_int(struct IsdnCardState *cs)
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{
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u_char event;
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event = cs->readisac(cs, IPACX_CIR0) >> 4;
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if (cs->debug & L1_DEB_ISAC) debugl1(cs, "cic_int(event=%#x)", event);
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//#########################################
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// printk(KERN_INFO "cic_int(%x)\n", event);
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//#########################################
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cs->dc.isac.ph_state = event;
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schedule_event(cs, D_L1STATECHANGE);
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}
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//==========================================================
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// D channel functions
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//==========================================================
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//----------------------------------------------------------
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// Command entry point
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//----------------------------------------------------------
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static void
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dch_l2l1(struct PStack *st, int pr, void *arg)
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{
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struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
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struct sk_buff *skb = arg;
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u_char cda1_cr;
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switch (pr) {
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case (PH_DATA | REQUEST):
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if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len);
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if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
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if (cs->tx_skb) {
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skb_queue_tail(&cs->sq, skb);
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#ifdef L2FRAME_DEBUG
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if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA Queued", 0);
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#endif
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} else {
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cs->tx_skb = skb;
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cs->tx_cnt = 0;
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#ifdef L2FRAME_DEBUG
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if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA", 0);
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#endif
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dch_fill_fifo(cs);
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}
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break;
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case (PH_PULL | INDICATION):
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if (cs->tx_skb) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
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skb_queue_tail(&cs->sq, skb);
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break;
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}
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if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len);
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if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0);
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cs->tx_skb = skb;
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cs->tx_cnt = 0;
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#ifdef L2FRAME_DEBUG
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if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
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#endif
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dch_fill_fifo(cs);
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break;
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case (PH_PULL | REQUEST):
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#ifdef L2FRAME_DEBUG
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if (cs->debug & L1_DEB_LAPD) debugl1(cs, "-> PH_REQUEST_PULL");
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#endif
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if (!cs->tx_skb) {
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clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
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st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
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} else
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set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
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break;
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case (HW_RESET | REQUEST):
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case (HW_ENABLE | REQUEST):
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if ((cs->dc.isac.ph_state == IPACX_IND_RES) ||
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(cs->dc.isac.ph_state == IPACX_IND_DR) ||
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(cs->dc.isac.ph_state == IPACX_IND_DC))
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ph_command(cs, IPACX_CMD_TIM);
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else
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ph_command(cs, IPACX_CMD_RES);
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break;
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case (HW_INFO3 | REQUEST):
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ph_command(cs, IPACX_CMD_AR8);
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break;
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case (HW_TESTLOOP | REQUEST):
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cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1
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cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1
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cda1_cr = cs->readisac(cs, IPACX_CDA1_CR);
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(void) cs->readisac(cs, IPACX_CDA2_CR);
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if ((long)arg & 1) { // loop B1
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cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr | 0x0a);
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}
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else { // B1 off
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cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr & ~0x0a);
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}
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if ((long)arg & 2) { // loop B2
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cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr | 0x14);
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}
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else { // B2 off
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cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr & ~0x14);
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}
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break;
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case (HW_DEACTIVATE | RESPONSE):
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skb_queue_purge(&cs->rq);
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skb_queue_purge(&cs->sq);
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if (cs->tx_skb) {
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dev_kfree_skb_any(cs->tx_skb);
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cs->tx_skb = NULL;
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}
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if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
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del_timer(&cs->dbusytimer);
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break;
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default:
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if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_l2l1 unknown %04x", pr);
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break;
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}
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}
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//----------------------------------------------------------
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//----------------------------------------------------------
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static void
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dbusy_timer_handler(struct timer_list *t)
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{
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struct IsdnCardState *cs = from_timer(cs, t, dbusytimer);
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struct PStack *st;
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int rbchd, stard;
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if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
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rbchd = cs->readisac(cs, IPACX_RBCHD);
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stard = cs->readisac(cs, IPACX_STARD);
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if (cs->debug)
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debugl1(cs, "D-Channel Busy RBCHD %02x STARD %02x", rbchd, stard);
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if (!(stard & 0x40)) { // D-Channel Busy
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set_bit(FLG_L1_DBUSY, &cs->HW_Flags);
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for (st = cs->stlist; st; st = st->next) {
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st->l1.l1l2(st, PH_PAUSE | INDICATION, NULL); // flow control on
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}
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} else {
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// seems we lost an interrupt; reset transceiver */
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clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags);
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if (cs->tx_skb) {
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dev_kfree_skb_any(cs->tx_skb);
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cs->tx_cnt = 0;
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cs->tx_skb = NULL;
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} else {
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printk(KERN_WARNING "HiSax: ISAC D-Channel Busy no skb\n");
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debugl1(cs, "D-Channel Busy no skb");
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}
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cs->writeisac(cs, IPACX_CMDRD, 0x01); // Tx reset, generates XPR
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}
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}
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}
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//----------------------------------------------------------
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// Fill buffer from receive FIFO
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//----------------------------------------------------------
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static void
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dch_empty_fifo(struct IsdnCardState *cs, int count)
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{
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u_char *ptr;
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if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
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debugl1(cs, "dch_empty_fifo()");
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// message too large, remove
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if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "dch_empty_fifo() incoming message too large");
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cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
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cs->rcvidx = 0;
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return;
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}
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ptr = cs->rcvbuf + cs->rcvidx;
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cs->rcvidx += count;
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cs->readisacfifo(cs, ptr, count);
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cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
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if (cs->debug & L1_DEB_ISAC_FIFO) {
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char *t = cs->dlog;
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t += sprintf(t, "dch_empty_fifo() cnt %d", count);
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QuickHex(t, ptr, count);
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debugl1(cs, "%s", cs->dlog);
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}
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}
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//----------------------------------------------------------
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// Fill transmit FIFO
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//----------------------------------------------------------
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static void
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dch_fill_fifo(struct IsdnCardState *cs)
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{
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int count;
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u_char cmd, *ptr;
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if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO))
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debugl1(cs, "dch_fill_fifo()");
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if (!cs->tx_skb) return;
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count = cs->tx_skb->len;
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if (count <= 0) return;
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if (count > D_FIFO_SIZE) {
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count = D_FIFO_SIZE;
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cmd = 0x08; // XTF
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} else {
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cmd = 0x0A; // XTF | XME
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}
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ptr = cs->tx_skb->data;
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skb_pull(cs->tx_skb, count);
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cs->tx_cnt += count;
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cs->writeisacfifo(cs, ptr, count);
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cs->writeisac(cs, IPACX_CMDRD, cmd);
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// set timeout for transmission contol
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if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
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debugl1(cs, "dch_fill_fifo dbusytimer running");
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del_timer(&cs->dbusytimer);
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}
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cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
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add_timer(&cs->dbusytimer);
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if (cs->debug & L1_DEB_ISAC_FIFO) {
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char *t = cs->dlog;
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t += sprintf(t, "dch_fill_fifo() cnt %d", count);
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QuickHex(t, ptr, count);
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debugl1(cs, "%s", cs->dlog);
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}
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}
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//----------------------------------------------------------
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// D channel interrupt handler
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//----------------------------------------------------------
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static inline void
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dch_int(struct IsdnCardState *cs)
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{
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struct sk_buff *skb;
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u_char istad, rstad;
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int count;
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istad = cs->readisac(cs, IPACX_ISTAD);
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//##############################################
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// printk(KERN_WARNING "dch_int(istad=%02x)\n", istad);
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//##############################################
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if (istad & 0x80) { // RME
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rstad = cs->readisac(cs, IPACX_RSTAD);
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if ((rstad & 0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB)
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if (!(rstad & 0x80))
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "dch_int(): invalid frame");
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if ((rstad & 0x40))
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "dch_int(): RDO");
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if (!(rstad & 0x20))
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "dch_int(): CRC error");
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cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
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} else { // received frame ok
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count = cs->readisac(cs, IPACX_RBCLD);
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if (count) count--; // RSTAB is last byte
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count &= D_FIFO_SIZE - 1;
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if (count == 0) count = D_FIFO_SIZE;
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dch_empty_fifo(cs, count);
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if ((count = cs->rcvidx) > 0) {
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cs->rcvidx = 0;
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if (!(skb = dev_alloc_skb(count)))
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printk(KERN_WARNING "HiSax dch_int(): receive out of memory\n");
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else {
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skb_put_data(skb, cs->rcvbuf, count);
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skb_queue_tail(&cs->rq, skb);
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}
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}
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}
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cs->rcvidx = 0;
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schedule_event(cs, D_RCVBUFREADY);
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}
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if (istad & 0x40) { // RPF
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dch_empty_fifo(cs, D_FIFO_SIZE);
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}
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if (istad & 0x20) { // RFO
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if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_int(): RFO");
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cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES
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}
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if (istad & 0x10) { // XPR
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if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
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del_timer(&cs->dbusytimer);
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if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
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schedule_event(cs, D_CLEARBUSY);
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if (cs->tx_skb) {
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if (cs->tx_skb->len) {
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dch_fill_fifo(cs);
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goto afterXPR;
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}
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else {
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dev_kfree_skb_irq(cs->tx_skb);
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cs->tx_skb = NULL;
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cs->tx_cnt = 0;
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}
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}
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if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
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cs->tx_cnt = 0;
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dch_fill_fifo(cs);
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}
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else {
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schedule_event(cs, D_XMTBUFREADY);
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}
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}
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afterXPR:
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if (istad & 0x0C) { // XDU or XMR
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if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_int(): XDU");
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if (cs->tx_skb) {
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skb_push(cs->tx_skb, cs->tx_cnt); // retransmit
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cs->tx_cnt = 0;
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dch_fill_fifo(cs);
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} else {
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printk(KERN_WARNING "HiSax: ISAC XDU no skb\n");
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debugl1(cs, "ISAC XDU no skb");
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}
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}
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}
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//----------------------------------------------------------
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//----------------------------------------------------------
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static void
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dch_setstack(struct PStack *st, struct IsdnCardState *cs)
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{
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st->l1.l1hw = dch_l2l1;
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}
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//----------------------------------------------------------
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//----------------------------------------------------------
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static void
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dch_init(struct IsdnCardState *cs)
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{
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printk(KERN_INFO "HiSax: IPACX ISDN driver v0.1.0\n");
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cs->setstack_d = dch_setstack;
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timer_setup(&cs->dbusytimer, dbusy_timer_handler, 0);
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cs->writeisac(cs, IPACX_TR_CONF0, 0x00); // clear LDD
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cs->writeisac(cs, IPACX_TR_CONF2, 0x00); // enable transmitter
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cs->writeisac(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go
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cs->writeisac(cs, IPACX_MON_CR, 0x00); // disable monitor channel
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}
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|
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//==========================================================
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// B channel functions
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//==========================================================
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|
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//----------------------------------------------------------
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// Entry point for commands
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//----------------------------------------------------------
|
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static void
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bch_l2l1(struct PStack *st, int pr, void *arg)
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{
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struct BCState *bcs = st->l1.bcs;
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struct sk_buff *skb = arg;
|
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u_long flags;
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switch (pr) {
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case (PH_DATA | REQUEST):
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spin_lock_irqsave(&bcs->cs->lock, flags);
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if (bcs->tx_skb) {
|
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skb_queue_tail(&bcs->squeue, skb);
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} else {
|
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bcs->tx_skb = skb;
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set_bit(BC_FLG_BUSY, &bcs->Flag);
|
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bcs->hw.hscx.count = 0;
|
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bch_fill_fifo(bcs);
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}
|
|
spin_unlock_irqrestore(&bcs->cs->lock, flags);
|
|
break;
|
|
case (PH_PULL | INDICATION):
|
|
spin_lock_irqsave(&bcs->cs->lock, flags);
|
|
if (bcs->tx_skb) {
|
|
printk(KERN_WARNING "HiSax bch_l2l1(): this shouldn't happen\n");
|
|
} else {
|
|
set_bit(BC_FLG_BUSY, &bcs->Flag);
|
|
bcs->tx_skb = skb;
|
|
bcs->hw.hscx.count = 0;
|
|
bch_fill_fifo(bcs);
|
|
}
|
|
spin_unlock_irqrestore(&bcs->cs->lock, flags);
|
|
break;
|
|
case (PH_PULL | REQUEST):
|
|
if (!bcs->tx_skb) {
|
|
clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
|
st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
|
|
} else
|
|
set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
|
break;
|
|
case (PH_ACTIVATE | REQUEST):
|
|
spin_lock_irqsave(&bcs->cs->lock, flags);
|
|
set_bit(BC_FLG_ACTIV, &bcs->Flag);
|
|
bch_mode(bcs, st->l1.mode, st->l1.bc);
|
|
spin_unlock_irqrestore(&bcs->cs->lock, flags);
|
|
l1_msg_b(st, pr, arg);
|
|
break;
|
|
case (PH_DEACTIVATE | REQUEST):
|
|
l1_msg_b(st, pr, arg);
|
|
break;
|
|
case (PH_DEACTIVATE | CONFIRM):
|
|
spin_lock_irqsave(&bcs->cs->lock, flags);
|
|
clear_bit(BC_FLG_ACTIV, &bcs->Flag);
|
|
clear_bit(BC_FLG_BUSY, &bcs->Flag);
|
|
bch_mode(bcs, 0, st->l1.bc);
|
|
spin_unlock_irqrestore(&bcs->cs->lock, flags);
|
|
st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
|
|
break;
|
|
}
|
|
}
|
|
|
|
//----------------------------------------------------------
|
|
// Read B channel fifo to receive buffer
|
|
//----------------------------------------------------------
|
|
static void
|
|
bch_empty_fifo(struct BCState *bcs, int count)
|
|
{
|
|
u_char *ptr, hscx;
|
|
struct IsdnCardState *cs;
|
|
int cnt;
|
|
|
|
cs = bcs->cs;
|
|
hscx = bcs->hw.hscx.hscx;
|
|
if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
|
|
debugl1(cs, "bch_empty_fifo()");
|
|
|
|
// message too large, remove
|
|
if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "bch_empty_fifo() incoming packet too large");
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
|
|
bcs->hw.hscx.rcvidx = 0;
|
|
return;
|
|
}
|
|
|
|
ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
|
|
cnt = count;
|
|
while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB);
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
|
|
|
|
ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
|
|
bcs->hw.hscx.rcvidx += count;
|
|
|
|
if (cs->debug & L1_DEB_HSCX_FIFO) {
|
|
char *t = bcs->blog;
|
|
|
|
t += sprintf(t, "bch_empty_fifo() B-%d cnt %d", hscx, count);
|
|
QuickHex(t, ptr, count);
|
|
debugl1(cs, "%s", bcs->blog);
|
|
}
|
|
}
|
|
|
|
//----------------------------------------------------------
|
|
// Fill buffer to transmit FIFO
|
|
//----------------------------------------------------------
|
|
static void
|
|
bch_fill_fifo(struct BCState *bcs)
|
|
{
|
|
struct IsdnCardState *cs;
|
|
int more, count, cnt;
|
|
u_char *ptr, *p, hscx;
|
|
|
|
cs = bcs->cs;
|
|
if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
|
|
debugl1(cs, "bch_fill_fifo()");
|
|
|
|
if (!bcs->tx_skb) return;
|
|
if (bcs->tx_skb->len <= 0) return;
|
|
|
|
hscx = bcs->hw.hscx.hscx;
|
|
more = (bcs->mode == L1_MODE_TRANS) ? 1 : 0;
|
|
if (bcs->tx_skb->len > B_FIFO_SIZE) {
|
|
more = 1;
|
|
count = B_FIFO_SIZE;
|
|
} else {
|
|
count = bcs->tx_skb->len;
|
|
}
|
|
cnt = count;
|
|
|
|
p = ptr = bcs->tx_skb->data;
|
|
skb_pull(bcs->tx_skb, count);
|
|
bcs->tx_cnt -= count;
|
|
bcs->hw.hscx.count += count;
|
|
while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++);
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a));
|
|
|
|
if (cs->debug & L1_DEB_HSCX_FIFO) {
|
|
char *t = bcs->blog;
|
|
|
|
t += sprintf(t, "%s() B-%d cnt %d", __func__, hscx, count);
|
|
QuickHex(t, ptr, count);
|
|
debugl1(cs, "%s", bcs->blog);
|
|
}
|
|
}
|
|
|
|
//----------------------------------------------------------
|
|
// B channel interrupt handler
|
|
//----------------------------------------------------------
|
|
static void
|
|
bch_int(struct IsdnCardState *cs, u_char hscx)
|
|
{
|
|
u_char istab;
|
|
struct BCState *bcs;
|
|
struct sk_buff *skb;
|
|
int count;
|
|
u_char rstab;
|
|
|
|
bcs = cs->bcs + hscx;
|
|
istab = cs->BC_Read_Reg(cs, hscx, IPACX_ISTAB);
|
|
//##############################################
|
|
// printk(KERN_WARNING "bch_int(istab=%02x)\n", istab);
|
|
//##############################################
|
|
if (!test_bit(BC_FLG_INIT, &bcs->Flag)) return;
|
|
|
|
if (istab & 0x80) { // RME
|
|
rstab = cs->BC_Read_Reg(cs, hscx, IPACX_RSTAB);
|
|
if ((rstab & 0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB)
|
|
if (!(rstab & 0x80))
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "bch_int() B-%d: invalid frame", hscx);
|
|
if ((rstab & 0x40) && (bcs->mode != L1_MODE_NULL))
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "bch_int() B-%d: RDO mode=%d", hscx, bcs->mode);
|
|
if (!(rstab & 0x20))
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "bch_int() B-%d: CRC error", hscx);
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC
|
|
}
|
|
else { // received frame ok
|
|
count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) & (B_FIFO_SIZE - 1);
|
|
if (count == 0) count = B_FIFO_SIZE;
|
|
bch_empty_fifo(bcs, count);
|
|
if ((count = bcs->hw.hscx.rcvidx - 1) > 0) {
|
|
if (cs->debug & L1_DEB_HSCX_FIFO)
|
|
debugl1(cs, "bch_int Frame %d", count);
|
|
if (!(skb = dev_alloc_skb(count)))
|
|
printk(KERN_WARNING "HiSax bch_int(): receive frame out of memory\n");
|
|
else {
|
|
skb_put_data(skb, bcs->hw.hscx.rcvbuf,
|
|
count);
|
|
skb_queue_tail(&bcs->rqueue, skb);
|
|
}
|
|
}
|
|
}
|
|
bcs->hw.hscx.rcvidx = 0;
|
|
schedule_event(bcs, B_RCVBUFREADY);
|
|
}
|
|
|
|
if (istab & 0x40) { // RPF
|
|
bch_empty_fifo(bcs, B_FIFO_SIZE);
|
|
|
|
if (bcs->mode == L1_MODE_TRANS) { // queue every chunk
|
|
// receive transparent audio data
|
|
if (!(skb = dev_alloc_skb(B_FIFO_SIZE)))
|
|
printk(KERN_WARNING "HiSax bch_int(): receive transparent out of memory\n");
|
|
else {
|
|
skb_put_data(skb, bcs->hw.hscx.rcvbuf,
|
|
B_FIFO_SIZE);
|
|
skb_queue_tail(&bcs->rqueue, skb);
|
|
}
|
|
bcs->hw.hscx.rcvidx = 0;
|
|
schedule_event(bcs, B_RCVBUFREADY);
|
|
}
|
|
}
|
|
|
|
if (istab & 0x20) { // RFO
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "bch_int() B-%d: RFO error", hscx);
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40); // RRES
|
|
}
|
|
|
|
if (istab & 0x10) { // XPR
|
|
if (bcs->tx_skb) {
|
|
if (bcs->tx_skb->len) {
|
|
bch_fill_fifo(bcs);
|
|
goto afterXPR;
|
|
} else {
|
|
if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
|
|
(PACKET_NOACK != bcs->tx_skb->pkt_type)) {
|
|
u_long flags;
|
|
spin_lock_irqsave(&bcs->aclock, flags);
|
|
bcs->ackcnt += bcs->hw.hscx.count;
|
|
spin_unlock_irqrestore(&bcs->aclock, flags);
|
|
schedule_event(bcs, B_ACKPENDING);
|
|
}
|
|
}
|
|
dev_kfree_skb_irq(bcs->tx_skb);
|
|
bcs->hw.hscx.count = 0;
|
|
bcs->tx_skb = NULL;
|
|
}
|
|
if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
|
|
bcs->hw.hscx.count = 0;
|
|
set_bit(BC_FLG_BUSY, &bcs->Flag);
|
|
bch_fill_fifo(bcs);
|
|
} else {
|
|
clear_bit(BC_FLG_BUSY, &bcs->Flag);
|
|
schedule_event(bcs, B_XMTBUFREADY);
|
|
}
|
|
}
|
|
afterXPR:
|
|
|
|
if (istab & 0x04) { // XDU
|
|
if (bcs->mode == L1_MODE_TRANS) {
|
|
bch_fill_fifo(bcs);
|
|
}
|
|
else {
|
|
if (bcs->tx_skb) { // restart transmitting the whole frame
|
|
skb_push(bcs->tx_skb, bcs->hw.hscx.count);
|
|
bcs->tx_cnt += bcs->hw.hscx.count;
|
|
bcs->hw.hscx.count = 0;
|
|
}
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01); // XRES
|
|
if (cs->debug & L1_DEB_WARN)
|
|
debugl1(cs, "bch_int() B-%d XDU error", hscx);
|
|
}
|
|
}
|
|
}
|
|
|
|
//----------------------------------------------------------
|
|
//----------------------------------------------------------
|
|
static void
|
|
bch_mode(struct BCState *bcs, int mode, int bc)
|
|
{
|
|
struct IsdnCardState *cs = bcs->cs;
|
|
int hscx = bcs->hw.hscx.hscx;
|
|
|
|
bc = bc ? 1 : 0; // in case bc is greater than 1
|
|
if (cs->debug & L1_DEB_HSCX)
|
|
debugl1(cs, "mode_bch() switch B-%d mode %d chan %d", hscx, mode, bc);
|
|
bcs->mode = mode;
|
|
bcs->channel = bc;
|
|
|
|
// map controller to according timeslot
|
|
if (!hscx)
|
|
{
|
|
cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc);
|
|
cs->writeisac(cs, IPACX_BCHA_CR, 0x88);
|
|
}
|
|
else
|
|
{
|
|
cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc);
|
|
cs->writeisac(cs, IPACX_BCHB_CR, 0x88);
|
|
}
|
|
|
|
switch (mode) {
|
|
case (L1_MODE_NULL):
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj.
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
|
|
break;
|
|
case (L1_MODE_TRANS):
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88); // ext transp mode
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x00); // xxx00000
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
|
|
break;
|
|
case (L1_MODE_HDLC):
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8); // transp mode 0
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments
|
|
cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK);
|
|
break;
|
|
}
|
|
}
|
|
|
|
//----------------------------------------------------------
|
|
//----------------------------------------------------------
|
|
static void
|
|
bch_close_state(struct BCState *bcs)
|
|
{
|
|
bch_mode(bcs, 0, bcs->channel);
|
|
if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
|
|
kfree(bcs->hw.hscx.rcvbuf);
|
|
bcs->hw.hscx.rcvbuf = NULL;
|
|
kfree(bcs->blog);
|
|
bcs->blog = NULL;
|
|
skb_queue_purge(&bcs->rqueue);
|
|
skb_queue_purge(&bcs->squeue);
|
|
if (bcs->tx_skb) {
|
|
dev_kfree_skb_any(bcs->tx_skb);
|
|
bcs->tx_skb = NULL;
|
|
clear_bit(BC_FLG_BUSY, &bcs->Flag);
|
|
}
|
|
}
|
|
}
|
|
|
|
//----------------------------------------------------------
|
|
//----------------------------------------------------------
|
|
static int
|
|
bch_open_state(struct IsdnCardState *cs, struct BCState *bcs)
|
|
{
|
|
if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
|
|
if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
|
|
printk(KERN_WARNING
|
|
"HiSax open_bchstate(): No memory for hscx.rcvbuf\n");
|
|
clear_bit(BC_FLG_INIT, &bcs->Flag);
|
|
return (1);
|
|
}
|
|
if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
|
|
printk(KERN_WARNING
|
|
"HiSax open_bchstate: No memory for bcs->blog\n");
|
|
clear_bit(BC_FLG_INIT, &bcs->Flag);
|
|
kfree(bcs->hw.hscx.rcvbuf);
|
|
bcs->hw.hscx.rcvbuf = NULL;
|
|
return (2);
|
|
}
|
|
skb_queue_head_init(&bcs->rqueue);
|
|
skb_queue_head_init(&bcs->squeue);
|
|
}
|
|
bcs->tx_skb = NULL;
|
|
clear_bit(BC_FLG_BUSY, &bcs->Flag);
|
|
bcs->event = 0;
|
|
bcs->hw.hscx.rcvidx = 0;
|
|
bcs->tx_cnt = 0;
|
|
return (0);
|
|
}
|
|
|
|
//----------------------------------------------------------
|
|
//----------------------------------------------------------
|
|
static int
|
|
bch_setstack(struct PStack *st, struct BCState *bcs)
|
|
{
|
|
bcs->channel = st->l1.bc;
|
|
if (bch_open_state(st->l1.hardware, bcs)) return (-1);
|
|
st->l1.bcs = bcs;
|
|
st->l2.l2l1 = bch_l2l1;
|
|
setstack_manager(st);
|
|
bcs->st = st;
|
|
setstack_l1_B(st);
|
|
return (0);
|
|
}
|
|
|
|
//----------------------------------------------------------
|
|
//----------------------------------------------------------
|
|
static void
|
|
bch_init(struct IsdnCardState *cs, int hscx)
|
|
{
|
|
cs->bcs[hscx].BC_SetStack = bch_setstack;
|
|
cs->bcs[hscx].BC_Close = bch_close_state;
|
|
cs->bcs[hscx].hw.hscx.hscx = hscx;
|
|
cs->bcs[hscx].cs = cs;
|
|
bch_mode(cs->bcs + hscx, 0, hscx);
|
|
}
|
|
|
|
|
|
//==========================================================
|
|
// Shared functions
|
|
//==========================================================
|
|
|
|
//----------------------------------------------------------
|
|
// Main interrupt handler
|
|
//----------------------------------------------------------
|
|
void
|
|
interrupt_ipacx(struct IsdnCardState *cs)
|
|
{
|
|
u_char ista;
|
|
|
|
while ((ista = cs->readisac(cs, IPACX_ISTA))) {
|
|
//#################################################
|
|
// printk(KERN_WARNING "interrupt_ipacx(ista=%02x)\n", ista);
|
|
//#################################################
|
|
if (ista & 0x80) bch_int(cs, 0); // B channel interrupts
|
|
if (ista & 0x40) bch_int(cs, 1);
|
|
|
|
if (ista & 0x01) dch_int(cs); // D channel
|
|
if (ista & 0x10) cic_int(cs); // Layer 1 state
|
|
}
|
|
}
|
|
|
|
//----------------------------------------------------------
|
|
// Clears chip interrupt status
|
|
//----------------------------------------------------------
|
|
static void
|
|
clear_pending_ints(struct IsdnCardState *cs)
|
|
{
|
|
int ista;
|
|
|
|
// all interrupts off
|
|
cs->writeisac(cs, IPACX_MASK, 0xff);
|
|
cs->writeisac(cs, IPACX_MASKD, 0xff);
|
|
cs->BC_Write_Reg(cs, 0, IPACX_MASKB, 0xff);
|
|
cs->BC_Write_Reg(cs, 1, IPACX_MASKB, 0xff);
|
|
|
|
ista = cs->readisac(cs, IPACX_ISTA);
|
|
if (ista & 0x80) cs->BC_Read_Reg(cs, 0, IPACX_ISTAB);
|
|
if (ista & 0x40) cs->BC_Read_Reg(cs, 1, IPACX_ISTAB);
|
|
if (ista & 0x10) cs->readisac(cs, IPACX_CIR0);
|
|
if (ista & 0x01) cs->readisac(cs, IPACX_ISTAD);
|
|
}
|
|
|
|
//----------------------------------------------------------
|
|
// Does chip configuration work
|
|
// Work to do depends on bit mask in part
|
|
//----------------------------------------------------------
|
|
void
|
|
init_ipacx(struct IsdnCardState *cs, int part)
|
|
{
|
|
if (part & 1) { // initialise chip
|
|
//##################################################
|
|
// printk(KERN_INFO "init_ipacx(%x)\n", part);
|
|
//##################################################
|
|
clear_pending_ints(cs);
|
|
bch_init(cs, 0);
|
|
bch_init(cs, 1);
|
|
dch_init(cs);
|
|
}
|
|
if (part & 2) { // reenable all interrupts and start chip
|
|
cs->BC_Write_Reg(cs, 0, IPACX_MASKB, _MASKB_IMASK);
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cs->BC_Write_Reg(cs, 1, IPACX_MASKB, _MASKB_IMASK);
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cs->writeisac(cs, IPACX_MASKD, _MASKD_IMASK);
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cs->writeisac(cs, IPACX_MASK, _MASK_IMASK); // global mask register
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// reset HDLC Transmitters/receivers
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cs->writeisac(cs, IPACX_CMDRD, 0x41);
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cs->BC_Write_Reg(cs, 0, IPACX_CMDRB, 0x41);
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cs->BC_Write_Reg(cs, 1, IPACX_CMDRB, 0x41);
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ph_command(cs, IPACX_CMD_RES);
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}
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}
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//----------------- end of file -----------------------
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