mirror of https://gitee.com/openkylin/linux.git
1226 lines
33 KiB
C
1226 lines
33 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
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#include <linux/clk.h>
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#include <linux/console.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/qcom-geni-se.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/slab.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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/* UART specific GENI registers */
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#define SE_UART_TX_TRANS_CFG 0x25c
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#define SE_UART_TX_WORD_LEN 0x268
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#define SE_UART_TX_STOP_BIT_LEN 0x26c
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#define SE_UART_TX_TRANS_LEN 0x270
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#define SE_UART_RX_TRANS_CFG 0x280
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#define SE_UART_RX_WORD_LEN 0x28c
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#define SE_UART_RX_STALE_CNT 0x294
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#define SE_UART_TX_PARITY_CFG 0x2a4
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#define SE_UART_RX_PARITY_CFG 0x2a8
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/* SE_UART_TRANS_CFG */
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#define UART_TX_PAR_EN BIT(0)
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#define UART_CTS_MASK BIT(1)
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/* SE_UART_TX_WORD_LEN */
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#define TX_WORD_LEN_MSK GENMASK(9, 0)
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/* SE_UART_TX_STOP_BIT_LEN */
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#define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
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#define TX_STOP_BIT_LEN_1 0
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#define TX_STOP_BIT_LEN_1_5 1
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#define TX_STOP_BIT_LEN_2 2
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/* SE_UART_TX_TRANS_LEN */
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#define TX_TRANS_LEN_MSK GENMASK(23, 0)
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/* SE_UART_RX_TRANS_CFG */
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#define UART_RX_INS_STATUS_BIT BIT(2)
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#define UART_RX_PAR_EN BIT(3)
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/* SE_UART_RX_WORD_LEN */
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#define RX_WORD_LEN_MASK GENMASK(9, 0)
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/* SE_UART_RX_STALE_CNT */
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#define RX_STALE_CNT GENMASK(23, 0)
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/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
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#define PAR_CALC_EN BIT(0)
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#define PAR_MODE_MSK GENMASK(2, 1)
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#define PAR_MODE_SHFT 1
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#define PAR_EVEN 0x00
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#define PAR_ODD 0x01
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#define PAR_SPACE 0x10
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#define PAR_MARK 0x11
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/* UART M_CMD OP codes */
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#define UART_START_TX 0x1
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#define UART_START_BREAK 0x4
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#define UART_STOP_BREAK 0x5
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/* UART S_CMD OP codes */
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#define UART_START_READ 0x1
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#define UART_PARAM 0x1
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#define UART_OVERSAMPLING 32
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#define STALE_TIMEOUT 16
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#define DEFAULT_BITS_PER_CHAR 10
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#define GENI_UART_CONS_PORTS 1
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#define DEF_FIFO_DEPTH_WORDS 16
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#define DEF_TX_WM 2
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#define DEF_FIFO_WIDTH_BITS 32
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#define UART_CONSOLE_RX_WM 2
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#ifdef CONFIG_CONSOLE_POLL
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#define RX_BYTES_PW 1
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#else
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#define RX_BYTES_PW 4
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#endif
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struct qcom_geni_serial_port {
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struct uart_port uport;
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struct geni_se se;
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char name[20];
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u32 tx_fifo_depth;
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u32 tx_fifo_width;
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u32 rx_fifo_depth;
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u32 tx_wm;
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u32 rx_wm;
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u32 rx_rfr;
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enum geni_se_xfer_mode xfer_mode;
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bool setup;
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int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
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unsigned int baud;
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unsigned int tx_bytes_pw;
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unsigned int rx_bytes_pw;
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bool brk;
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};
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static const struct uart_ops qcom_geni_console_pops;
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static struct uart_driver qcom_geni_console_driver;
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static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
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static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
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static void qcom_geni_serial_stop_rx(struct uart_port *uport);
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static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
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32000000, 48000000, 64000000, 80000000,
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96000000, 100000000};
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#define to_dev_port(ptr, member) \
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container_of(ptr, struct qcom_geni_serial_port, member)
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static struct qcom_geni_serial_port qcom_geni_console_port = {
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.uport = {
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.iotype = UPIO_MEM,
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.ops = &qcom_geni_console_pops,
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.flags = UPF_BOOT_AUTOCONF,
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.line = 0,
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},
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};
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static int qcom_geni_serial_request_port(struct uart_port *uport)
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{
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struct platform_device *pdev = to_platform_device(uport->dev);
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struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
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struct resource *res;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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uport->membase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(uport->membase))
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return PTR_ERR(uport->membase);
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port->se.base = uport->membase;
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return 0;
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}
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static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
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{
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if (cfg_flags & UART_CONFIG_TYPE) {
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uport->type = PORT_MSM;
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qcom_geni_serial_request_port(uport);
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}
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}
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static unsigned int qcom_geni_cons_get_mctrl(struct uart_port *uport)
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{
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return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS;
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}
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static void qcom_geni_cons_set_mctrl(struct uart_port *uport,
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unsigned int mctrl)
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{
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}
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static const char *qcom_geni_serial_get_type(struct uart_port *uport)
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{
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return "MSM";
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}
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static struct qcom_geni_serial_port *get_port_from_line(int line)
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{
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if (line < 0 || line >= GENI_UART_CONS_PORTS)
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return ERR_PTR(-ENXIO);
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return &qcom_geni_console_port;
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}
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static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
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int offset, int field, bool set)
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{
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u32 reg;
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struct qcom_geni_serial_port *port;
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unsigned int baud;
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unsigned int fifo_bits;
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unsigned long timeout_us = 20000;
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/* Ensure polling is not re-ordered before the prior writes/reads */
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mb();
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if (uport->private_data) {
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port = to_dev_port(uport, uport);
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baud = port->baud;
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if (!baud)
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baud = 115200;
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fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
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/*
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* Total polling iterations based on FIFO worth of bytes to be
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* sent at current baud. Add a little fluff to the wait.
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*/
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timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
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}
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/*
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* Use custom implementation instead of readl_poll_atomic since ktimer
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* is not ready at the time of early console.
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*/
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timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
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while (timeout_us) {
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reg = readl_relaxed(uport->membase + offset);
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if ((bool)(reg & field) == set)
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return true;
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udelay(10);
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timeout_us -= 10;
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}
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return false;
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}
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static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
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{
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u32 m_cmd;
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writel_relaxed(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
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m_cmd = UART_START_TX << M_OPCODE_SHFT;
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writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
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}
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static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
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{
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int done;
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u32 irq_clear = M_CMD_DONE_EN;
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done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
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M_CMD_DONE_EN, true);
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if (!done) {
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writel_relaxed(M_GENI_CMD_ABORT, uport->membase +
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SE_GENI_M_CMD_CTRL_REG);
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irq_clear |= M_CMD_ABORT_EN;
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qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
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M_CMD_ABORT_EN, true);
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}
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writel_relaxed(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
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}
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static void qcom_geni_serial_abort_rx(struct uart_port *uport)
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{
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u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
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writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
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qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
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S_GENI_CMD_ABORT, false);
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writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
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writel_relaxed(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
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}
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#ifdef CONFIG_CONSOLE_POLL
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static int qcom_geni_serial_get_char(struct uart_port *uport)
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{
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u32 rx_fifo;
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u32 status;
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status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
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writel_relaxed(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
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status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
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writel_relaxed(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
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/*
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* Ensure the writes to clear interrupts is not re-ordered after
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* reading the data.
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*/
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mb();
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status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
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if (!(status & RX_FIFO_WC_MSK))
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return NO_POLL_CHAR;
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rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
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return rx_fifo & 0xff;
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}
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static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
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unsigned char c)
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{
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struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
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writel_relaxed(port->tx_wm, uport->membase + SE_GENI_TX_WATERMARK_REG);
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qcom_geni_serial_setup_tx(uport, 1);
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WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
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M_TX_FIFO_WATERMARK_EN, true));
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writel_relaxed(c, uport->membase + SE_GENI_TX_FIFOn);
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writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
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SE_GENI_M_IRQ_CLEAR);
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qcom_geni_serial_poll_tx_done(uport);
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}
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#endif
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#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
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static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
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{
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writel_relaxed(ch, uport->membase + SE_GENI_TX_FIFOn);
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}
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static void
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__qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
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unsigned int count)
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{
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int i;
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u32 bytes_to_send = count;
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for (i = 0; i < count; i++) {
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/*
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* uart_console_write() adds a carriage return for each newline.
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* Account for additional bytes to be written.
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*/
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if (s[i] == '\n')
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bytes_to_send++;
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}
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writel_relaxed(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
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qcom_geni_serial_setup_tx(uport, bytes_to_send);
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for (i = 0; i < count; ) {
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size_t chars_to_write = 0;
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size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
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/*
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* If the WM bit never set, then the Tx state machine is not
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* in a valid state, so break, cancel/abort any existing
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* command. Unfortunately the current data being written is
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* lost.
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*/
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if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
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M_TX_FIFO_WATERMARK_EN, true))
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break;
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chars_to_write = min_t(size_t, count - i, avail / 2);
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uart_console_write(uport, s + i, chars_to_write,
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qcom_geni_serial_wr_char);
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writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
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SE_GENI_M_IRQ_CLEAR);
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i += chars_to_write;
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}
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qcom_geni_serial_poll_tx_done(uport);
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}
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static void qcom_geni_serial_console_write(struct console *co, const char *s,
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unsigned int count)
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{
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struct uart_port *uport;
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struct qcom_geni_serial_port *port;
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bool locked = true;
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unsigned long flags;
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WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
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port = get_port_from_line(co->index);
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if (IS_ERR(port))
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return;
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uport = &port->uport;
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if (oops_in_progress)
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locked = spin_trylock_irqsave(&uport->lock, flags);
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else
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spin_lock_irqsave(&uport->lock, flags);
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/* Cancel the current write to log the fault */
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if (!locked) {
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geni_se_cancel_m_cmd(&port->se);
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if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
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M_CMD_CANCEL_EN, true)) {
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geni_se_abort_m_cmd(&port->se);
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qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
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M_CMD_ABORT_EN, true);
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writel_relaxed(M_CMD_ABORT_EN, uport->membase +
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SE_GENI_M_IRQ_CLEAR);
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}
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writel_relaxed(M_CMD_CANCEL_EN, uport->membase +
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SE_GENI_M_IRQ_CLEAR);
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}
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__qcom_geni_serial_console_write(uport, s, count);
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if (locked)
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spin_unlock_irqrestore(&uport->lock, flags);
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}
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static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
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{
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u32 i;
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unsigned char buf[sizeof(u32)];
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struct tty_port *tport;
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struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
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tport = &uport->state->port;
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for (i = 0; i < bytes; ) {
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int c;
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int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
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ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
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i += chunk;
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if (drop)
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continue;
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for (c = 0; c < chunk; c++) {
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int sysrq;
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uport->icount.rx++;
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if (port->brk && buf[c] == 0) {
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port->brk = false;
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if (uart_handle_break(uport))
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continue;
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}
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sysrq = uart_handle_sysrq_char(uport, buf[c]);
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if (!sysrq)
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tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
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}
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}
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if (!drop)
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tty_flip_buffer_push(tport);
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return 0;
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}
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#else
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static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
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{
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return -EPERM;
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}
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#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
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static void qcom_geni_serial_start_tx(struct uart_port *uport)
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{
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u32 irq_en;
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struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
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u32 status;
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if (port->xfer_mode == GENI_SE_FIFO) {
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/*
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* readl ensures reading & writing of IRQ_EN register
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* is not re-ordered before checking the status of the
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* Serial Engine.
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*/
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status = readl(uport->membase + SE_GENI_STATUS);
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if (status & M_GENI_CMD_ACTIVE)
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return;
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if (!qcom_geni_serial_tx_empty(uport))
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return;
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irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
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irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
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writel_relaxed(port->tx_wm, uport->membase +
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SE_GENI_TX_WATERMARK_REG);
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writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
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}
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}
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static void qcom_geni_serial_stop_tx(struct uart_port *uport)
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{
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u32 irq_en;
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u32 status;
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struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
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irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
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irq_en &= ~M_CMD_DONE_EN;
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if (port->xfer_mode == GENI_SE_FIFO) {
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irq_en &= ~M_TX_FIFO_WATERMARK_EN;
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writel_relaxed(0, uport->membase +
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SE_GENI_TX_WATERMARK_REG);
|
|
}
|
|
writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
|
|
status = readl_relaxed(uport->membase + SE_GENI_STATUS);
|
|
/* Possible stop tx is called multiple times. */
|
|
if (!(status & M_GENI_CMD_ACTIVE))
|
|
return;
|
|
|
|
/*
|
|
* Ensure cancel command write is not re-ordered before checking
|
|
* the status of the Primary Sequencer.
|
|
*/
|
|
mb();
|
|
|
|
geni_se_cancel_m_cmd(&port->se);
|
|
if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
|
|
M_CMD_CANCEL_EN, true)) {
|
|
geni_se_abort_m_cmd(&port->se);
|
|
qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
|
|
M_CMD_ABORT_EN, true);
|
|
writel_relaxed(M_CMD_ABORT_EN, uport->membase +
|
|
SE_GENI_M_IRQ_CLEAR);
|
|
}
|
|
writel_relaxed(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
|
|
}
|
|
|
|
static void qcom_geni_serial_start_rx(struct uart_port *uport)
|
|
{
|
|
u32 irq_en;
|
|
u32 status;
|
|
struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
|
|
|
|
status = readl_relaxed(uport->membase + SE_GENI_STATUS);
|
|
if (status & S_GENI_CMD_ACTIVE)
|
|
qcom_geni_serial_stop_rx(uport);
|
|
|
|
/*
|
|
* Ensure setup command write is not re-ordered before checking
|
|
* the status of the Secondary Sequencer.
|
|
*/
|
|
mb();
|
|
|
|
geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
|
|
|
|
if (port->xfer_mode == GENI_SE_FIFO) {
|
|
irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
|
|
irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
|
|
writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
|
|
|
|
irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
|
|
irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
|
|
writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
|
|
}
|
|
}
|
|
|
|
static void qcom_geni_serial_stop_rx(struct uart_port *uport)
|
|
{
|
|
u32 irq_en;
|
|
u32 status;
|
|
struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
|
|
u32 irq_clear = S_CMD_DONE_EN;
|
|
|
|
if (port->xfer_mode == GENI_SE_FIFO) {
|
|
irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
|
|
irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
|
|
writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
|
|
|
|
irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
|
|
irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
|
|
writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
|
|
}
|
|
|
|
status = readl_relaxed(uport->membase + SE_GENI_STATUS);
|
|
/* Possible stop rx is called multiple times. */
|
|
if (!(status & S_GENI_CMD_ACTIVE))
|
|
return;
|
|
|
|
/*
|
|
* Ensure cancel command write is not re-ordered before checking
|
|
* the status of the Secondary Sequencer.
|
|
*/
|
|
mb();
|
|
|
|
geni_se_cancel_s_cmd(&port->se);
|
|
qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
|
|
S_GENI_CMD_CANCEL, false);
|
|
status = readl_relaxed(uport->membase + SE_GENI_STATUS);
|
|
writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
|
|
if (status & S_GENI_CMD_ACTIVE)
|
|
qcom_geni_serial_abort_rx(uport);
|
|
}
|
|
|
|
static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
|
|
{
|
|
u32 status;
|
|
u32 word_cnt;
|
|
u32 last_word_byte_cnt;
|
|
u32 last_word_partial;
|
|
u32 total_bytes;
|
|
struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
|
|
|
|
status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
|
|
word_cnt = status & RX_FIFO_WC_MSK;
|
|
last_word_partial = status & RX_LAST;
|
|
last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
|
|
RX_LAST_BYTE_VALID_SHFT;
|
|
|
|
if (!word_cnt)
|
|
return;
|
|
total_bytes = port->rx_bytes_pw * (word_cnt - 1);
|
|
if (last_word_partial && last_word_byte_cnt)
|
|
total_bytes += last_word_byte_cnt;
|
|
else
|
|
total_bytes += port->rx_bytes_pw;
|
|
port->handle_rx(uport, total_bytes, drop);
|
|
}
|
|
|
|
static void qcom_geni_serial_handle_tx(struct uart_port *uport)
|
|
{
|
|
struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
|
|
struct circ_buf *xmit = &uport->state->xmit;
|
|
size_t avail;
|
|
size_t remaining;
|
|
int i;
|
|
u32 status;
|
|
unsigned int chunk;
|
|
int tail;
|
|
|
|
chunk = uart_circ_chars_pending(xmit);
|
|
status = readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);
|
|
/* Both FIFO and framework buffer are drained */
|
|
if (!chunk && !status) {
|
|
qcom_geni_serial_stop_tx(uport);
|
|
goto out_write_wakeup;
|
|
}
|
|
|
|
avail = (port->tx_fifo_depth - port->tx_wm) * port->tx_bytes_pw;
|
|
tail = xmit->tail;
|
|
chunk = min3((size_t)chunk, (size_t)(UART_XMIT_SIZE - tail), avail);
|
|
if (!chunk)
|
|
goto out_write_wakeup;
|
|
|
|
qcom_geni_serial_setup_tx(uport, chunk);
|
|
|
|
remaining = chunk;
|
|
for (i = 0; i < chunk; ) {
|
|
unsigned int tx_bytes;
|
|
u8 buf[sizeof(u32)];
|
|
int c;
|
|
|
|
memset(buf, 0, ARRAY_SIZE(buf));
|
|
tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
|
|
for (c = 0; c < tx_bytes ; c++)
|
|
buf[c] = xmit->buf[tail + c];
|
|
|
|
iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
|
|
|
|
i += tx_bytes;
|
|
tail += tx_bytes;
|
|
uport->icount.tx += tx_bytes;
|
|
remaining -= tx_bytes;
|
|
}
|
|
|
|
xmit->tail = tail & (UART_XMIT_SIZE - 1);
|
|
qcom_geni_serial_poll_tx_done(uport);
|
|
out_write_wakeup:
|
|
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
|
uart_write_wakeup(uport);
|
|
}
|
|
|
|
static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
|
|
{
|
|
unsigned int m_irq_status;
|
|
unsigned int s_irq_status;
|
|
struct uart_port *uport = dev;
|
|
unsigned long flags;
|
|
unsigned int m_irq_en;
|
|
bool drop_rx = false;
|
|
struct tty_port *tport = &uport->state->port;
|
|
struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
|
|
|
|
if (uport->suspended)
|
|
return IRQ_NONE;
|
|
|
|
spin_lock_irqsave(&uport->lock, flags);
|
|
m_irq_status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
|
|
s_irq_status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
|
|
m_irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
|
|
writel_relaxed(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
|
|
writel_relaxed(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
|
|
|
|
if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
|
|
goto out_unlock;
|
|
|
|
if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
|
|
uport->icount.overrun++;
|
|
tty_insert_flip_char(tport, 0, TTY_OVERRUN);
|
|
}
|
|
|
|
if (m_irq_status & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN) &&
|
|
m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
|
|
qcom_geni_serial_handle_tx(uport);
|
|
|
|
if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
|
|
if (s_irq_status & S_GP_IRQ_0_EN)
|
|
uport->icount.parity++;
|
|
drop_rx = true;
|
|
} else if (s_irq_status & S_GP_IRQ_2_EN ||
|
|
s_irq_status & S_GP_IRQ_3_EN) {
|
|
uport->icount.brk++;
|
|
port->brk = true;
|
|
}
|
|
|
|
if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
|
|
s_irq_status & S_RX_FIFO_LAST_EN)
|
|
qcom_geni_serial_handle_rx(uport, drop_rx);
|
|
|
|
out_unlock:
|
|
spin_unlock_irqrestore(&uport->lock, flags);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
|
|
{
|
|
struct uart_port *uport;
|
|
|
|
uport = &port->uport;
|
|
port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
|
|
port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
|
|
port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
|
|
uport->fifosize =
|
|
(port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
|
|
}
|
|
|
|
static void set_rfr_wm(struct qcom_geni_serial_port *port)
|
|
{
|
|
/*
|
|
* Set RFR (Flow off) to FIFO_DEPTH - 2.
|
|
* RX WM level at 10% RX_FIFO_DEPTH.
|
|
* TX WM level at 10% TX_FIFO_DEPTH.
|
|
*/
|
|
port->rx_rfr = port->rx_fifo_depth - 2;
|
|
port->rx_wm = UART_CONSOLE_RX_WM;
|
|
port->tx_wm = DEF_TX_WM;
|
|
}
|
|
|
|
static void qcom_geni_serial_shutdown(struct uart_port *uport)
|
|
{
|
|
unsigned long flags;
|
|
|
|
/* Stop the console before stopping the current tx */
|
|
console_stop(uport->cons);
|
|
|
|
free_irq(uport->irq, uport);
|
|
spin_lock_irqsave(&uport->lock, flags);
|
|
qcom_geni_serial_stop_tx(uport);
|
|
qcom_geni_serial_stop_rx(uport);
|
|
spin_unlock_irqrestore(&uport->lock, flags);
|
|
}
|
|
|
|
static int qcom_geni_serial_port_setup(struct uart_port *uport)
|
|
{
|
|
struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
|
|
unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
|
|
|
|
set_rfr_wm(port);
|
|
writel_relaxed(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
|
|
/*
|
|
* Make an unconditional cancel on the main sequencer to reset
|
|
* it else we could end up in data loss scenarios.
|
|
*/
|
|
port->xfer_mode = GENI_SE_FIFO;
|
|
qcom_geni_serial_poll_tx_done(uport);
|
|
geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
|
|
false, true, false);
|
|
geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
|
|
false, false, true);
|
|
geni_se_init(&port->se, port->rx_wm, port->rx_rfr);
|
|
geni_se_select_mode(&port->se, port->xfer_mode);
|
|
port->setup = true;
|
|
return 0;
|
|
}
|
|
|
|
static int qcom_geni_serial_startup(struct uart_port *uport)
|
|
{
|
|
int ret;
|
|
u32 proto;
|
|
struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
|
|
|
|
scnprintf(port->name, sizeof(port->name),
|
|
"qcom_serial_geni%d", uport->line);
|
|
|
|
proto = geni_se_read_proto(&port->se);
|
|
if (proto != GENI_SE_UART) {
|
|
dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
|
|
return -ENXIO;
|
|
}
|
|
|
|
get_tx_fifo_size(port);
|
|
if (!port->setup) {
|
|
ret = qcom_geni_serial_port_setup(uport);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
|
|
port->name, uport);
|
|
if (ret)
|
|
dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
static unsigned long get_clk_cfg(unsigned long clk_freq)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
|
|
if (!(root_freq[i] % clk_freq))
|
|
return root_freq[i];
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div)
|
|
{
|
|
unsigned long ser_clk;
|
|
unsigned long desired_clk;
|
|
|
|
desired_clk = baud * UART_OVERSAMPLING;
|
|
ser_clk = get_clk_cfg(desired_clk);
|
|
if (!ser_clk) {
|
|
pr_err("%s: Can't find matching DFS entry for baud %d\n",
|
|
__func__, baud);
|
|
return ser_clk;
|
|
}
|
|
|
|
*clk_div = ser_clk / desired_clk;
|
|
return ser_clk;
|
|
}
|
|
|
|
static void qcom_geni_serial_set_termios(struct uart_port *uport,
|
|
struct ktermios *termios, struct ktermios *old)
|
|
{
|
|
unsigned int baud;
|
|
unsigned int bits_per_char;
|
|
unsigned int tx_trans_cfg;
|
|
unsigned int tx_parity_cfg;
|
|
unsigned int rx_trans_cfg;
|
|
unsigned int rx_parity_cfg;
|
|
unsigned int stop_bit_len;
|
|
unsigned int clk_div;
|
|
unsigned long ser_clk_cfg;
|
|
struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
|
|
unsigned long clk_rate;
|
|
|
|
qcom_geni_serial_stop_rx(uport);
|
|
/* baud rate */
|
|
baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
|
|
port->baud = baud;
|
|
clk_rate = get_clk_div_rate(baud, &clk_div);
|
|
if (!clk_rate)
|
|
goto out_restart_rx;
|
|
|
|
uport->uartclk = clk_rate;
|
|
clk_set_rate(port->se.clk, clk_rate);
|
|
ser_clk_cfg = SER_CLK_EN;
|
|
ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
|
|
|
|
/* parity */
|
|
tx_trans_cfg = readl_relaxed(uport->membase + SE_UART_TX_TRANS_CFG);
|
|
tx_parity_cfg = readl_relaxed(uport->membase + SE_UART_TX_PARITY_CFG);
|
|
rx_trans_cfg = readl_relaxed(uport->membase + SE_UART_RX_TRANS_CFG);
|
|
rx_parity_cfg = readl_relaxed(uport->membase + SE_UART_RX_PARITY_CFG);
|
|
if (termios->c_cflag & PARENB) {
|
|
tx_trans_cfg |= UART_TX_PAR_EN;
|
|
rx_trans_cfg |= UART_RX_PAR_EN;
|
|
tx_parity_cfg |= PAR_CALC_EN;
|
|
rx_parity_cfg |= PAR_CALC_EN;
|
|
if (termios->c_cflag & PARODD) {
|
|
tx_parity_cfg |= PAR_ODD;
|
|
rx_parity_cfg |= PAR_ODD;
|
|
} else if (termios->c_cflag & CMSPAR) {
|
|
tx_parity_cfg |= PAR_SPACE;
|
|
rx_parity_cfg |= PAR_SPACE;
|
|
} else {
|
|
tx_parity_cfg |= PAR_EVEN;
|
|
rx_parity_cfg |= PAR_EVEN;
|
|
}
|
|
} else {
|
|
tx_trans_cfg &= ~UART_TX_PAR_EN;
|
|
rx_trans_cfg &= ~UART_RX_PAR_EN;
|
|
tx_parity_cfg &= ~PAR_CALC_EN;
|
|
rx_parity_cfg &= ~PAR_CALC_EN;
|
|
}
|
|
|
|
/* bits per char */
|
|
switch (termios->c_cflag & CSIZE) {
|
|
case CS5:
|
|
bits_per_char = 5;
|
|
break;
|
|
case CS6:
|
|
bits_per_char = 6;
|
|
break;
|
|
case CS7:
|
|
bits_per_char = 7;
|
|
break;
|
|
case CS8:
|
|
default:
|
|
bits_per_char = 8;
|
|
break;
|
|
}
|
|
|
|
/* stop bits */
|
|
if (termios->c_cflag & CSTOPB)
|
|
stop_bit_len = TX_STOP_BIT_LEN_2;
|
|
else
|
|
stop_bit_len = TX_STOP_BIT_LEN_1;
|
|
|
|
/* flow control, clear the CTS_MASK bit if using flow control. */
|
|
if (termios->c_cflag & CRTSCTS)
|
|
tx_trans_cfg &= ~UART_CTS_MASK;
|
|
else
|
|
tx_trans_cfg |= UART_CTS_MASK;
|
|
|
|
if (baud)
|
|
uart_update_timeout(uport, termios->c_cflag, baud);
|
|
|
|
writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
|
|
writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
|
|
writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
|
|
writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
|
|
writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
|
|
writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
|
|
writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
|
|
writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
|
|
writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
|
|
out_restart_rx:
|
|
qcom_geni_serial_start_rx(uport);
|
|
}
|
|
|
|
static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
|
|
{
|
|
return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
|
|
}
|
|
|
|
#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
|
|
static int __init qcom_geni_console_setup(struct console *co, char *options)
|
|
{
|
|
struct uart_port *uport;
|
|
struct qcom_geni_serial_port *port;
|
|
int baud;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
|
|
if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
|
|
return -ENXIO;
|
|
|
|
port = get_port_from_line(co->index);
|
|
if (IS_ERR(port)) {
|
|
pr_err("Invalid line %d\n", co->index);
|
|
return PTR_ERR(port);
|
|
}
|
|
|
|
uport = &port->uport;
|
|
|
|
if (unlikely(!uport->membase))
|
|
return -ENXIO;
|
|
|
|
if (geni_se_resources_on(&port->se)) {
|
|
dev_err(port->se.dev, "Error turning on resources\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
if (unlikely(geni_se_read_proto(&port->se) != GENI_SE_UART)) {
|
|
geni_se_resources_off(&port->se);
|
|
return -ENXIO;
|
|
}
|
|
|
|
if (!port->setup) {
|
|
port->tx_bytes_pw = 1;
|
|
port->rx_bytes_pw = RX_BYTES_PW;
|
|
qcom_geni_serial_stop_rx(uport);
|
|
qcom_geni_serial_port_setup(uport);
|
|
}
|
|
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
|
|
return uart_set_options(uport, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static void qcom_geni_serial_earlycon_write(struct console *con,
|
|
const char *s, unsigned int n)
|
|
{
|
|
struct earlycon_device *dev = con->data;
|
|
|
|
__qcom_geni_serial_console_write(&dev->port, s, n);
|
|
}
|
|
|
|
static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
|
|
const char *opt)
|
|
{
|
|
struct uart_port *uport = &dev->port;
|
|
u32 tx_trans_cfg;
|
|
u32 tx_parity_cfg = 0; /* Disable Tx Parity */
|
|
u32 rx_trans_cfg = 0;
|
|
u32 rx_parity_cfg = 0; /* Disable Rx Parity */
|
|
u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
|
|
u32 bits_per_char;
|
|
struct geni_se se;
|
|
|
|
if (!uport->membase)
|
|
return -EINVAL;
|
|
|
|
memset(&se, 0, sizeof(se));
|
|
se.base = uport->membase;
|
|
if (geni_se_read_proto(&se) != GENI_SE_UART)
|
|
return -ENXIO;
|
|
/*
|
|
* Ignore Flow control.
|
|
* n = 8.
|
|
*/
|
|
tx_trans_cfg = UART_CTS_MASK;
|
|
bits_per_char = BITS_PER_BYTE;
|
|
|
|
/*
|
|
* Make an unconditional cancel on the main sequencer to reset
|
|
* it else we could end up in data loss scenarios.
|
|
*/
|
|
qcom_geni_serial_poll_tx_done(uport);
|
|
qcom_geni_serial_abort_rx(uport);
|
|
geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
|
|
geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
|
|
geni_se_select_mode(&se, GENI_SE_FIFO);
|
|
|
|
writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
|
|
writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
|
|
writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
|
|
writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
|
|
writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
|
|
writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
|
|
writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
|
|
|
|
dev->con->write = qcom_geni_serial_earlycon_write;
|
|
dev->con->setup = NULL;
|
|
return 0;
|
|
}
|
|
OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
|
|
qcom_geni_serial_earlycon_setup);
|
|
|
|
static int __init console_register(struct uart_driver *drv)
|
|
{
|
|
return uart_register_driver(drv);
|
|
}
|
|
|
|
static void console_unregister(struct uart_driver *drv)
|
|
{
|
|
uart_unregister_driver(drv);
|
|
}
|
|
|
|
static struct console cons_ops = {
|
|
.name = "ttyMSM",
|
|
.write = qcom_geni_serial_console_write,
|
|
.device = uart_console_device,
|
|
.setup = qcom_geni_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.data = &qcom_geni_console_driver,
|
|
};
|
|
|
|
static struct uart_driver qcom_geni_console_driver = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = "qcom_geni_console",
|
|
.dev_name = "ttyMSM",
|
|
.nr = GENI_UART_CONS_PORTS,
|
|
.cons = &cons_ops,
|
|
};
|
|
#else
|
|
static int console_register(struct uart_driver *drv)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static void console_unregister(struct uart_driver *drv)
|
|
{
|
|
}
|
|
#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
|
|
|
|
static void qcom_geni_serial_cons_pm(struct uart_port *uport,
|
|
unsigned int new_state, unsigned int old_state)
|
|
{
|
|
struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
|
|
|
|
if (unlikely(!uart_console(uport)))
|
|
return;
|
|
|
|
if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
|
|
geni_se_resources_on(&port->se);
|
|
else if (new_state == UART_PM_STATE_OFF &&
|
|
old_state == UART_PM_STATE_ON)
|
|
geni_se_resources_off(&port->se);
|
|
}
|
|
|
|
static const struct uart_ops qcom_geni_console_pops = {
|
|
.tx_empty = qcom_geni_serial_tx_empty,
|
|
.stop_tx = qcom_geni_serial_stop_tx,
|
|
.start_tx = qcom_geni_serial_start_tx,
|
|
.stop_rx = qcom_geni_serial_stop_rx,
|
|
.set_termios = qcom_geni_serial_set_termios,
|
|
.startup = qcom_geni_serial_startup,
|
|
.request_port = qcom_geni_serial_request_port,
|
|
.config_port = qcom_geni_serial_config_port,
|
|
.shutdown = qcom_geni_serial_shutdown,
|
|
.type = qcom_geni_serial_get_type,
|
|
.set_mctrl = qcom_geni_cons_set_mctrl,
|
|
.get_mctrl = qcom_geni_cons_get_mctrl,
|
|
#ifdef CONFIG_CONSOLE_POLL
|
|
.poll_get_char = qcom_geni_serial_get_char,
|
|
.poll_put_char = qcom_geni_serial_poll_put_char,
|
|
#endif
|
|
.pm = qcom_geni_serial_cons_pm,
|
|
};
|
|
|
|
static int qcom_geni_serial_probe(struct platform_device *pdev)
|
|
{
|
|
int ret = 0;
|
|
int line = -1;
|
|
struct qcom_geni_serial_port *port;
|
|
struct uart_port *uport;
|
|
struct resource *res;
|
|
int irq;
|
|
|
|
if (pdev->dev.of_node)
|
|
line = of_alias_get_id(pdev->dev.of_node, "serial");
|
|
|
|
if (line < 0 || line >= GENI_UART_CONS_PORTS)
|
|
return -ENXIO;
|
|
port = get_port_from_line(line);
|
|
if (IS_ERR(port)) {
|
|
dev_err(&pdev->dev, "Invalid line %d\n", line);
|
|
return PTR_ERR(port);
|
|
}
|
|
|
|
uport = &port->uport;
|
|
/* Don't allow 2 drivers to access the same port */
|
|
if (uport->private_data)
|
|
return -ENODEV;
|
|
|
|
uport->dev = &pdev->dev;
|
|
port->se.dev = &pdev->dev;
|
|
port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
|
|
port->se.clk = devm_clk_get(&pdev->dev, "se");
|
|
if (IS_ERR(port->se.clk)) {
|
|
ret = PTR_ERR(port->se.clk);
|
|
dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res)
|
|
return -EINVAL;
|
|
uport->mapbase = res->start;
|
|
|
|
port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
|
|
port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
|
|
port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "Failed to get IRQ %d\n", irq);
|
|
return irq;
|
|
}
|
|
uport->irq = irq;
|
|
|
|
uport->private_data = &qcom_geni_console_driver;
|
|
platform_set_drvdata(pdev, port);
|
|
port->handle_rx = handle_rx_console;
|
|
return uart_add_one_port(&qcom_geni_console_driver, uport);
|
|
}
|
|
|
|
static int qcom_geni_serial_remove(struct platform_device *pdev)
|
|
{
|
|
struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
|
|
struct uart_driver *drv = port->uport.private_data;
|
|
|
|
uart_remove_one_port(drv, &port->uport);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused qcom_geni_serial_sys_suspend_noirq(struct device *dev)
|
|
{
|
|
struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
|
|
struct uart_port *uport = &port->uport;
|
|
|
|
uart_suspend_port(uport->private_data, uport);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused qcom_geni_serial_sys_resume_noirq(struct device *dev)
|
|
{
|
|
struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
|
|
struct uart_port *uport = &port->uport;
|
|
|
|
if (console_suspend_enabled && uport->suspended) {
|
|
uart_resume_port(uport->private_data, uport);
|
|
/*
|
|
* uart_suspend_port() invokes port shutdown which in turn
|
|
* frees the irq. uart_resume_port invokes port startup which
|
|
* performs request_irq. The request_irq auto-enables the IRQ.
|
|
* In addition, resume_noirq implicitly enables the IRQ and
|
|
* leads to an unbalanced IRQ enable warning. Disable the IRQ
|
|
* before returning so that the warning is suppressed.
|
|
*/
|
|
disable_irq(uport->irq);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
|
|
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend_noirq,
|
|
qcom_geni_serial_sys_resume_noirq)
|
|
};
|
|
|
|
static const struct of_device_id qcom_geni_serial_match_table[] = {
|
|
{ .compatible = "qcom,geni-debug-uart", },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
|
|
|
|
static struct platform_driver qcom_geni_serial_platform_driver = {
|
|
.remove = qcom_geni_serial_remove,
|
|
.probe = qcom_geni_serial_probe,
|
|
.driver = {
|
|
.name = "qcom_geni_serial",
|
|
.of_match_table = qcom_geni_serial_match_table,
|
|
.pm = &qcom_geni_serial_pm_ops,
|
|
},
|
|
};
|
|
|
|
static int __init qcom_geni_serial_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = console_register(&qcom_geni_console_driver);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = platform_driver_register(&qcom_geni_serial_platform_driver);
|
|
if (ret)
|
|
console_unregister(&qcom_geni_console_driver);
|
|
return ret;
|
|
}
|
|
module_init(qcom_geni_serial_init);
|
|
|
|
static void __exit qcom_geni_serial_exit(void)
|
|
{
|
|
platform_driver_unregister(&qcom_geni_serial_platform_driver);
|
|
console_unregister(&qcom_geni_console_driver);
|
|
}
|
|
module_exit(qcom_geni_serial_exit);
|
|
|
|
MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
|
|
MODULE_LICENSE("GPL v2");
|