mirror of https://gitee.com/openkylin/linux.git
411 lines
10 KiB
C
411 lines
10 KiB
C
/*
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* horus3a.h
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*
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* Sony Horus3A DVB-S/S2 tuner driver
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*
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* Copyright 2012 Sony Corporation
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* Copyright (C) 2014 NetUP Inc.
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* Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
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* Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/dvb/frontend.h>
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#include <linux/types.h>
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#include "horus3a.h"
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#include "dvb_frontend.h"
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#define MAX_WRITE_REGSIZE 5
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enum horus3a_state {
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STATE_UNKNOWN,
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STATE_SLEEP,
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STATE_ACTIVE
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};
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struct horus3a_priv {
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u32 frequency;
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u8 i2c_address;
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struct i2c_adapter *i2c;
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enum horus3a_state state;
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void *set_tuner_data;
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int (*set_tuner)(void *, int);
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};
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static void horus3a_i2c_debug(struct horus3a_priv *priv,
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u8 reg, u8 write, const u8 *data, u32 len)
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{
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dev_dbg(&priv->i2c->dev, "horus3a: I2C %s reg 0x%02x size %d\n",
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(write == 0 ? "read" : "write"), reg, len);
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print_hex_dump_bytes("horus3a: I2C data: ",
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DUMP_PREFIX_OFFSET, data, len);
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}
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static int horus3a_write_regs(struct horus3a_priv *priv,
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u8 reg, const u8 *data, u32 len)
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{
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int ret;
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u8 buf[MAX_WRITE_REGSIZE + 1];
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struct i2c_msg msg[1] = {
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{
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.addr = priv->i2c_address,
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.flags = 0,
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.len = len + 1,
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.buf = buf,
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}
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};
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if (len + 1 > sizeof(buf)) {
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dev_warn(&priv->i2c->dev,"wr reg=%04x: len=%d is too big!\n",
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reg, len + 1);
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return -E2BIG;
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}
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horus3a_i2c_debug(priv, reg, 1, data, len);
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buf[0] = reg;
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memcpy(&buf[1], data, len);
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ret = i2c_transfer(priv->i2c, msg, 1);
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if (ret >= 0 && ret != 1)
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ret = -EREMOTEIO;
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if (ret < 0) {
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dev_warn(&priv->i2c->dev,
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"%s: i2c wr failed=%d reg=%02x len=%d\n",
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KBUILD_MODNAME, ret, reg, len);
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return ret;
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}
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return 0;
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}
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static int horus3a_write_reg(struct horus3a_priv *priv, u8 reg, u8 val)
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{
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return horus3a_write_regs(priv, reg, &val, 1);
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}
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static int horus3a_enter_power_save(struct horus3a_priv *priv)
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{
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u8 data[2];
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dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
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if (priv->state == STATE_SLEEP)
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return 0;
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/* IQ Generator disable */
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horus3a_write_reg(priv, 0x2a, 0x79);
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/* MDIV_EN = 0 */
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horus3a_write_reg(priv, 0x29, 0x70);
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/* VCO disable preparation */
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horus3a_write_reg(priv, 0x28, 0x3e);
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/* VCO buffer disable */
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horus3a_write_reg(priv, 0x2a, 0x19);
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/* VCO calibration disable */
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horus3a_write_reg(priv, 0x1c, 0x00);
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/* Power save setting (xtal is not stopped) */
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data[0] = 0xC0;
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/* LNA is Disabled */
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data[1] = 0xA7;
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/* 0x11 - 0x12 */
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horus3a_write_regs(priv, 0x11, data, sizeof(data));
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priv->state = STATE_SLEEP;
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return 0;
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}
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static int horus3a_leave_power_save(struct horus3a_priv *priv)
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{
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u8 data[2];
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dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
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if (priv->state == STATE_ACTIVE)
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return 0;
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/* Leave power save */
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data[0] = 0x00;
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/* LNA is Disabled */
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data[1] = 0xa7;
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/* 0x11 - 0x12 */
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horus3a_write_regs(priv, 0x11, data, sizeof(data));
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/* VCO buffer enable */
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horus3a_write_reg(priv, 0x2a, 0x79);
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/* VCO calibration enable */
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horus3a_write_reg(priv, 0x1c, 0xc0);
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/* MDIV_EN = 1 */
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horus3a_write_reg(priv, 0x29, 0x71);
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usleep_range(5000, 7000);
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priv->state = STATE_ACTIVE;
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return 0;
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}
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static int horus3a_init(struct dvb_frontend *fe)
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{
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struct horus3a_priv *priv = fe->tuner_priv;
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dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
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return 0;
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}
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static int horus3a_release(struct dvb_frontend *fe)
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{
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struct horus3a_priv *priv = fe->tuner_priv;
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dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
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kfree(fe->tuner_priv);
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fe->tuner_priv = NULL;
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return 0;
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}
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static int horus3a_sleep(struct dvb_frontend *fe)
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{
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struct horus3a_priv *priv = fe->tuner_priv;
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dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
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horus3a_enter_power_save(priv);
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return 0;
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}
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static int horus3a_set_params(struct dvb_frontend *fe)
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{
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struct dtv_frontend_properties *p = &fe->dtv_property_cache;
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struct horus3a_priv *priv = fe->tuner_priv;
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u32 frequency = p->frequency;
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u32 symbol_rate = p->symbol_rate/1000;
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u8 mixdiv = 0;
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u8 mdiv = 0;
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u32 ms = 0;
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u8 f_ctl = 0;
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u8 g_ctl = 0;
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u8 fc_lpf = 0;
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u8 data[5];
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dev_dbg(&priv->i2c->dev, "%s(): frequency %dkHz symbol_rate %dksps\n",
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__func__, frequency, symbol_rate);
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if (priv->set_tuner)
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priv->set_tuner(priv->set_tuner_data, 0);
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if (priv->state == STATE_SLEEP)
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horus3a_leave_power_save(priv);
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/* frequency should be X MHz (X : integer) */
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frequency = DIV_ROUND_CLOSEST(frequency, 1000) * 1000;
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if (frequency <= 1155000) {
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mixdiv = 4;
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mdiv = 1;
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} else {
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mixdiv = 2;
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mdiv = 0;
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}
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/* Assumed that fREF == 1MHz (1000kHz) */
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ms = DIV_ROUND_CLOSEST((frequency * mixdiv) / 2, 1000);
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if (ms > 0x7FFF) { /* 15 bit */
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dev_err(&priv->i2c->dev, "horus3a: invalid frequency %d\n",
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frequency);
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return -EINVAL;
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}
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if (frequency < 975000) {
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/* F_CTL=11100 G_CTL=001 */
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f_ctl = 0x1C;
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g_ctl = 0x01;
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} else if (frequency < 1050000) {
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/* F_CTL=11000 G_CTL=010 */
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f_ctl = 0x18;
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g_ctl = 0x02;
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} else if (frequency < 1150000) {
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/* F_CTL=10100 G_CTL=010 */
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f_ctl = 0x14;
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g_ctl = 0x02;
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} else if (frequency < 1250000) {
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/* F_CTL=10000 G_CTL=011 */
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f_ctl = 0x10;
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g_ctl = 0x03;
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} else if (frequency < 1350000) {
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/* F_CTL=01100 G_CTL=100 */
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f_ctl = 0x0C;
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g_ctl = 0x04;
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} else if (frequency < 1450000) {
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/* F_CTL=01010 G_CTL=100 */
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f_ctl = 0x0A;
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g_ctl = 0x04;
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} else if (frequency < 1600000) {
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/* F_CTL=00111 G_CTL=101 */
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f_ctl = 0x07;
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g_ctl = 0x05;
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} else if (frequency < 1800000) {
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/* F_CTL=00100 G_CTL=010 */
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f_ctl = 0x04;
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g_ctl = 0x02;
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} else if (frequency < 2000000) {
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/* F_CTL=00010 G_CTL=001 */
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f_ctl = 0x02;
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g_ctl = 0x01;
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} else {
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/* F_CTL=00000 G_CTL=000 */
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f_ctl = 0x00;
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g_ctl = 0x00;
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}
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/* LPF cutoff frequency setting */
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if (p->delivery_system == SYS_DVBS) {
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/*
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* rolloff = 0.35
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* SR <= 4.3
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* fc_lpf = 5
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* 4.3 < SR <= 10
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* fc_lpf = SR * (1 + rolloff) / 2 + SR / 2 =
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* SR * 1.175 = SR * (47/40)
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* 10 < SR
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* fc_lpf = SR * (1 + rolloff) / 2 + 5 =
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* SR * 0.675 + 5 = SR * (27/40) + 5
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* NOTE: The result should be round up.
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*/
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if (symbol_rate <= 4300)
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fc_lpf = 5;
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else if (symbol_rate <= 10000)
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fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 47, 40000);
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else
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fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 27, 40000) + 5;
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/* 5 <= fc_lpf <= 36 */
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if (fc_lpf > 36)
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fc_lpf = 36;
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} else if (p->delivery_system == SYS_DVBS2) {
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/*
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* SR <= 4.5:
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* fc_lpf = 5
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* 4.5 < SR <= 10:
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* fc_lpf = SR * (1 + rolloff) / 2 + SR / 2
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* 10 < SR:
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* fc_lpf = SR * (1 + rolloff) / 2 + 5
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* NOTE: The result should be round up.
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*/
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if (symbol_rate <= 4500)
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fc_lpf = 5;
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else if (symbol_rate <= 10000)
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fc_lpf = (u8)((symbol_rate * 11 + (10000-1)) / 10000);
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else
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fc_lpf = (u8)((symbol_rate * 3 + (5000-1)) / 5000 + 5);
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/* 5 <= fc_lpf <= 36 is valid */
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if (fc_lpf > 36)
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fc_lpf = 36;
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} else {
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dev_err(&priv->i2c->dev,
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"horus3a: invalid delivery system %d\n",
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p->delivery_system);
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return -EINVAL;
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}
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/* 0x00 - 0x04 */
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data[0] = (u8)((ms >> 7) & 0xFF);
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data[1] = (u8)((ms << 1) & 0xFF);
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data[2] = 0x00;
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data[3] = 0x00;
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data[4] = (u8)(mdiv << 7);
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horus3a_write_regs(priv, 0x00, data, sizeof(data));
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/* Write G_CTL, F_CTL */
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horus3a_write_reg(priv, 0x09, (u8)((g_ctl << 5) | f_ctl));
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/* Write LPF cutoff frequency */
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horus3a_write_reg(priv, 0x37, (u8)(0x80 | (fc_lpf << 1)));
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/* Start Calibration */
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horus3a_write_reg(priv, 0x05, 0x80);
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/* IQ Generator enable */
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horus3a_write_reg(priv, 0x2a, 0x7b);
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/* tuner stabilization time */
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msleep(60);
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/* Store tuned frequency to the struct */
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priv->frequency = ms * 2 * 1000 / mixdiv;
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return 0;
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}
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static int horus3a_get_frequency(struct dvb_frontend *fe, u32 *frequency)
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{
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struct horus3a_priv *priv = fe->tuner_priv;
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*frequency = priv->frequency;
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return 0;
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}
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static const struct dvb_tuner_ops horus3a_tuner_ops = {
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.info = {
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.name = "Sony Horus3a",
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.frequency_min = 950000,
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.frequency_max = 2150000,
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.frequency_step = 1000,
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},
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.init = horus3a_init,
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.release = horus3a_release,
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.sleep = horus3a_sleep,
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.set_params = horus3a_set_params,
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.get_frequency = horus3a_get_frequency,
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};
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struct dvb_frontend *horus3a_attach(struct dvb_frontend *fe,
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const struct horus3a_config *config,
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struct i2c_adapter *i2c)
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{
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u8 buf[3], val;
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struct horus3a_priv *priv = NULL;
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priv = kzalloc(sizeof(struct horus3a_priv), GFP_KERNEL);
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if (priv == NULL)
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return NULL;
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priv->i2c_address = (config->i2c_address >> 1);
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priv->i2c = i2c;
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priv->set_tuner_data = config->set_tuner_priv;
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priv->set_tuner = config->set_tuner_callback;
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1);
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/* wait 4ms after power on */
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usleep_range(4000, 6000);
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/* IQ Generator disable */
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horus3a_write_reg(priv, 0x2a, 0x79);
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/* REF_R = Xtal Frequency */
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buf[0] = config->xtal_freq_mhz;
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buf[1] = config->xtal_freq_mhz;
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buf[2] = 0;
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/* 0x6 - 0x8 */
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horus3a_write_regs(priv, 0x6, buf, 3);
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/* IQ Out = Single Ended */
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horus3a_write_reg(priv, 0x0a, 0x40);
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switch (config->xtal_freq_mhz) {
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case 27:
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val = 0x1f;
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break;
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case 24:
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val = 0x10;
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break;
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case 16:
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val = 0xc;
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break;
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default:
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val = 0;
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dev_warn(&priv->i2c->dev,
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"horus3a: invalid xtal frequency %dMHz\n",
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config->xtal_freq_mhz);
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break;
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}
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val <<= 2;
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horus3a_write_reg(priv, 0x0e, val);
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horus3a_enter_power_save(priv);
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usleep_range(3000, 5000);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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memcpy(&fe->ops.tuner_ops, &horus3a_tuner_ops,
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sizeof(struct dvb_tuner_ops));
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fe->tuner_priv = priv;
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dev_info(&priv->i2c->dev,
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"Sony HORUS3A attached on addr=%x at I2C adapter %p\n",
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priv->i2c_address, priv->i2c);
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return fe;
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}
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EXPORT_SYMBOL(horus3a_attach);
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MODULE_DESCRIPTION("Sony HORUS3A sattelite tuner driver");
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MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>");
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MODULE_LICENSE("GPL");
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