mirror of https://gitee.com/openkylin/linux.git
208 lines
4.9 KiB
C
208 lines
4.9 KiB
C
/*
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* Low level TLB handling.
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*
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* Copyright (C) 2000-2003, Axis Communications AB.
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*
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* Authors: Bjorn Wesen <bjornw@axis.com>
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* Tobias Anderberg <tobiasa@axis.com>, CRISv32 port.
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*/
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#include <asm/tlb.h>
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#include <asm/mmu_context.h>
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#include <asm/arch/hwregs/asm/mmu_defs_asm.h>
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#include <asm/arch/hwregs/supp_reg.h>
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#define UPDATE_TLB_SEL_IDX(val) \
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do { \
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unsigned long tlb_sel; \
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\
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tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, val); \
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SUPP_REG_WR(RW_MM_TLB_SEL, tlb_sel); \
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} while(0)
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#define UPDATE_TLB_HILO(tlb_hi, tlb_lo) \
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do { \
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SUPP_REG_WR(RW_MM_TLB_HI, tlb_hi); \
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SUPP_REG_WR(RW_MM_TLB_LO, tlb_lo); \
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} while(0)
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/*
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* The TLB can host up to 256 different mm contexts at the same time. The running
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* context is found in the PID register. Each TLB entry contains a page_id that
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* has to match the PID register to give a hit. page_id_map keeps track of which
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* mm's is assigned to which page_id's, making sure it's known when to
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* invalidate TLB entries.
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*
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* The last page_id is never running, it is used as an invalid page_id so that
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* it's possible to make TLB entries that will nerver match.
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*
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* Note; the flushes needs to be atomic otherwise an interrupt hander that uses
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* vmalloc'ed memory might cause a TLB load in the middle of a flush.
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*/
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/* Flush all TLB entries. */
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void
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__flush_tlb_all(void)
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{
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int i;
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int mmu;
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unsigned long flags;
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unsigned long mmu_tlb_hi;
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unsigned long mmu_tlb_sel;
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/*
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* Mask with 0xf so similar TLB entries aren't written in the same 4-way
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* entry group.
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*/
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local_irq_save(flags);
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for (mmu = 1; mmu <= 2; mmu++) {
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SUPP_BANK_SEL(mmu); /* Select the MMU */
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for (i = 0; i < NUM_TLB_ENTRIES; i++) {
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/* Store invalid entry */
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mmu_tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, i);
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mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid, INVALID_PAGEID)
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| REG_FIELD(mmu, rw_mm_tlb_hi, vpn, i & 0xf));
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SUPP_REG_WR(RW_MM_TLB_SEL, mmu_tlb_sel);
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SUPP_REG_WR(RW_MM_TLB_HI, mmu_tlb_hi);
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SUPP_REG_WR(RW_MM_TLB_LO, 0);
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}
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}
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local_irq_restore(flags);
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}
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/* Flush an entire user address space. */
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void
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__flush_tlb_mm(struct mm_struct *mm)
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{
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int i;
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int mmu;
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unsigned long flags;
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unsigned long page_id;
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unsigned long tlb_hi;
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unsigned long mmu_tlb_hi;
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page_id = mm->context.page_id;
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if (page_id == NO_CONTEXT)
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return;
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/* Mark the TLB entries that match the page_id as invalid. */
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local_irq_save(flags);
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for (mmu = 1; mmu <= 2; mmu++) {
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SUPP_BANK_SEL(mmu);
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for (i = 0; i < NUM_TLB_ENTRIES; i++) {
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UPDATE_TLB_SEL_IDX(i);
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/* Get the page_id */
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SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi);
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/* Check if the page_id match. */
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if ((tlb_hi & 0xff) == page_id) {
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mmu_tlb_hi = (REG_FIELD(mmu, rw_mm_tlb_hi, pid,
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INVALID_PAGEID)
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| REG_FIELD(mmu, rw_mm_tlb_hi, vpn,
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i & 0xf));
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UPDATE_TLB_HILO(mmu_tlb_hi, 0);
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}
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}
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}
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local_irq_restore(flags);
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}
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/* Invalidate a single page. */
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void
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__flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
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{
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int i;
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int mmu;
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unsigned long page_id;
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unsigned long flags;
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unsigned long tlb_hi;
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unsigned long mmu_tlb_hi;
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page_id = vma->vm_mm->context.page_id;
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if (page_id == NO_CONTEXT)
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return;
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addr &= PAGE_MASK;
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/*
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* Invalidate those TLB entries that match both the mm context and the
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* requested virtual address.
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*/
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local_irq_save(flags);
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for (mmu = 1; mmu <= 2; mmu++) {
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SUPP_BANK_SEL(mmu);
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for (i = 0; i < NUM_TLB_ENTRIES; i++) {
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UPDATE_TLB_SEL_IDX(i);
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SUPP_REG_RD(RW_MM_TLB_HI, tlb_hi);
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/* Check if page_id and address matches */
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if (((tlb_hi & 0xff) == page_id) &&
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((tlb_hi & PAGE_MASK) == addr)) {
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mmu_tlb_hi = REG_FIELD(mmu, rw_mm_tlb_hi, pid,
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INVALID_PAGEID) | addr;
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UPDATE_TLB_HILO(mmu_tlb_hi, 0);
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}
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}
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}
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local_irq_restore(flags);
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}
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/*
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* Initialize the context related info for a new mm_struct
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* instance.
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*/
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int
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init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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mm->context.page_id = NO_CONTEXT;
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return 0;
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}
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static DEFINE_SPINLOCK(mmu_context_lock);
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/* Called in schedule() just before actually doing the switch_to. */
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void
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switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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int cpu = smp_processor_id();
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/* Make sure there is a MMU context. */
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spin_lock(&mmu_context_lock);
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get_mmu_context(next);
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cpu_set(cpu, next->cpu_vm_mask);
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spin_unlock(&mmu_context_lock);
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/*
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* Remember the pgd for the fault handlers. Keep a seperate copy of it
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* because current and active_mm might be invalid at points where
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* there's still a need to derefer the pgd.
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*/
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per_cpu(current_pgd, cpu) = next->pgd;
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/* Switch context in the MMU. */
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if (tsk && task_thread_info(tsk))
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{
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SPEC_REG_WR(SPEC_REG_PID, next->context.page_id | task_thread_info(tsk)->tls);
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}
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else
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{
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SPEC_REG_WR(SPEC_REG_PID, next->context.page_id);
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}
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}
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