mirror of https://gitee.com/openkylin/linux.git
906 lines
25 KiB
ArmAsm
906 lines
25 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* PowerPC version
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Low-level exception handlers and MMU support
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* rewritten by Paul Mackerras.
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* Copyright (C) 1996 Paul Mackerras.
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* MPC8xx modifications by Dan Malek
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* Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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*
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* This file contains low-level support and setup for PowerPC 8xx
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* embedded processors, including trap and interrupt dispatch.
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*/
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#include <linux/init.h>
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#include <linux/magic.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/pgtable.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/ptrace.h>
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#include <asm/export.h>
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#include <asm/code-patching-asm.h>
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#include "head_32.h"
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#if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
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/* By simply checking Address >= 0x80000000, we know if its a kernel address */
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#define SIMPLE_KERNEL_ADDRESS 1
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#endif
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/*
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* We need an ITLB miss handler for kernel addresses if:
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* - Either we have modules
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* - Or we have not pinned the first 8M
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*/
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#if defined(CONFIG_MODULES) || !defined(CONFIG_PIN_TLB_TEXT) || \
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defined(CONFIG_DEBUG_PAGEALLOC)
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#define ITLB_MISS_KERNEL 1
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#endif
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/*
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* Value for the bits that have fixed value in RPN entries.
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* Also used for tagging DAR for DTLBerror.
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*/
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#define RPN_PATTERN 0x00f0
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#define PAGE_SHIFT_512K 19
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#define PAGE_SHIFT_8M 23
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__HEAD
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_ENTRY(_stext);
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_ENTRY(_start);
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/* MPC8xx
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* This port was done on an MBX board with an 860. Right now I only
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* support an ELF compressed (zImage) boot from EPPC-Bug because the
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* code there loads up some registers before calling us:
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* r3: ptr to board info data
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* r4: initrd_start or if no initrd then 0
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* r5: initrd_end - unused if r4 is 0
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* r6: Start of command line string
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* r7: End of command line string
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*
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* I decided to use conditional compilation instead of checking PVR and
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* adding more processor specific branches around code I don't need.
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* Since this is an embedded processor, I also appreciate any memory
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* savings I can get.
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*
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* The MPC8xx does not have any BATs, but it supports large page sizes.
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* We first initialize the MMU to support 8M byte pages, then load one
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* entry into each of the instruction and data TLBs to map the first
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* 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
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* the "internal" processor registers before MMU_init is called.
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*
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* -- Dan
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*/
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.globl __start
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__start:
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mr r31,r3 /* save device tree ptr */
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/* We have to turn on the MMU right away so we get cache modes
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* set correctly.
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*/
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bl initial_mmu
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/* We now have the lower 8 Meg mapped into TLB entries, and the caches
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* ready to work.
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*/
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turn_on_mmu:
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mfmsr r0
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ori r0,r0,MSR_DR|MSR_IR
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mtspr SPRN_SRR1,r0
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lis r0,start_here@h
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ori r0,r0,start_here@l
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mtspr SPRN_SRR0,r0
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rfi /* enables MMU */
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#ifdef CONFIG_PERF_EVENTS
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.align 4
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.globl itlb_miss_counter
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itlb_miss_counter:
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.space 4
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.globl dtlb_miss_counter
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dtlb_miss_counter:
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.space 4
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.globl instruction_counter
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instruction_counter:
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.space 4
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#endif
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/* System reset */
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EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
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/* Machine check */
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. = 0x200
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MachineCheck:
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EXCEPTION_PROLOG handle_dar_dsisr=1
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save_dar_dsisr_on_stack r4, r5, r11
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li r6, RPN_PATTERN
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mtspr SPRN_DAR, r6 /* Tag DAR, to be used in DTLB Error */
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addi r3,r1,STACK_FRAME_OVERHEAD
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EXC_XFER_STD(0x200, machine_check_exception)
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/* External interrupt */
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EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
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/* Alignment exception */
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. = 0x600
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Alignment:
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EXCEPTION_PROLOG handle_dar_dsisr=1
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save_dar_dsisr_on_stack r4, r5, r11
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li r6, RPN_PATTERN
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mtspr SPRN_DAR, r6 /* Tag DAR, to be used in DTLB Error */
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addi r3,r1,STACK_FRAME_OVERHEAD
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b .Lalignment_exception_ool
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/* Program check exception */
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EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
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/* Decrementer */
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EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
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/* With VMAP_STACK there's not enough room for this at 0x600 */
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. = 0xa00
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.Lalignment_exception_ool:
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EXC_XFER_STD(0x600, alignment_exception)
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/* System call */
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. = 0xc00
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SystemCall:
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SYSCALL_ENTRY 0xc00
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/* Single step - not used on 601 */
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EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
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/* On the MPC8xx, this is a software emulation interrupt. It occurs
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* for all unimplemented and illegal instructions.
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*/
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EXCEPTION(0x1000, SoftEmu, program_check_exception, EXC_XFER_STD)
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. = 0x1100
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/*
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* For the MPC8xx, this is a software tablewalk to load the instruction
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* TLB. The task switch loads the M_TWB register with the pointer to the first
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* level table.
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* If we discover there is no second level table (value is zero) or if there
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* is an invalid pte, we load that into the TLB, which causes another fault
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* into the TLB Error interrupt where we can handle such problems.
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* We have to use the MD_xxx registers for the tablewalk because the
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* equivalent MI_xxx registers only perform the attribute functions.
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*/
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#ifdef CONFIG_8xx_CPU15
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#define INVALIDATE_ADJACENT_PAGES_CPU15(addr) \
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addi addr, addr, PAGE_SIZE; \
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tlbie addr; \
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addi addr, addr, -(PAGE_SIZE << 1); \
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tlbie addr; \
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addi addr, addr, PAGE_SIZE
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#else
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#define INVALIDATE_ADJACENT_PAGES_CPU15(addr)
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#endif
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InstructionTLBMiss:
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mtspr SPRN_SPRG_SCRATCH0, r10
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
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mtspr SPRN_SPRG_SCRATCH1, r11
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#endif
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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mfspr r10, SPRN_SRR0 /* Get effective address of fault */
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INVALIDATE_ADJACENT_PAGES_CPU15(r10)
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mtspr SPRN_MD_EPN, r10
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/* Only modules will cause ITLB Misses as we always
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* pin the first 8MB of kernel memory */
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#ifdef ITLB_MISS_KERNEL
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mfcr r11
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#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
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cmpi cr0, r10, 0 /* Address >= 0x80000000 */
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#else
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rlwinm r10, r10, 16, 0xfff8
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cmpli cr0, r10, PAGE_OFFSET@h
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#ifndef CONFIG_PIN_TLB_TEXT
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/* It is assumed that kernel code fits into the first 32M */
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0: cmpli cr7, r10, (PAGE_OFFSET + 0x2000000)@h
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patch_site 0b, patch__itlbmiss_linmem_top
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#endif
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#endif
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#endif
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mfspr r10, SPRN_M_TWB /* Get level 1 table */
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#ifdef ITLB_MISS_KERNEL
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#if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
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bge+ 3f
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#else
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blt+ 3f
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#endif
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#ifndef CONFIG_PIN_TLB_TEXT
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blt cr7, ITLBMissLinear
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#endif
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rlwinm r10, r10, 0, 20, 31
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oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
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3:
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#endif
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lwz r10, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
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mtspr SPRN_MI_TWC, r10 /* Set segment attributes */
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mtspr SPRN_MD_TWC, r10
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mfspr r10, SPRN_MD_TWC
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lwz r10, 0(r10) /* Get the pte */
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#ifdef ITLB_MISS_KERNEL
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mtcr r11
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#endif
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#ifdef CONFIG_SWAP
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rlwinm r11, r10, 32-5, _PAGE_PRESENT
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and r11, r11, r10
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rlwimi r10, r11, 0, _PAGE_PRESENT
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#endif
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/* The Linux PTE won't go exactly into the MMU TLB.
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* Software indicator bits 20 and 23 must be clear.
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* Software indicator bits 22, 24, 25, 26, and 27 must be
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* set. All other Linux PTE bits control the behavior
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* of the MMU.
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*/
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rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */
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rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
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ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */
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mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
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/* Restore registers */
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0: mfspr r10, SPRN_SPRG_SCRATCH0
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
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mfspr r11, SPRN_SPRG_SCRATCH1
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#endif
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rfi
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patch_site 0b, patch__itlbmiss_exit_1
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#ifdef CONFIG_PERF_EVENTS
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patch_site 0f, patch__itlbmiss_perf
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0: lwz r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
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addi r10, r10, 1
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stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
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mfspr r10, SPRN_SPRG_SCRATCH0
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#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
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mfspr r11, SPRN_SPRG_SCRATCH1
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#endif
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rfi
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#endif
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#ifndef CONFIG_PIN_TLB_TEXT
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ITLBMissLinear:
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mtcr r11
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#if defined(CONFIG_STRICT_KERNEL_RWX) && CONFIG_ETEXT_SHIFT < 23
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patch_site 0f, patch__itlbmiss_linmem_top8
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mfspr r10, SPRN_SRR0
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0: subis r11, r10, (PAGE_OFFSET - 0x80000000)@ha
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rlwinm r11, r11, 4, MI_PS8MEG ^ MI_PS512K
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ori r11, r11, MI_PS512K | MI_SVALID
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rlwinm r10, r10, 0, 0x0ff80000 /* 8xx supports max 256Mb RAM */
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#else
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/* Set 8M byte page and mark it valid */
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li r11, MI_PS8MEG | MI_SVALID
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rlwinm r10, r10, 20, 0x0f800000 /* 8xx supports max 256Mb RAM */
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#endif
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mtspr SPRN_MI_TWC, r11
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ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
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_PAGE_PRESENT
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mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
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0: mfspr r10, SPRN_SPRG_SCRATCH0
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mfspr r11, SPRN_SPRG_SCRATCH1
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rfi
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patch_site 0b, patch__itlbmiss_exit_2
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#endif
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. = 0x1200
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DataStoreTLBMiss:
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mtspr SPRN_DAR, r10
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mtspr SPRN_M_TW, r11
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mfcr r11
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/* If we are faulting a kernel address, we have to use the
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* kernel page tables.
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*/
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mfspr r10, SPRN_MD_EPN
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rlwinm r10, r10, 16, 0xfff8
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cmpli cr0, r10, PAGE_OFFSET@h
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#ifndef CONFIG_PIN_TLB_IMMR
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cmpli cr6, r10, VIRT_IMMR_BASE@h
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#endif
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0: cmpli cr7, r10, (PAGE_OFFSET + 0x2000000)@h
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patch_site 0b, patch__dtlbmiss_linmem_top
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mfspr r10, SPRN_M_TWB /* Get level 1 table */
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blt+ 3f
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#ifndef CONFIG_PIN_TLB_IMMR
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0: beq- cr6, DTLBMissIMMR
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patch_site 0b, patch__dtlbmiss_immr_jmp
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#endif
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blt cr7, DTLBMissLinear
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rlwinm r10, r10, 0, 20, 31
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oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
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3:
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mtcr r11
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lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
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mtspr SPRN_MD_TWC, r11
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mfspr r10, SPRN_MD_TWC
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lwz r10, 0(r10) /* Get the pte */
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/* Insert the Guarded flag into the TWC from the Linux PTE.
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* It is bit 27 of both the Linux PTE and the TWC (at least
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* I got that right :-). It will be better when we can put
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* this into the Linux pgd/pmd and load it in the operation
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* above.
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*/
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rlwimi r11, r10, 0, _PAGE_GUARDED
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mtspr SPRN_MD_TWC, r11
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/* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
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* We also need to know if the insn is a load/store, so:
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* Clear _PAGE_PRESENT and load that which will
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* trap into DTLB Error with store bit set accordinly.
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*/
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/* PRESENT=0x1, ACCESSED=0x20
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* r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
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* r10 = (r10 & ~PRESENT) | r11;
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*/
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#ifdef CONFIG_SWAP
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rlwinm r11, r10, 32-5, _PAGE_PRESENT
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and r11, r11, r10
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rlwimi r10, r11, 0, _PAGE_PRESENT
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#endif
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/* The Linux PTE won't go exactly into the MMU TLB.
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* Software indicator bits 24, 25, 26, and 27 must be
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* set. All other Linux PTE bits control the behavior
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* of the MMU.
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*/
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li r11, RPN_PATTERN
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rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */
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mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
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/* Restore registers */
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0: mfspr r10, SPRN_DAR
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mtspr SPRN_DAR, r11 /* Tag DAR */
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mfspr r11, SPRN_M_TW
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rfi
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patch_site 0b, patch__dtlbmiss_exit_1
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DTLBMissIMMR:
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mtcr r11
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/* Set 512k byte guarded page and mark it valid */
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li r10, MD_PS512K | MD_GUARDED | MD_SVALID
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mtspr SPRN_MD_TWC, r10
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mfspr r10, SPRN_IMMR /* Get current IMMR */
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rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
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ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
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_PAGE_PRESENT | _PAGE_NO_CACHE
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mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
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li r11, RPN_PATTERN
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0: mfspr r10, SPRN_DAR
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mtspr SPRN_DAR, r11 /* Tag DAR */
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mfspr r11, SPRN_M_TW
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rfi
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patch_site 0b, patch__dtlbmiss_exit_2
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DTLBMissLinear:
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mtcr r11
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rlwinm r10, r10, 20, 0x0f800000 /* 8xx supports max 256Mb RAM */
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#if defined(CONFIG_STRICT_KERNEL_RWX) && CONFIG_DATA_SHIFT < 23
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patch_site 0f, patch__dtlbmiss_romem_top8
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0: subis r11, r10, (PAGE_OFFSET - 0x80000000)@ha
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rlwinm r11, r11, 0, 0xff800000
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neg r10, r11
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or r11, r11, r10
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rlwinm r11, r11, 4, MI_PS8MEG ^ MI_PS512K
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ori r11, r11, MI_PS512K | MI_SVALID
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mfspr r10, SPRN_MD_EPN
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rlwinm r10, r10, 0, 0x0ff80000 /* 8xx supports max 256Mb RAM */
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#else
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/* Set 8M byte page and mark it valid */
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li r11, MD_PS8MEG | MD_SVALID
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#endif
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mtspr SPRN_MD_TWC, r11
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#ifdef CONFIG_STRICT_KERNEL_RWX
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patch_site 0f, patch__dtlbmiss_romem_top
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0: subis r11, r10, 0
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rlwimi r10, r11, 11, _PAGE_RO
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#endif
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ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
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_PAGE_PRESENT
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mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
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li r11, RPN_PATTERN
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0: mfspr r10, SPRN_DAR
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mtspr SPRN_DAR, r11 /* Tag DAR */
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mfspr r11, SPRN_M_TW
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rfi
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patch_site 0b, patch__dtlbmiss_exit_3
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/* This is an instruction TLB error on the MPC8xx. This could be due
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* to many reasons, such as executing guarded memory or illegal instruction
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* addresses. There is nothing to do but handle a big time error fault.
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*/
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. = 0x1300
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InstructionTLBError:
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EXCEPTION_PROLOG
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mr r4,r12
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andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
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andis. r10,r9,SRR1_ISI_NOPT@h
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beq+ .Litlbie
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tlbie r4
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/* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
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.Litlbie:
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stw r4, _DAR(r11)
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EXC_XFER_LITE(0x400, handle_page_fault)
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|
/* This is the data TLB error on the MPC8xx. This could be due to
|
|
* many reasons, including a dirty update to a pte. We bail out to
|
|
* a higher level function that can handle it.
|
|
*/
|
|
. = 0x1400
|
|
DataTLBError:
|
|
EXCEPTION_PROLOG_0 handle_dar_dsisr=1
|
|
mfspr r11, SPRN_DAR
|
|
cmpwi cr1, r11, RPN_PATTERN
|
|
beq- cr1, FixupDAR /* must be a buggy dcbX, icbi insn. */
|
|
DARFixed:/* Return from dcbx instruction bug workaround */
|
|
#ifdef CONFIG_VMAP_STACK
|
|
li r11, RPN_PATTERN
|
|
mtspr SPRN_DAR, r11 /* Tag DAR, to be used in DTLB Error */
|
|
#endif
|
|
EXCEPTION_PROLOG_1
|
|
EXCEPTION_PROLOG_2 handle_dar_dsisr=1
|
|
get_and_save_dar_dsisr_on_stack r4, r5, r11
|
|
andis. r10,r5,DSISR_NOHPTE@h
|
|
beq+ .Ldtlbie
|
|
tlbie r4
|
|
.Ldtlbie:
|
|
#ifndef CONFIG_VMAP_STACK
|
|
li r10,RPN_PATTERN
|
|
mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
|
|
#endif
|
|
/* 0x300 is DataAccess exception, needed by bad_page_fault() */
|
|
EXC_XFER_LITE(0x300, handle_page_fault)
|
|
|
|
/* Called from DataStoreTLBMiss when perf TLB misses events are activated */
|
|
#ifdef CONFIG_PERF_EVENTS
|
|
patch_site 0f, patch__dtlbmiss_perf
|
|
0: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
|
|
addi r10, r10, 1
|
|
stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
|
|
mfspr r10, SPRN_DAR
|
|
mtspr SPRN_DAR, r11 /* Tag DAR */
|
|
mfspr r11, SPRN_M_TW
|
|
rfi
|
|
#endif
|
|
|
|
stack_overflow:
|
|
vmap_stack_overflow_exception
|
|
|
|
/* On the MPC8xx, these next four traps are used for development
|
|
* support of breakpoints and such. Someday I will get around to
|
|
* using them.
|
|
*/
|
|
do_databreakpoint:
|
|
EXCEPTION_PROLOG_1
|
|
EXCEPTION_PROLOG_2 handle_dar_dsisr=1
|
|
addi r3,r1,STACK_FRAME_OVERHEAD
|
|
mfspr r4,SPRN_BAR
|
|
stw r4,_DAR(r11)
|
|
#ifdef CONFIG_VMAP_STACK
|
|
lwz r5,_DSISR(r11)
|
|
#else
|
|
mfspr r5,SPRN_DSISR
|
|
#endif
|
|
EXC_XFER_STD(0x1c00, do_break)
|
|
|
|
. = 0x1c00
|
|
DataBreakpoint:
|
|
EXCEPTION_PROLOG_0 handle_dar_dsisr=1
|
|
mfspr r11, SPRN_SRR0
|
|
cmplwi cr1, r11, (.Ldtlbie - PAGE_OFFSET)@l
|
|
cmplwi cr7, r11, (.Litlbie - PAGE_OFFSET)@l
|
|
cror 4*cr1+eq, 4*cr1+eq, 4*cr7+eq
|
|
bne cr1, do_databreakpoint
|
|
mtcr r10
|
|
mfspr r10, SPRN_SPRG_SCRATCH0
|
|
mfspr r11, SPRN_SPRG_SCRATCH1
|
|
rfi
|
|
|
|
#ifdef CONFIG_PERF_EVENTS
|
|
. = 0x1d00
|
|
InstructionBreakpoint:
|
|
mtspr SPRN_SPRG_SCRATCH0, r10
|
|
lwz r10, (instruction_counter - PAGE_OFFSET)@l(0)
|
|
addi r10, r10, -1
|
|
stw r10, (instruction_counter - PAGE_OFFSET)@l(0)
|
|
lis r10, 0xffff
|
|
ori r10, r10, 0x01
|
|
mtspr SPRN_COUNTA, r10
|
|
mfspr r10, SPRN_SPRG_SCRATCH0
|
|
rfi
|
|
#else
|
|
EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_STD)
|
|
#endif
|
|
EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_STD)
|
|
EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_STD)
|
|
|
|
. = 0x2000
|
|
|
|
/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
|
|
* by decoding the registers used by the dcbx instruction and adding them.
|
|
* DAR is set to the calculated address.
|
|
*/
|
|
FixupDAR:/* Entry point for dcbx workaround. */
|
|
mtspr SPRN_M_TW, r10
|
|
/* fetch instruction from memory. */
|
|
mfspr r10, SPRN_SRR0
|
|
mtspr SPRN_MD_EPN, r10
|
|
rlwinm r11, r10, 16, 0xfff8
|
|
cmpli cr1, r11, PAGE_OFFSET@h
|
|
mfspr r11, SPRN_M_TWB /* Get level 1 table */
|
|
blt+ cr1, 3f
|
|
rlwinm r11, r10, 16, 0xfff8
|
|
|
|
0: cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
|
|
patch_site 0b, patch__fixupdar_linmem_top
|
|
|
|
/* create physical page address from effective address */
|
|
tophys(r11, r10)
|
|
blt- cr7, 201f
|
|
mfspr r11, SPRN_M_TWB /* Get level 1 table */
|
|
rlwinm r11, r11, 0, 20, 31
|
|
oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
|
|
3:
|
|
lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
|
|
mtspr SPRN_MD_TWC, r11
|
|
mtcrf 0x01, r11
|
|
mfspr r11, SPRN_MD_TWC
|
|
lwz r11, 0(r11) /* Get the pte */
|
|
bt 28,200f /* bit 28 = Large page (8M) */
|
|
bt 29,202f /* bit 29 = Large page (8M or 512K) */
|
|
/* concat physical page address(r11) and page offset(r10) */
|
|
rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
|
|
201: lwz r11,0(r11)
|
|
/* Check if it really is a dcbx instruction. */
|
|
/* dcbt and dcbtst does not generate DTLB Misses/Errors,
|
|
* no need to include them here */
|
|
xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
|
|
rlwinm r10, r10, 0, 21, 5
|
|
cmpwi cr1, r10, 2028 /* Is dcbz? */
|
|
beq+ cr1, 142f
|
|
cmpwi cr1, r10, 940 /* Is dcbi? */
|
|
beq+ cr1, 142f
|
|
cmpwi cr1, r10, 108 /* Is dcbst? */
|
|
beq+ cr1, 144f /* Fix up store bit! */
|
|
cmpwi cr1, r10, 172 /* Is dcbf? */
|
|
beq+ cr1, 142f
|
|
cmpwi cr1, r10, 1964 /* Is icbi? */
|
|
beq+ cr1, 142f
|
|
141: mfspr r10,SPRN_M_TW
|
|
b DARFixed /* Nope, go back to normal TLB processing */
|
|
|
|
200:
|
|
/* concat physical page address(r11) and page offset(r10) */
|
|
rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
|
|
b 201b
|
|
|
|
202:
|
|
/* concat physical page address(r11) and page offset(r10) */
|
|
rlwimi r11, r10, 0, 32 - PAGE_SHIFT_512K, 31
|
|
b 201b
|
|
|
|
144: mfspr r10, SPRN_DSISR
|
|
rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
|
|
mtspr SPRN_DSISR, r10
|
|
142: /* continue, it was a dcbx, dcbi instruction. */
|
|
mfctr r10
|
|
mtdar r10 /* save ctr reg in DAR */
|
|
rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
|
|
addi r10, r10, 150f@l /* add start of table */
|
|
mtctr r10 /* load ctr with jump address */
|
|
xor r10, r10, r10 /* sum starts at zero */
|
|
bctr /* jump into table */
|
|
150:
|
|
add r10, r10, r0 ;b 151f
|
|
add r10, r10, r1 ;b 151f
|
|
add r10, r10, r2 ;b 151f
|
|
add r10, r10, r3 ;b 151f
|
|
add r10, r10, r4 ;b 151f
|
|
add r10, r10, r5 ;b 151f
|
|
add r10, r10, r6 ;b 151f
|
|
add r10, r10, r7 ;b 151f
|
|
add r10, r10, r8 ;b 151f
|
|
add r10, r10, r9 ;b 151f
|
|
mtctr r11 ;b 154f /* r10 needs special handling */
|
|
mtctr r11 ;b 153f /* r11 needs special handling */
|
|
add r10, r10, r12 ;b 151f
|
|
add r10, r10, r13 ;b 151f
|
|
add r10, r10, r14 ;b 151f
|
|
add r10, r10, r15 ;b 151f
|
|
add r10, r10, r16 ;b 151f
|
|
add r10, r10, r17 ;b 151f
|
|
add r10, r10, r18 ;b 151f
|
|
add r10, r10, r19 ;b 151f
|
|
add r10, r10, r20 ;b 151f
|
|
add r10, r10, r21 ;b 151f
|
|
add r10, r10, r22 ;b 151f
|
|
add r10, r10, r23 ;b 151f
|
|
add r10, r10, r24 ;b 151f
|
|
add r10, r10, r25 ;b 151f
|
|
add r10, r10, r26 ;b 151f
|
|
add r10, r10, r27 ;b 151f
|
|
add r10, r10, r28 ;b 151f
|
|
add r10, r10, r29 ;b 151f
|
|
add r10, r10, r30 ;b 151f
|
|
add r10, r10, r31
|
|
151:
|
|
rlwinm r11,r11,19,24,28 /* offset into jump table for reg RA */
|
|
cmpwi cr1, r11, 0
|
|
beq cr1, 152f /* if reg RA is zero, don't add it */
|
|
addi r11, r11, 150b@l /* add start of table */
|
|
mtctr r11 /* load ctr with jump address */
|
|
rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
|
|
bctr /* jump into table */
|
|
152:
|
|
mfdar r11
|
|
mtctr r11 /* restore ctr reg from DAR */
|
|
#ifdef CONFIG_VMAP_STACK
|
|
mfspr r11, SPRN_SPRG_THREAD
|
|
stw r10, DAR(r11)
|
|
mfspr r10, SPRN_DSISR
|
|
stw r10, DSISR(r11)
|
|
#else
|
|
mtdar r10 /* save fault EA to DAR */
|
|
#endif
|
|
mfspr r10,SPRN_M_TW
|
|
b DARFixed /* Go back to normal TLB handling */
|
|
|
|
/* special handling for r10,r11 since these are modified already */
|
|
153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
|
|
add r10, r10, r11 /* add it */
|
|
mfctr r11 /* restore r11 */
|
|
b 151b
|
|
154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
|
|
add r10, r10, r11 /* add it */
|
|
mfctr r11 /* restore r11 */
|
|
b 151b
|
|
|
|
/*
|
|
* This is where the main kernel code starts.
|
|
*/
|
|
start_here:
|
|
/* ptr to current */
|
|
lis r2,init_task@h
|
|
ori r2,r2,init_task@l
|
|
|
|
/* ptr to phys current thread */
|
|
tophys(r4,r2)
|
|
addi r4,r4,THREAD /* init task's THREAD */
|
|
mtspr SPRN_SPRG_THREAD,r4
|
|
|
|
/* stack */
|
|
lis r1,init_thread_union@ha
|
|
addi r1,r1,init_thread_union@l
|
|
lis r0, STACK_END_MAGIC@h
|
|
ori r0, r0, STACK_END_MAGIC@l
|
|
stw r0, 0(r1)
|
|
li r0,0
|
|
stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
|
|
|
|
lis r6, swapper_pg_dir@ha
|
|
tophys(r6,r6)
|
|
mtspr SPRN_M_TWB, r6
|
|
|
|
bl early_init /* We have to do this with MMU on */
|
|
|
|
/*
|
|
* Decide what sort of machine this is and initialize the MMU.
|
|
*/
|
|
#ifdef CONFIG_KASAN
|
|
bl kasan_early_init
|
|
#endif
|
|
li r3,0
|
|
mr r4,r31
|
|
bl machine_init
|
|
bl MMU_init
|
|
|
|
/*
|
|
* Go back to running unmapped so we can load up new values
|
|
* and change to using our exception vectors.
|
|
* On the 8xx, all we have to do is invalidate the TLB to clear
|
|
* the old 8M byte TLB mappings and load the page table base register.
|
|
*/
|
|
/* The right way to do this would be to track it down through
|
|
* init's THREAD like the context switch code does, but this is
|
|
* easier......until someone changes init's static structures.
|
|
*/
|
|
lis r4,2f@h
|
|
ori r4,r4,2f@l
|
|
tophys(r4,r4)
|
|
li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
|
|
mtspr SPRN_SRR0,r4
|
|
mtspr SPRN_SRR1,r3
|
|
rfi
|
|
/* Load up the kernel context */
|
|
2:
|
|
tlbia /* Clear all TLB entries */
|
|
sync /* wait for tlbia/tlbie to finish */
|
|
|
|
/* set up the PTE pointers for the Abatron bdiGDB.
|
|
*/
|
|
lis r5, abatron_pteptrs@h
|
|
ori r5, r5, abatron_pteptrs@l
|
|
stw r5, 0xf0(0) /* Must match your Abatron config file */
|
|
tophys(r5,r5)
|
|
lis r6, swapper_pg_dir@h
|
|
ori r6, r6, swapper_pg_dir@l
|
|
stw r6, 0(r5)
|
|
|
|
/* Now turn on the MMU for real! */
|
|
li r4,MSR_KERNEL
|
|
lis r3,start_kernel@h
|
|
ori r3,r3,start_kernel@l
|
|
mtspr SPRN_SRR0,r3
|
|
mtspr SPRN_SRR1,r4
|
|
rfi /* enable MMU and jump to start_kernel */
|
|
|
|
/* Set up the initial MMU state so we can do the first level of
|
|
* kernel initialization. This maps the first 8 MBytes of memory 1:1
|
|
* virtual to physical. Also, set the cache mode since that is defined
|
|
* by TLB entries and perform any additional mapping (like of the IMMR).
|
|
* If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
|
|
* 24 Mbytes of data, and the 512k IMMR space. Anything not covered by
|
|
* these mappings is mapped by page tables.
|
|
*/
|
|
initial_mmu:
|
|
li r8, 0
|
|
mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */
|
|
lis r10, MD_RESETVAL@h
|
|
#ifndef CONFIG_8xx_COPYBACK
|
|
oris r10, r10, MD_WTDEF@h
|
|
#endif
|
|
mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */
|
|
|
|
tlbia /* Invalidate all TLB entries */
|
|
#ifdef CONFIG_PIN_TLB_DATA
|
|
oris r10, r10, MD_RSV4I@h
|
|
mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
|
|
#endif
|
|
|
|
lis r8, MI_APG_INIT@h /* Set protection modes */
|
|
ori r8, r8, MI_APG_INIT@l
|
|
mtspr SPRN_MI_AP, r8
|
|
lis r8, MD_APG_INIT@h
|
|
ori r8, r8, MD_APG_INIT@l
|
|
mtspr SPRN_MD_AP, r8
|
|
|
|
/* Map a 512k page for the IMMR to get the processor
|
|
* internal registers (among other things).
|
|
*/
|
|
#ifdef CONFIG_PIN_TLB_IMMR
|
|
oris r10, r10, MD_RSV4I@h
|
|
ori r10, r10, 0x1c00
|
|
mtspr SPRN_MD_CTR, r10
|
|
|
|
mfspr r9, 638 /* Get current IMMR */
|
|
andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */
|
|
|
|
lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */
|
|
ori r8, r8, MD_EVALID /* Mark it valid */
|
|
mtspr SPRN_MD_EPN, r8
|
|
li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */
|
|
ori r8, r8, MD_SVALID /* Make it valid */
|
|
mtspr SPRN_MD_TWC, r8
|
|
mr r8, r9 /* Create paddr for TLB */
|
|
ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
|
|
mtspr SPRN_MD_RPN, r8
|
|
#endif
|
|
|
|
/* Now map the lower RAM (up to 32 Mbytes) into the ITLB. */
|
|
#ifdef CONFIG_PIN_TLB_TEXT
|
|
lis r8, MI_RSV4I@h
|
|
ori r8, r8, 0x1c00
|
|
#endif
|
|
li r9, 4 /* up to 4 pages of 8M */
|
|
mtctr r9
|
|
lis r9, KERNELBASE@h /* Create vaddr for TLB */
|
|
li r10, MI_PS8MEG | MI_SVALID /* Set 8M byte page */
|
|
li r11, MI_BOOTINIT /* Create RPN for address 0 */
|
|
lis r12, _einittext@h
|
|
ori r12, r12, _einittext@l
|
|
1:
|
|
#ifdef CONFIG_PIN_TLB_TEXT
|
|
mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
|
|
addi r8, r8, 0x100
|
|
#endif
|
|
|
|
ori r0, r9, MI_EVALID /* Mark it valid */
|
|
mtspr SPRN_MI_EPN, r0
|
|
mtspr SPRN_MI_TWC, r10
|
|
mtspr SPRN_MI_RPN, r11 /* Store TLB entry */
|
|
addis r9, r9, 0x80
|
|
addis r11, r11, 0x80
|
|
|
|
cmpl cr0, r9, r12
|
|
bdnzf gt, 1b
|
|
|
|
/* Since the cache is enabled according to the information we
|
|
* just loaded into the TLB, invalidate and enable the caches here.
|
|
* We should probably check/set other modes....later.
|
|
*/
|
|
lis r8, IDC_INVALL@h
|
|
mtspr SPRN_IC_CST, r8
|
|
mtspr SPRN_DC_CST, r8
|
|
lis r8, IDC_ENABLE@h
|
|
mtspr SPRN_IC_CST, r8
|
|
#ifdef CONFIG_8xx_COPYBACK
|
|
mtspr SPRN_DC_CST, r8
|
|
#else
|
|
/* For a debug option, I left this here to easily enable
|
|
* the write through cache mode
|
|
*/
|
|
lis r8, DC_SFWT@h
|
|
mtspr SPRN_DC_CST, r8
|
|
lis r8, IDC_ENABLE@h
|
|
mtspr SPRN_DC_CST, r8
|
|
#endif
|
|
/* Disable debug mode entry on breakpoints */
|
|
mfspr r8, SPRN_DER
|
|
#ifdef CONFIG_PERF_EVENTS
|
|
rlwinm r8, r8, 0, ~0xc
|
|
#else
|
|
rlwinm r8, r8, 0, ~0x8
|
|
#endif
|
|
mtspr SPRN_DER, r8
|
|
blr
|
|
|
|
|
|
/*
|
|
* We put a few things here that have to be page-aligned.
|
|
* This stuff goes at the beginning of the data segment,
|
|
* which is page-aligned.
|
|
*/
|
|
.data
|
|
.globl sdata
|
|
sdata:
|
|
.globl empty_zero_page
|
|
.align PAGE_SHIFT
|
|
empty_zero_page:
|
|
.space PAGE_SIZE
|
|
EXPORT_SYMBOL(empty_zero_page)
|
|
|
|
.globl swapper_pg_dir
|
|
swapper_pg_dir:
|
|
.space PGD_TABLE_SIZE
|
|
|
|
/* Room for two PTE table poiners, usually the kernel and current user
|
|
* pointer to their respective root page table (pgdir).
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*/
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.globl abatron_pteptrs
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abatron_pteptrs:
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.space 8
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