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145 lines
4.0 KiB
Plaintext
145 lines
4.0 KiB
Plaintext
* Allwinner A1X Pin Controller
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The pins controlled by sunXi pin controller are organized in banks,
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each bank has 32 pins. Each pin has 7 multiplexing functions, with
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the first two functions being GPIO in and out. The configuration on
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the pins includes drive strength and pull-up.
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Required properties:
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- compatible: Should be one of the following (depending on your SoC):
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"allwinner,sun4i-a10-pinctrl"
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"allwinner,sun5i-a10s-pinctrl"
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"allwinner,sun5i-a13-pinctrl"
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"allwinner,sun6i-a31-pinctrl"
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"allwinner,sun6i-a31s-pinctrl"
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"allwinner,sun6i-a31-r-pinctrl"
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"allwinner,sun7i-a20-pinctrl"
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"allwinner,sun8i-a23-pinctrl"
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"allwinner,sun8i-a23-r-pinctrl"
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"allwinner,sun8i-a33-pinctrl"
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"allwinner,sun9i-a80-pinctrl"
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"allwinner,sun9i-a80-r-pinctrl"
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"allwinner,sun8i-a83t-pinctrl"
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"allwinner,sun8i-h3-pinctrl"
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"allwinner,sun8i-h3-r-pinctrl"
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"allwinner,sun50i-a64-pinctrl"
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"allwinner,sun50i-a64-r-pinctrl"
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"allwinner,sun50i-h5-pinctrl"
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"nextthing,gr8-pinctrl"
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- reg: Should contain the register physical address and length for the
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pin controller.
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- clocks: phandle to the clocks feeding the pin controller:
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- "apb": the gated APB parent clock
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- "hosc": the high frequency oscillator in the system
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- "losc": the low frequency oscillator in the system
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Note: For backward compatibility reasons, the hosc and losc clocks are only
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required if you need to use the optional input-debounce property. Any new
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device tree should set them.
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Optional properties:
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- input-debounce: Array of debouncing periods in microseconds. One period per
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irq bank found in the controller. 0 if no setup required.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices.
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A pinctrl node should contain at least one subnodes representing the
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pinctrl groups available on the machine. Each subnode will list the
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pins it needs, and how they should be configured, with regard to muxer
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configuration, drive strength and pullups. If one of these options is
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not set, its actual value will be unspecified.
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This driver supports the generic pin multiplexing and configuration
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bindings. For details on each properties, you can refer to
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./pinctrl-bindings.txt.
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Required sub-node properties:
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- pins
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- function
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Optional sub-node properties:
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- bias-disable
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- bias-pull-up
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- bias-pull-down
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- drive-strength
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*** Deprecated pin configuration and multiplexing binding
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Required subnode-properties:
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- allwinner,pins: List of strings containing the pin name.
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- allwinner,function: Function to mux the pins listed above to.
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Optional subnode-properties:
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- allwinner,drive: Integer. Represents the current sent to the pin
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0: 10 mA
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1: 20 mA
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2: 30 mA
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3: 40 mA
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- allwinner,pull: Integer.
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0: No resistor
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1: Pull-up resistor
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2: Pull-down resistor
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Examples:
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pio: pinctrl@01c20800 {
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compatible = "allwinner,sun5i-a13-pinctrl";
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reg = <0x01c20800 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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uart1_pins_a: uart1@0 {
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allwinner,pins = "PE10", "PE11";
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allwinner,function = "uart1";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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uart1_pins_b: uart1@1 {
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allwinner,pins = "PG3", "PG4";
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allwinner,function = "uart1";
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allwinner,drive = <0>;
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allwinner,pull = <0>;
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};
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};
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GPIO and interrupt controller
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-----------------------------
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This hardware also acts as a GPIO controller and an interrupt
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controller.
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Consumers that would want to refer to one or the other (or both)
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should provide through the usual *-gpios and interrupts properties a
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cell with 3 arguments, first the number of the bank, then the pin
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inside that bank, and finally the flags for the GPIO/interrupts.
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Example:
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xio: gpio@38 {
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compatible = "nxp,pcf8574a";
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reg = <0x38>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&pio>;
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interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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reg_usb1_vbus: usb1-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb1-vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
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};
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