mirror of https://gitee.com/openkylin/linux.git
511 lines
23 KiB
C
511 lines
23 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/**********************************************************
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* Copyright 1998-2019 VMware, Inc.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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**********************************************************/
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/*
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* svga3d_devcaps.h --
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*
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* SVGA 3d caps definitions
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*/
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#ifndef _SVGA3D_DEVCAPS_H_
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#define _SVGA3D_DEVCAPS_H_
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#define INCLUDE_ALLOW_MODULE
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#define INCLUDE_ALLOW_USERLEVEL
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#define INCLUDE_ALLOW_VMCORE
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#include "includeCheck.h"
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#include "svga3d_types.h"
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/*
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* 3D Hardware Version
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*
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* The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
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* register. Is set by the host and read by the guest. This lets
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* us make new guest drivers which are backwards-compatible with old
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* SVGA hardware revisions. It does not let us support old guest
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* drivers. Good enough for now.
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*
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*/
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#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
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#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
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#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
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typedef enum {
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SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
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SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
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SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
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SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
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SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
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SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
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SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
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SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
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} SVGA3dHardwareVersion;
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/*
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* DevCap indexes.
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*/
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typedef uint32 SVGA3dDevCapIndex;
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#define SVGA3D_DEVCAP_INVALID ((uint32)-1)
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#define SVGA3D_DEVCAP_3D 0
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#define SVGA3D_DEVCAP_MAX_LIGHTS 1
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/*
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* SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
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* fixed-function texture units available. Each of these units
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* work in both FFP and Shader modes, and they support texture
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* transforms and texture coordinates. The host may have additional
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* texture image units that are only usable with shaders.
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*/
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#define SVGA3D_DEVCAP_MAX_TEXTURES 2
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#define SVGA3D_DEVCAP_MAX_CLIP_PLANES 3
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#define SVGA3D_DEVCAP_VERTEX_SHADER_VERSION 4
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#define SVGA3D_DEVCAP_VERTEX_SHADER 5
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#define SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION 6
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#define SVGA3D_DEVCAP_FRAGMENT_SHADER 7
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#define SVGA3D_DEVCAP_MAX_RENDER_TARGETS 8
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#define SVGA3D_DEVCAP_S23E8_TEXTURES 9
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#define SVGA3D_DEVCAP_S10E5_TEXTURES 10
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#define SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND 11
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#define SVGA3D_DEVCAP_D16_BUFFER_FORMAT 12
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#define SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT 13
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#define SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT 14
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#define SVGA3D_DEVCAP_QUERY_TYPES 15
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#define SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING 16
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#define SVGA3D_DEVCAP_MAX_POINT_SIZE 17
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#define SVGA3D_DEVCAP_MAX_SHADER_TEXTURES 18
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#define SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH 19
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#define SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT 20
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#define SVGA3D_DEVCAP_MAX_VOLUME_EXTENT 21
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#define SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT 22
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#define SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO 23
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#define SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY 24
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#define SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT 25
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#define SVGA3D_DEVCAP_MAX_VERTEX_INDEX 26
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#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS 27
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#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS 28
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#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS 29
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#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS 30
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#define SVGA3D_DEVCAP_TEXTURE_OPS 31
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#define SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 32
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#define SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 33
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#define SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 34
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#define SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 35
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#define SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 36
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#define SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 37
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#define SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 38
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#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 39
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#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 40
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#define SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 41
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#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 42
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#define SVGA3D_DEVCAP_SURFACEFMT_Z_D16 43
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#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 44
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#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 45
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#define SVGA3D_DEVCAP_SURFACEFMT_DXT1 46
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#define SVGA3D_DEVCAP_SURFACEFMT_DXT2 47
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#define SVGA3D_DEVCAP_SURFACEFMT_DXT3 48
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#define SVGA3D_DEVCAP_SURFACEFMT_DXT4 49
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#define SVGA3D_DEVCAP_SURFACEFMT_DXT5 50
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#define SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 51
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#define SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 52
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#define SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 53
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#define SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 54
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#define SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 55
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#define SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 56
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#define SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 57
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#define SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 58
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#define SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 59
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#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 60
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#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 61
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/*
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* There is a hole in our devcap definitions for
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* historical reasons.
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*
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* Define a constant just for completeness.
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*/
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#define SVGA3D_DEVCAP_MISSING62 62
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#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES 63
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/*
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* Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
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* render targets. This does not include the depth or stencil targets.
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*/
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#define SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS 64
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#define SVGA3D_DEVCAP_SURFACEFMT_V16U16 65
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#define SVGA3D_DEVCAP_SURFACEFMT_G16R16 66
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#define SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 67
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#define SVGA3D_DEVCAP_SURFACEFMT_UYVY 68
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#define SVGA3D_DEVCAP_SURFACEFMT_YUY2 69
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/*
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* Deprecated.
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*/
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#define SVGA3D_DEVCAP_DEAD4 70
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#define SVGA3D_DEVCAP_DEAD5 71
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#define SVGA3D_DEVCAP_DEAD7 72
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#define SVGA3D_DEVCAP_DEAD6 73
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#define SVGA3D_DEVCAP_AUTOGENMIPMAPS 74
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#define SVGA3D_DEVCAP_SURFACEFMT_NV12 75
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#define SVGA3D_DEVCAP_DEAD10 76
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/*
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* This is the maximum number of SVGA context IDs that the guest
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* can define using SVGA_3D_CMD_CONTEXT_DEFINE.
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*/
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#define SVGA3D_DEVCAP_MAX_CONTEXT_IDS 77
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/*
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* This is the maximum number of SVGA surface IDs that the guest
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* can define using SVGA_3D_CMD_SURFACE_DEFINE*.
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*/
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#define SVGA3D_DEVCAP_MAX_SURFACE_IDS 78
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#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 79
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#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 80
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#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT 81
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#define SVGA3D_DEVCAP_SURFACEFMT_ATI1 82
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#define SVGA3D_DEVCAP_SURFACEFMT_ATI2 83
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/*
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* Deprecated.
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*/
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#define SVGA3D_DEVCAP_DEAD1 84
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#define SVGA3D_DEVCAP_DEAD8 85
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#define SVGA3D_DEVCAP_DEAD9 86
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#define SVGA3D_DEVCAP_LINE_AA 87 /* boolean */
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#define SVGA3D_DEVCAP_LINE_STIPPLE 88 /* boolean */
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#define SVGA3D_DEVCAP_MAX_LINE_WIDTH 89 /* float */
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#define SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH 90 /* float */
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#define SVGA3D_DEVCAP_SURFACEFMT_YV12 91
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/*
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* Deprecated.
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*/
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#define SVGA3D_DEVCAP_DEAD3 92
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/*
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* Are TS_CONSTANT, TS_COLOR_KEY, and TS_COLOR_KEY_ENABLE supported?
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*/
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#define SVGA3D_DEVCAP_TS_COLOR_KEY 93 /* boolean */
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/*
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* Deprecated.
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*/
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#define SVGA3D_DEVCAP_DEAD2 94
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/*
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* Does the device support DXContexts?
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*/
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#define SVGA3D_DEVCAP_DXCONTEXT 95
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/*
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* Deprecated.
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*/
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#define SVGA3D_DEVCAP_DEAD11 96
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/*
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* What is the maximum number of vertex buffers or vertex input registers
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* that can be expected to work correctly with a DXContext?
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*
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* The guest is allowed to set up to SVGA3D_DX_MAX_VERTEXBUFFERS, but
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* anything in excess of this cap is not guaranteed to render correctly.
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*
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* Similarly, the guest can set up to SVGA3D_DX_MAX_VERTEXINPUTREGISTERS
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* input registers without the SVGA3D_DEVCAP_SM4_1 cap, or
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* SVGA3D_DX_SM41_MAX_VERTEXINPUTREGISTERS with the SVGA3D_DEVCAP_SM4_1,
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* but only the registers up to this cap value are guaranteed to render
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* correctly.
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*
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* If guest-drivers are able to expose a lower-limit, it's recommended
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* that they clamp to this value. Otherwise, the host will make a
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* best-effort on case-by-case basis if guests exceed this.
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*/
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#define SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS 97
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/*
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* What is the maximum number of constant buffers that can be expected to
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* work correctly with a DX context?
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*
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* The guest is allowed to set up to SVGA3D_DX_MAX_CONSTBUFFERS, but
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* anything in excess of this cap is not guaranteed to render correctly.
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*
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* If guest-drivers are able to expose a lower-limit, it's recommended
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* that they clamp to this value. Otherwise, the host will make a
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* best-effort on case-by-case basis if guests exceed this.
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*/
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#define SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS 98
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/*
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* Does the device support provoking vertex control?
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*
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* If this cap is present, the provokingVertexLast field in the
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* rasterizer state is enabled. (Guests can then set it to FALSE,
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* meaning that the first vertex is the provoking vertex, or TRUE,
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* meaning that the last verteix is the provoking vertex.)
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*
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* If this cap is FALSE, then guests should set the provokingVertexLast
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* to FALSE, otherwise rendering behavior is undefined.
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*/
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#define SVGA3D_DEVCAP_DX_PROVOKING_VERTEX 99
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#define SVGA3D_DEVCAP_DXFMT_X8R8G8B8 100
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#define SVGA3D_DEVCAP_DXFMT_A8R8G8B8 101
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#define SVGA3D_DEVCAP_DXFMT_R5G6B5 102
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#define SVGA3D_DEVCAP_DXFMT_X1R5G5B5 103
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#define SVGA3D_DEVCAP_DXFMT_A1R5G5B5 104
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#define SVGA3D_DEVCAP_DXFMT_A4R4G4B4 105
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#define SVGA3D_DEVCAP_DXFMT_Z_D32 106
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#define SVGA3D_DEVCAP_DXFMT_Z_D16 107
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#define SVGA3D_DEVCAP_DXFMT_Z_D24S8 108
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#define SVGA3D_DEVCAP_DXFMT_Z_D15S1 109
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#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8 110
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#define SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4 111
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#define SVGA3D_DEVCAP_DXFMT_LUMINANCE16 112
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#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8 113
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#define SVGA3D_DEVCAP_DXFMT_DXT1 114
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#define SVGA3D_DEVCAP_DXFMT_DXT2 115
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#define SVGA3D_DEVCAP_DXFMT_DXT3 116
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#define SVGA3D_DEVCAP_DXFMT_DXT4 117
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#define SVGA3D_DEVCAP_DXFMT_DXT5 118
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#define SVGA3D_DEVCAP_DXFMT_BUMPU8V8 119
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#define SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 120
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#define SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 121
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#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1 122
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#define SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 123
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#define SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 124
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#define SVGA3D_DEVCAP_DXFMT_A2R10G10B10 125
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#define SVGA3D_DEVCAP_DXFMT_V8U8 126
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#define SVGA3D_DEVCAP_DXFMT_Q8W8V8U8 127
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#define SVGA3D_DEVCAP_DXFMT_CxV8U8 128
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#define SVGA3D_DEVCAP_DXFMT_X8L8V8U8 129
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#define SVGA3D_DEVCAP_DXFMT_A2W10V10U10 130
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#define SVGA3D_DEVCAP_DXFMT_ALPHA8 131
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#define SVGA3D_DEVCAP_DXFMT_R_S10E5 132
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#define SVGA3D_DEVCAP_DXFMT_R_S23E8 133
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#define SVGA3D_DEVCAP_DXFMT_RG_S10E5 134
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#define SVGA3D_DEVCAP_DXFMT_RG_S23E8 135
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#define SVGA3D_DEVCAP_DXFMT_BUFFER 136
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#define SVGA3D_DEVCAP_DXFMT_Z_D24X8 137
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#define SVGA3D_DEVCAP_DXFMT_V16U16 138
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#define SVGA3D_DEVCAP_DXFMT_G16R16 139
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#define SVGA3D_DEVCAP_DXFMT_A16B16G16R16 140
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#define SVGA3D_DEVCAP_DXFMT_UYVY 141
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#define SVGA3D_DEVCAP_DXFMT_YUY2 142
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#define SVGA3D_DEVCAP_DXFMT_NV12 143
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#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2 144
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#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS 145
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#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT 146
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#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT 147
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#define SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS 148
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#define SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT 149
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#define SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT 150
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#define SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT 151
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#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS 152
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#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT 153
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#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM 154
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#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT 155
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#define SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS 156
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#define SVGA3D_DEVCAP_DXFMT_R32G32_UINT 157
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#define SVGA3D_DEVCAP_DXFMT_R32G32_SINT 158
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#define SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS 159
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#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT 160
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#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24 161
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#define SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT 162
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#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS 163
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#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT 164
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#define SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT 165
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#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS 166
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#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM 167
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#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB 168
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#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT 169
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#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT 170
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#define SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS 171
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#define SVGA3D_DEVCAP_DXFMT_R16G16_UINT 172
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#define SVGA3D_DEVCAP_DXFMT_R16G16_SINT 173
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#define SVGA3D_DEVCAP_DXFMT_R32_TYPELESS 174
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#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT 175
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#define SVGA3D_DEVCAP_DXFMT_R32_UINT 176
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#define SVGA3D_DEVCAP_DXFMT_R32_SINT 177
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#define SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS 178
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#define SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT 179
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#define SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8 180
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#define SVGA3D_DEVCAP_DXFMT_X24_G8_UINT 181
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#define SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS 182
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#define SVGA3D_DEVCAP_DXFMT_R8G8_UNORM 183
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#define SVGA3D_DEVCAP_DXFMT_R8G8_UINT 184
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#define SVGA3D_DEVCAP_DXFMT_R8G8_SINT 185
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#define SVGA3D_DEVCAP_DXFMT_R16_TYPELESS 186
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#define SVGA3D_DEVCAP_DXFMT_R16_UNORM 187
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#define SVGA3D_DEVCAP_DXFMT_R16_UINT 188
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#define SVGA3D_DEVCAP_DXFMT_R16_SNORM 189
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#define SVGA3D_DEVCAP_DXFMT_R16_SINT 190
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#define SVGA3D_DEVCAP_DXFMT_R8_TYPELESS 191
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#define SVGA3D_DEVCAP_DXFMT_R8_UNORM 192
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#define SVGA3D_DEVCAP_DXFMT_R8_UINT 193
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#define SVGA3D_DEVCAP_DXFMT_R8_SNORM 194
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#define SVGA3D_DEVCAP_DXFMT_R8_SINT 195
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#define SVGA3D_DEVCAP_DXFMT_P8 196
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#define SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP 197
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#define SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM 198
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#define SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM 199
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#define SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS 200
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#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB 201
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#define SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS 202
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#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB 203
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#define SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS 204
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#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB 205
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#define SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS 206
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#define SVGA3D_DEVCAP_DXFMT_ATI1 207
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#define SVGA3D_DEVCAP_DXFMT_BC4_SNORM 208
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#define SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS 209
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#define SVGA3D_DEVCAP_DXFMT_ATI2 210
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#define SVGA3D_DEVCAP_DXFMT_BC5_SNORM 211
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#define SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM 212
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#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS 213
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#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB 214
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#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS 215
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#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB 216
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#define SVGA3D_DEVCAP_DXFMT_Z_DF16 217
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#define SVGA3D_DEVCAP_DXFMT_Z_DF24 218
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#define SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT 219
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#define SVGA3D_DEVCAP_DXFMT_YV12 220
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#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT 221
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#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT 222
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#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM 223
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#define SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT 224
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#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM 225
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#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM 226
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#define SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT 227
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#define SVGA3D_DEVCAP_DXFMT_R16G16_UNORM 228
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#define SVGA3D_DEVCAP_DXFMT_R16G16_SNORM 229
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#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT 230
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#define SVGA3D_DEVCAP_DXFMT_R8G8_SNORM 231
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#define SVGA3D_DEVCAP_DXFMT_R16_FLOAT 232
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#define SVGA3D_DEVCAP_DXFMT_D16_UNORM 233
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#define SVGA3D_DEVCAP_DXFMT_A8_UNORM 234
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#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM 235
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#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM 236
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#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM 237
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#define SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM 238
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#define SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM 239
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#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM 240
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#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM 241
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#define SVGA3D_DEVCAP_DXFMT_BC4_UNORM 242
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#define SVGA3D_DEVCAP_DXFMT_BC5_UNORM 243
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/*
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* Advertises shaderModel 4.1 support, independent blend-states,
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* cube-map arrays, and a higher vertex input registers limit.
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*
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* (See documentation on SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS.)
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*/
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#define SVGA3D_DEVCAP_SM41 244
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#define SVGA3D_DEVCAP_MULTISAMPLE_2X 245
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#define SVGA3D_DEVCAP_MULTISAMPLE_4X 246
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/*
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* Indicates that the device has rendering support for
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* the full multisample quality. If this cap is not present,
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* the host may or may not support full quality rendering.
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*
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* See also SVGA_REG_MS_HINT_RESOLVED.
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*/
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#define SVGA3D_DEVCAP_MS_FULL_QUALITY 247
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/*
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* Advertises support for the SVGA3D LogicOps commands.
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*/
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#define SVGA3D_DEVCAP_LOGICOPS 248
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/*
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* Advertises support for using logicOps in the DXBlendStates.
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*/
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#define SVGA3D_DEVCAP_LOGIC_BLENDOPS 249
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/*
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* Note DXFMT range is now non-contiguous.
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*/
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#define SVGA3D_DEVCAP_RESERVED_1 250
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#define SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS 251
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#define SVGA3D_DEVCAP_DXFMT_BC6H_UF16 252
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#define SVGA3D_DEVCAP_DXFMT_BC6H_SF16 253
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#define SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS 254
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#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM 255
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#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB 256
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#define SVGA3D_DEVCAP_RESERVED_2 257
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#define SVGA3D_DEVCAP_SM5 258
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|
#define SVGA3D_DEVCAP_MULTISAMPLE_8X 259
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|
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/* This must be the last index. */
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#define SVGA3D_DEVCAP_MAX 260
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/*
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* Bit definitions for DXFMT devcaps
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*
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*
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* SUPPORTED: Can the format be defined?
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* SHADER_SAMPLE: Can the format be sampled from a shader?
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* COLOR_RENDERTARGET: Can the format be a color render target?
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* DEPTH_RENDERTARGET: Can the format be a depth render target?
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* BLENDABLE: Is the format blendable?
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* MIPS: Does the format support mip levels?
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|
* ARRAY: Does the format support texture arrays?
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* VOLUME: Does the format support having volume?
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* MULTISAMPLE: Does the format support multisample?
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|
*/
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#define SVGA3D_DXFMT_SUPPORTED (1 << 0)
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#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1)
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#define SVGA3D_DXFMT_COLOR_RENDERTARGET (1 << 2)
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#define SVGA3D_DXFMT_DEPTH_RENDERTARGET (1 << 3)
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#define SVGA3D_DXFMT_BLENDABLE (1 << 4)
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#define SVGA3D_DXFMT_MIPS (1 << 5)
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#define SVGA3D_DXFMT_ARRAY (1 << 6)
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#define SVGA3D_DXFMT_VOLUME (1 << 7)
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#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8)
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#define SVGA3D_DXFMT_MULTISAMPLE (1 << 9)
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#define SVGA3D_DXFMT_MAX (1 << 10)
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typedef union {
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SVGA3dBool b;
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uint32 u;
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int32 i;
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|
float f;
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} SVGA3dDevCapResult;
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#endif /* _SVGA3D_DEVCAPS_H_ */
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