mirror of https://gitee.com/openkylin/linux.git
54 lines
1.3 KiB
Plaintext
54 lines
1.3 KiB
Plaintext
Ingenic SoC CGU binding
|
|
|
|
The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
|
|
typically includes a variety of PLLs, multiplexers, dividers & gates in order
|
|
to provide many different clock signals derived from only 2 external source
|
|
clocks.
|
|
|
|
Required properties:
|
|
- compatible : Should be "ingenic,<soctype>-cgu".
|
|
For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu".
|
|
- reg : The address & length of the CGU registers.
|
|
- clocks : List of phandle & clock specifiers for clocks external to the CGU.
|
|
Two such external clocks should be specified - first the external crystal
|
|
"ext" and second the RTC clock source "rtc".
|
|
- clock-names : List of name strings for the external clocks.
|
|
- #clock-cells: Should be 1.
|
|
Clock consumers specify this argument to identify a clock. The valid values
|
|
may be found in <dt-bindings/clock/<soctype>-cgu.h>.
|
|
|
|
Example SoC include file:
|
|
|
|
/ {
|
|
cgu: jz4740-cgu {
|
|
compatible = "ingenic,jz4740-cgu";
|
|
reg = <0x10000000 0x100>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
uart0: serial@10030000 {
|
|
clocks = <&cgu JZ4740_CLK_UART0>;
|
|
};
|
|
};
|
|
|
|
Example board file:
|
|
|
|
/ {
|
|
ext: clock@0 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <12000000>;
|
|
};
|
|
|
|
rtc: clock@1 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
&cgu {
|
|
clocks = <&ext> <&rtc>;
|
|
clock-names: "ext", "rtc";
|
|
};
|
|
};
|