mirror of https://gitee.com/openkylin/linux.git
124 lines
4.4 KiB
Plaintext
124 lines
4.4 KiB
Plaintext
Imagination Technologies Pistachio SoC clock controllers
|
|
========================================================
|
|
|
|
Pistachio has four clock controllers (core clock, peripheral clock, peripheral
|
|
general control, and top general control) which are instantiated individually
|
|
from the device-tree.
|
|
|
|
External clocks:
|
|
----------------
|
|
|
|
There are three external inputs to the clock controllers which should be
|
|
defined with the following clock-output-names:
|
|
- "xtal": External 52Mhz oscillator (required)
|
|
- "audio_clk_in": Alternate audio reference clock (optional)
|
|
- "enet_clk_in": Alternate ethernet PHY clock (optional)
|
|
|
|
Core clock controller:
|
|
----------------------
|
|
|
|
The core clock controller generates clocks for the CPU, RPU (WiFi + BT
|
|
co-processor), audio, and several peripherals.
|
|
|
|
Required properties:
|
|
- compatible: Must be "img,pistachio-clk".
|
|
- reg: Must contain the base address and length of the core clock controller.
|
|
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
|
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
|
- clocks: Must contain an entry for each clock in clock-names.
|
|
- clock-names: Must include "xtal" (see "External clocks") and
|
|
"audio_clk_in_gate", "enet_clk_in_gate" which are generated by the
|
|
top-level general control.
|
|
|
|
Example:
|
|
clk_core: clock-controller@18144000 {
|
|
compatible = "img,pistachio-clk";
|
|
reg = <0x18144000 0x800>;
|
|
clocks = <&xtal>, <&cr_top EXT_CLK_AUDIO_IN>,
|
|
<&cr_top EXT_CLK_ENET_IN>;
|
|
clock-names = "xtal", "audio_clk_in_gate", "enet_clk_in_gate";
|
|
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
Peripheral clock controller:
|
|
----------------------------
|
|
|
|
The peripheral clock controller generates clocks for the DDR, ROM, and other
|
|
peripherals. The peripheral system clock ("periph_sys") generated by the core
|
|
clock controller is the input clock to the peripheral clock controller.
|
|
|
|
Required properties:
|
|
- compatible: Must be "img,pistachio-periph-clk".
|
|
- reg: Must contain the base address and length of the peripheral clock
|
|
controller.
|
|
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
|
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
|
- clocks: Must contain an entry for each clock in clock-names.
|
|
- clock-names: Must include "periph_sys", the peripheral system clock generated
|
|
by the core clock controller.
|
|
|
|
Example:
|
|
clk_periph: clock-controller@18144800 {
|
|
compatible = "img,pistachio-clk-periph";
|
|
reg = <0x18144800 0x800>;
|
|
clocks = <&clk_core CLK_PERIPH_SYS>;
|
|
clock-names = "periph_sys";
|
|
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
Peripheral general control:
|
|
---------------------------
|
|
|
|
The peripheral general control block generates system interface clocks and
|
|
resets for various peripherals. It also contains miscellaneous peripheral
|
|
control registers. The system clock ("sys") generated by the peripheral clock
|
|
controller is the input clock to the system clock controller.
|
|
|
|
Required properties:
|
|
- compatible: Must include "img,pistachio-periph-cr" and "syscon".
|
|
- reg: Must contain the base address and length of the peripheral general
|
|
control registers.
|
|
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
|
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
|
- clocks: Must contain an entry for each clock in clock-names.
|
|
- clock-names: Must include "sys", the system clock generated by the peripheral
|
|
clock controller.
|
|
|
|
Example:
|
|
cr_periph: syscon@18144800 {
|
|
compatible = "img,pistachio-cr-periph", "syscon";
|
|
reg = <0x18148000 0x1000>;
|
|
clocks = <&clock_periph PERIPH_CLK_PERIPH_SYS>;
|
|
clock-names = "sys";
|
|
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
Top-level general control:
|
|
--------------------------
|
|
|
|
The top-level general control block contains miscellaneous control registers and
|
|
gates for the external clocks "audio_clk_in" and "enet_clk_in".
|
|
|
|
Required properties:
|
|
- compatible: Must include "img,pistachio-cr-top" and "syscon".
|
|
- reg: Must contain the base address and length of the top-level
|
|
control registers.
|
|
- clocks: Must contain an entry for each clock in clock-names.
|
|
- clock-names: Two optional clocks, "audio_clk_in" and "enet_clk_in" (see
|
|
"External clocks").
|
|
- #clock-cells: Must be 1. The single cell is the clock identifier.
|
|
See dt-bindings/clock/pistachio-clk.h for the list of valid identifiers.
|
|
|
|
Example:
|
|
cr_top: syscon@18144800 {
|
|
compatible = "img,pistachio-cr-top", "syscon";
|
|
reg = <0x18149000 0x200>;
|
|
clocks = <&audio_refclk>, <&ext_enet_in>;
|
|
clock-names = "audio_clk_in", "enet_clk_in";
|
|
|
|
#clock-cells = <1>;
|
|
};
|