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118 lines
3.7 KiB
Plaintext
118 lines
3.7 KiB
Plaintext
Binding for TI divider clock
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Binding status: Unstable - ABI compatibility may be broken in the future
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This binding uses the common clock binding[1]. It assumes a
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register-mapped adjustable clock rate divider that does not gate and has
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only one input clock or parent. By default the value programmed into
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the register is one less than the actual divisor value. E.g:
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register value actual divisor value
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0 1
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1 2
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2 3
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This assumption may be modified by the following optional properties:
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ti,index-starts-at-one - valid divisor values start at 1, not the default
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of 0. E.g:
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register value actual divisor value
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1 1
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2 2
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3 3
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ti,index-power-of-two - valid divisor values are powers of two. E.g:
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register value actual divisor value
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0 1
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1 2
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2 4
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Additionally an array of valid dividers may be supplied like so:
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ti,dividers = <4>, <8>, <0>, <16>;
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Which will map the resulting values to a divisor table by their index:
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register value actual divisor value
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0 4
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1 8
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2 <invalid divisor, skipped>
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3 16
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Any zero value in this array means the corresponding bit-value is invalid
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and must not be used.
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The binding must also provide the register to control the divider and
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unless the divider array is provided, min and max dividers. Optionally
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the number of bits to shift that mask, if necessary. If the shift value
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is missing it is the same as supplying a zero shift.
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This binding can also optionally provide support to the hardware autoidle
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feature, see [2].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
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Required properties:
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- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
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- #clock-cells : from common clock binding; shall be set to 0.
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- clocks : link to phandle of parent clock
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- reg : offset for register controlling adjustable divider
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Optional properties:
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- clock-output-names : from common clock binding.
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- ti,dividers : array of integers defining divisors
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- ti,bit-shift : number of bits to shift the divider value, defaults to 0
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- ti,min-div : min divisor for dividing the input clock rate, only
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needed if the first divisor is offset from the default value (1)
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- ti,max-div : max divisor for dividing the input clock rate, only needed
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if ti,dividers is not defined.
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- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
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only valid if ti,dividers is not defined.
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- ti,index-power-of-two : valid divisor programming must be a power of two,
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only valid if ti,dividers is not defined.
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- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
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see [2]
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- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
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see [2]
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- ti,set-rate-parent : clk_set_rate is propagated to parent
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- ti,latch-bit : latch the divider value to HW, only needed if the register
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access requires this. As an example dra76x DPLL_GMAC H14 divider implements
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such behavior.
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Examples:
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dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_usb_ck>;
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ti,max-div = <127>;
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reg = <0x190>;
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ti,index-starts-at-one;
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};
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aess_fclk: aess_fclk@4a004528 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&abe_clk>;
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ti,bit-shift = <24>;
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reg = <0x528>;
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ti,max-div = <2>;
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};
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dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <31>;
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reg = <0x0134>;
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ti,index-starts-at-one;
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};
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ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&corex2_fck>;
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ti,bit-shift = <8>;
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reg = <0x0a40>;
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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};
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