mirror of https://gitee.com/openkylin/linux.git
523 lines
17 KiB
C
523 lines
17 KiB
C
/*
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* B53 register definitions
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*
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* Copyright (C) 2004 Broadcom Corporation
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* Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __B53_REGS_H
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#define __B53_REGS_H
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/* Management Port (SMP) Page offsets */
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#define B53_CTRL_PAGE 0x00 /* Control */
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#define B53_STAT_PAGE 0x01 /* Status */
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#define B53_MGMT_PAGE 0x02 /* Management Mode */
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#define B53_MIB_AC_PAGE 0x03 /* MIB Autocast */
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#define B53_ARLCTRL_PAGE 0x04 /* ARL Control */
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#define B53_ARLIO_PAGE 0x05 /* ARL Access */
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#define B53_FRAMEBUF_PAGE 0x06 /* Management frame access */
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#define B53_MEM_ACCESS_PAGE 0x08 /* Memory access */
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/* PHY Registers */
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#define B53_PORT_MII_PAGE(i) (0x10 + (i)) /* Port i MII Registers */
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#define B53_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */
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#define B53_ALL_PORT_PAGE 0x19 /* All ports MII (broadcast) */
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/* MIB registers */
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#define B53_MIB_PAGE(i) (0x20 + (i))
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/* Quality of Service (QoS) Registers */
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#define B53_QOS_PAGE 0x30
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/* Port VLAN Page */
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#define B53_PVLAN_PAGE 0x31
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/* VLAN Registers */
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#define B53_VLAN_PAGE 0x34
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/* Jumbo Frame Registers */
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#define B53_JUMBO_PAGE 0x40
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/* EEE Control Registers Page */
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#define B53_EEE_PAGE 0x92
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/* CFP Configuration Registers Page */
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#define B53_CFP_PAGE 0xa1
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/*************************************************************************
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* Control Page registers
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*************************************************************************/
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/* Port Control Register (8 bit) */
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#define B53_PORT_CTRL(i) (0x00 + (i))
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#define PORT_CTRL_RX_DISABLE BIT(0)
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#define PORT_CTRL_TX_DISABLE BIT(1)
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#define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
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#define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
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#define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
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#define PORT_CTRL_STP_STATE_S 5
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#define PORT_CTRL_NO_STP (0 << PORT_CTRL_STP_STATE_S)
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#define PORT_CTRL_DIS_STATE (1 << PORT_CTRL_STP_STATE_S)
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#define PORT_CTRL_BLOCK_STATE (2 << PORT_CTRL_STP_STATE_S)
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#define PORT_CTRL_LISTEN_STATE (3 << PORT_CTRL_STP_STATE_S)
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#define PORT_CTRL_LEARN_STATE (4 << PORT_CTRL_STP_STATE_S)
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#define PORT_CTRL_FWD_STATE (5 << PORT_CTRL_STP_STATE_S)
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#define PORT_CTRL_STP_STATE_MASK (0x7 << PORT_CTRL_STP_STATE_S)
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/* SMP Control Register (8 bit) */
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#define B53_SMP_CTRL 0x0a
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/* Switch Mode Control Register (8 bit) */
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#define B53_SWITCH_MODE 0x0b
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#define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */
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#define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */
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/* IMP Port state override register (8 bit) */
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#define B53_PORT_OVERRIDE_CTRL 0x0e
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#define PORT_OVERRIDE_LINK BIT(0)
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#define PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
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#define PORT_OVERRIDE_SPEED_S 2
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#define PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S)
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#define PORT_OVERRIDE_SPEED_100M (1 << PORT_OVERRIDE_SPEED_S)
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#define PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S)
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#define PORT_OVERRIDE_RV_MII_25 BIT(4) /* BCM5325 only */
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#define PORT_OVERRIDE_RX_FLOW BIT(4)
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#define PORT_OVERRIDE_TX_FLOW BIT(5)
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#define PORT_OVERRIDE_SPEED_2000M BIT(6) /* BCM5301X only, requires setting 1000M */
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#define PORT_OVERRIDE_EN BIT(7) /* Use the register contents */
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/* Power-down mode control */
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#define B53_PD_MODE_CTRL_25 0x0f
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/* IP Multicast control (8 bit) */
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#define B53_IP_MULTICAST_CTRL 0x21
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#define B53_IPMC_FWD_EN BIT(1)
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#define B53_UC_FWD_EN BIT(6)
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#define B53_MC_FWD_EN BIT(7)
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/* Switch control (8 bit) */
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#define B53_SWITCH_CTRL 0x22
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#define B53_MII_DUMB_FWDG_EN BIT(6)
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/* (16 bit) */
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#define B53_UC_FLOOD_MASK 0x32
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#define B53_MC_FLOOD_MASK 0x34
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#define B53_IPMC_FLOOD_MASK 0x36
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/*
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* Override Ports 0-7 State on devices with xMII interfaces (8 bit)
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*
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* For port 8 still use B53_PORT_OVERRIDE_CTRL
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* Please note that not all ports are available on every hardware, e.g. BCM5301X
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* don't include overriding port 6, BCM63xx also have some limitations.
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*/
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#define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + (i))
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#define GMII_PO_LINK BIT(0)
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#define GMII_PO_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
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#define GMII_PO_SPEED_S 2
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#define GMII_PO_SPEED_10M (0 << GMII_PO_SPEED_S)
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#define GMII_PO_SPEED_100M (1 << GMII_PO_SPEED_S)
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#define GMII_PO_SPEED_1000M (2 << GMII_PO_SPEED_S)
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#define GMII_PO_RX_FLOW BIT(4)
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#define GMII_PO_TX_FLOW BIT(5)
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#define GMII_PO_EN BIT(6) /* Use the register contents */
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#define GMII_PO_SPEED_2000M BIT(7) /* BCM5301X only, requires setting 1000M */
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#define B53_RGMII_CTRL_IMP 0x60
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#define RGMII_CTRL_ENABLE_GMII BIT(7)
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#define RGMII_CTRL_TIMING_SEL BIT(2)
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#define RGMII_CTRL_DLL_RXC BIT(1)
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#define RGMII_CTRL_DLL_TXC BIT(0)
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#define B53_RGMII_CTRL_P(i) (B53_RGMII_CTRL_IMP + (i))
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/* Software reset register (8 bit) */
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#define B53_SOFTRESET 0x79
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#define SW_RST BIT(7)
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#define EN_CH_RST BIT(6)
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#define EN_SW_RST BIT(4)
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/* Fast Aging Control register (8 bit) */
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#define B53_FAST_AGE_CTRL 0x88
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#define FAST_AGE_STATIC BIT(0)
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#define FAST_AGE_DYNAMIC BIT(1)
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#define FAST_AGE_PORT BIT(2)
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#define FAST_AGE_VLAN BIT(3)
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#define FAST_AGE_STP BIT(4)
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#define FAST_AGE_MC BIT(5)
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#define FAST_AGE_DONE BIT(7)
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/* Fast Aging Port Control register (8 bit) */
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#define B53_FAST_AGE_PORT_CTRL 0x89
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/* Fast Aging VID Control register (16 bit) */
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#define B53_FAST_AGE_VID_CTRL 0x8a
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/*************************************************************************
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* Status Page registers
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*************************************************************************/
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/* Link Status Summary Register (16bit) */
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#define B53_LINK_STAT 0x00
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/* Link Status Change Register (16 bit) */
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#define B53_LINK_STAT_CHANGE 0x02
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/* Port Speed Summary Register (16 bit for FE, 32 bit for GE) */
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#define B53_SPEED_STAT 0x04
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#define SPEED_PORT_FE(reg, port) (((reg) >> (port)) & 1)
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#define SPEED_PORT_GE(reg, port) (((reg) >> 2 * (port)) & 3)
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#define SPEED_STAT_10M 0
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#define SPEED_STAT_100M 1
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#define SPEED_STAT_1000M 2
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/* Duplex Status Summary (16 bit) */
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#define B53_DUPLEX_STAT_FE 0x06
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#define B53_DUPLEX_STAT_GE 0x08
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#define B53_DUPLEX_STAT_63XX 0x0c
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/* Revision ID register for BCM5325 */
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#define B53_REV_ID_25 0x50
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/* Strap Value (48 bit) */
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#define B53_STRAP_VALUE 0x70
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#define SV_GMII_CTRL_115 BIT(27)
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/*************************************************************************
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* Management Mode Page Registers
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*************************************************************************/
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/* Global Management Config Register (8 bit) */
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#define B53_GLOBAL_CONFIG 0x00
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#define GC_RESET_MIB 0x01
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#define GC_RX_BPDU_EN 0x02
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#define GC_MIB_AC_HDR_EN 0x10
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#define GC_MIB_AC_EN 0x20
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#define GC_FRM_MGMT_PORT_M 0xC0
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#define GC_FRM_MGMT_PORT_04 0x00
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#define GC_FRM_MGMT_PORT_MII 0x80
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/* Broadcom Header control register (8 bit) */
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#define B53_BRCM_HDR 0x03
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#define BRCM_HDR_P8_EN BIT(0) /* Enable tagging on port 8 */
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#define BRCM_HDR_P5_EN BIT(1) /* Enable tagging on port 5 */
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#define BRCM_HDR_P7_EN BIT(2) /* Enable tagging on port 7 */
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/* Mirror capture control register (16 bit) */
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#define B53_MIR_CAP_CTL 0x10
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#define CAP_PORT_MASK 0xf
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#define BLK_NOT_MIR BIT(14)
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#define MIRROR_EN BIT(15)
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/* Ingress mirror control register (16 bit) */
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#define B53_IG_MIR_CTL 0x12
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#define MIRROR_MASK 0x1ff
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#define DIV_EN BIT(13)
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#define MIRROR_FILTER_MASK 0x3
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#define MIRROR_FILTER_SHIFT 14
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#define MIRROR_ALL 0
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#define MIRROR_DA 1
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#define MIRROR_SA 2
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/* Ingress mirror divider register (16 bit) */
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#define B53_IG_MIR_DIV 0x14
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#define IN_MIRROR_DIV_MASK 0x3ff
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/* Ingress mirror MAC address register (48 bit) */
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#define B53_IG_MIR_MAC 0x16
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/* Egress mirror control register (16 bit) */
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#define B53_EG_MIR_CTL 0x1C
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/* Egress mirror divider register (16 bit) */
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#define B53_EG_MIR_DIV 0x1E
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/* Egress mirror MAC address register (48 bit) */
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#define B53_EG_MIR_MAC 0x20
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/* Device ID register (8 or 32 bit) */
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#define B53_DEVICE_ID 0x30
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/* Revision ID register (8 bit) */
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#define B53_REV_ID 0x40
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/* Broadcom header RX control (16 bit) */
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#define B53_BRCM_HDR_RX_DIS 0x60
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/* Broadcom header TX control (16 bit) */
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#define B53_BRCM_HDR_TX_DIS 0x62
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/*************************************************************************
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* ARL Access Page Registers
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*************************************************************************/
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/* VLAN Table Access Register (8 bit) */
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#define B53_VT_ACCESS 0x80
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#define B53_VT_ACCESS_9798 0x60 /* for BCM5397/BCM5398 */
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#define B53_VT_ACCESS_63XX 0x60 /* for BCM6328/62/68 */
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#define VTA_CMD_WRITE 0
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#define VTA_CMD_READ 1
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#define VTA_CMD_CLEAR 2
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#define VTA_START_CMD BIT(7)
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/* VLAN Table Index Register (16 bit) */
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#define B53_VT_INDEX 0x81
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#define B53_VT_INDEX_9798 0x61
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#define B53_VT_INDEX_63XX 0x62
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/* VLAN Table Entry Register (32 bit) */
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#define B53_VT_ENTRY 0x83
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#define B53_VT_ENTRY_9798 0x63
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#define B53_VT_ENTRY_63XX 0x64
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#define VTE_MEMBERS 0x1ff
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#define VTE_UNTAG_S 9
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#define VTE_UNTAG (0x1ff << 9)
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/*************************************************************************
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* ARL I/O Registers
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*************************************************************************/
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/* ARL Table Read/Write Register (8 bit) */
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#define B53_ARLTBL_RW_CTRL 0x00
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#define ARLTBL_RW BIT(0)
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#define ARLTBL_START_DONE BIT(7)
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/* MAC Address Index Register (48 bit) */
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#define B53_MAC_ADDR_IDX 0x02
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/* VLAN ID Index Register (16 bit) */
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#define B53_VLAN_ID_IDX 0x08
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/* ARL Table MAC/VID Entry N Registers (64 bit)
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*
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* BCM5325 and BCM5365 share most definitions below
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*/
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#define B53_ARLTBL_MAC_VID_ENTRY(n) (0x10 * (n))
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#define ARLTBL_MAC_MASK 0xffffffffffffULL
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#define ARLTBL_VID_S 48
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#define ARLTBL_VID_MASK_25 0xff
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#define ARLTBL_VID_MASK 0xfff
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#define ARLTBL_DATA_PORT_ID_S_25 48
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#define ARLTBL_DATA_PORT_ID_MASK_25 0xf
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#define ARLTBL_AGE_25 BIT(61)
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#define ARLTBL_STATIC_25 BIT(62)
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#define ARLTBL_VALID_25 BIT(63)
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/* ARL Table Data Entry N Registers (32 bit) */
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#define B53_ARLTBL_DATA_ENTRY(n) ((0x10 * (n)) + 0x08)
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#define ARLTBL_DATA_PORT_ID_MASK 0x1ff
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#define ARLTBL_TC(tc) ((3 & tc) << 11)
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#define ARLTBL_AGE BIT(14)
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#define ARLTBL_STATIC BIT(15)
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#define ARLTBL_VALID BIT(16)
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/* ARL Search Control Register (8 bit) */
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#define B53_ARL_SRCH_CTL 0x50
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#define B53_ARL_SRCH_CTL_25 0x20
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#define ARL_SRCH_VLID BIT(0)
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#define ARL_SRCH_STDN BIT(7)
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/* ARL Search Address Register (16 bit) */
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#define B53_ARL_SRCH_ADDR 0x51
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#define B53_ARL_SRCH_ADDR_25 0x22
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#define B53_ARL_SRCH_ADDR_65 0x24
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#define ARL_ADDR_MASK GENMASK(14, 0)
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/* ARL Search MAC/VID Result (64 bit) */
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#define B53_ARL_SRCH_RSTL_0_MACVID 0x60
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/* Single register search result on 5325 */
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#define B53_ARL_SRCH_RSTL_0_MACVID_25 0x24
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/* Single register search result on 5365 */
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#define B53_ARL_SRCH_RSTL_0_MACVID_65 0x30
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/* ARL Search Data Result (32 bit) */
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#define B53_ARL_SRCH_RSTL_0 0x68
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#define B53_ARL_SRCH_RSTL_MACVID(x) (B53_ARL_SRCH_RSTL_0_MACVID + ((x) * 0x10))
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#define B53_ARL_SRCH_RSTL(x) (B53_ARL_SRCH_RSTL_0 + ((x) * 0x10))
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/*************************************************************************
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* Port VLAN Registers
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*************************************************************************/
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/* Port VLAN mask (16 bit) IMP port is always 8, also on 5325 & co */
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#define B53_PVLAN_PORT_MASK(i) ((i) * 2)
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/* Join all VLANs register (16 bit) */
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#define B53_JOIN_ALL_VLAN_EN 0x50
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/*************************************************************************
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* 802.1Q Page Registers
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*************************************************************************/
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/* Global QoS Control (8 bit) */
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#define B53_QOS_GLOBAL_CTL 0x00
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/* Enable 802.1Q for individual Ports (16 bit) */
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#define B53_802_1P_EN 0x04
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/*************************************************************************
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* VLAN Page Registers
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*************************************************************************/
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/* VLAN Control 0 (8 bit) */
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#define B53_VLAN_CTRL0 0x00
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#define VC0_8021PF_CTRL_MASK 0x3
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#define VC0_8021PF_CTRL_NONE 0x0
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#define VC0_8021PF_CTRL_CHANGE_PRI 0x1
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#define VC0_8021PF_CTRL_CHANGE_VID 0x2
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#define VC0_8021PF_CTRL_CHANGE_BOTH 0x3
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#define VC0_8021QF_CTRL_MASK 0xc
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#define VC0_8021QF_CTRL_CHANGE_PRI 0x1
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#define VC0_8021QF_CTRL_CHANGE_VID 0x2
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#define VC0_8021QF_CTRL_CHANGE_BOTH 0x3
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#define VC0_RESERVED_1 BIT(1)
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#define VC0_DROP_VID_MISS BIT(4)
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#define VC0_VID_HASH_VID BIT(5)
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#define VC0_VID_CHK_EN BIT(6) /* Use VID,DA or VID,SA */
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#define VC0_VLAN_EN BIT(7) /* 802.1Q VLAN Enabled */
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/* VLAN Control 1 (8 bit) */
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#define B53_VLAN_CTRL1 0x01
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#define VC1_RX_MCST_TAG_EN BIT(1)
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#define VC1_RX_MCST_FWD_EN BIT(2)
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#define VC1_RX_MCST_UNTAG_EN BIT(3)
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/* VLAN Control 2 (8 bit) */
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#define B53_VLAN_CTRL2 0x02
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/* VLAN Control 3 (8 bit when BCM5325, 16 bit else) */
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#define B53_VLAN_CTRL3 0x03
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#define B53_VLAN_CTRL3_63XX 0x04
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#define VC3_MAXSIZE_1532 BIT(6) /* 5325 only */
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#define VC3_HIGH_8BIT_EN BIT(7) /* 5325 only */
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/* VLAN Control 4 (8 bit) */
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#define B53_VLAN_CTRL4 0x05
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#define B53_VLAN_CTRL4_25 0x04
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#define B53_VLAN_CTRL4_63XX 0x06
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#define VC4_ING_VID_CHECK_S 6
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#define VC4_ING_VID_CHECK_MASK (0x3 << VC4_ING_VID_CHECK_S)
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#define VC4_ING_VID_VIO_FWD 0 /* forward, but do not learn */
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#define VC4_ING_VID_VIO_DROP 1 /* drop VID violations */
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#define VC4_NO_ING_VID_CHK 2 /* do not check */
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#define VC4_ING_VID_VIO_TO_IMP 3 /* redirect to MII port */
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/* VLAN Control 5 (8 bit) */
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#define B53_VLAN_CTRL5 0x06
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#define B53_VLAN_CTRL5_25 0x05
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#define B53_VLAN_CTRL5_63XX 0x07
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#define VC5_VID_FFF_EN BIT(2)
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#define VC5_DROP_VTABLE_MISS BIT(3)
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/* VLAN Control 6 (8 bit) */
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#define B53_VLAN_CTRL6 0x07
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#define B53_VLAN_CTRL6_63XX 0x08
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/* VLAN Table Access Register (16 bit) */
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#define B53_VLAN_TABLE_ACCESS_25 0x06 /* BCM5325E/5350 */
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#define B53_VLAN_TABLE_ACCESS_65 0x08 /* BCM5365 */
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#define VTA_VID_LOW_MASK_25 0xf
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#define VTA_VID_LOW_MASK_65 0xff
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#define VTA_VID_HIGH_S_25 4
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#define VTA_VID_HIGH_S_65 8
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#define VTA_VID_HIGH_MASK_25 (0xff << VTA_VID_HIGH_S_25E)
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#define VTA_VID_HIGH_MASK_65 (0xf << VTA_VID_HIGH_S_65)
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#define VTA_RW_STATE BIT(12)
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#define VTA_RW_STATE_RD 0
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#define VTA_RW_STATE_WR BIT(12)
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#define VTA_RW_OP_EN BIT(13)
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/* VLAN Read/Write Registers for (16/32 bit) */
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#define B53_VLAN_WRITE_25 0x08
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#define B53_VLAN_WRITE_65 0x0a
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#define B53_VLAN_READ 0x0c
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#define VA_MEMBER_MASK 0x3f
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#define VA_UNTAG_S_25 6
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#define VA_UNTAG_MASK_25 0x3f
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#define VA_UNTAG_S_65 7
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#define VA_UNTAG_MASK_65 0x1f
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#define VA_VID_HIGH_S 12
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#define VA_VID_HIGH_MASK (0xffff << VA_VID_HIGH_S)
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#define VA_VALID_25 BIT(20)
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#define VA_VALID_25_R4 BIT(24)
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#define VA_VALID_65 BIT(14)
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/* VLAN Port Default Tag (16 bit) */
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#define B53_VLAN_PORT_DEF_TAG(i) (0x10 + 2 * (i))
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/*************************************************************************
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* Jumbo Frame Page Registers
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*************************************************************************/
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/* Jumbo Enable Port Mask (bit i == port i enabled) (32 bit) */
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#define B53_JUMBO_PORT_MASK 0x01
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#define B53_JUMBO_PORT_MASK_63XX 0x04
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#define JPM_10_100_JUMBO_EN BIT(24) /* GigE always enabled */
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/* Good Frame Max Size without 802.1Q TAG (16 bit) */
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#define B53_JUMBO_MAX_SIZE 0x05
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#define B53_JUMBO_MAX_SIZE_63XX 0x08
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#define JMS_MIN_SIZE 1518
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#define JMS_MAX_SIZE 9724
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/*************************************************************************
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* EEE Configuration Page Registers
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*************************************************************************/
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/* EEE Enable control register (16 bit) */
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#define B53_EEE_EN_CTRL 0x00
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/* EEE LPI assert status register (16 bit) */
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#define B53_EEE_LPI_ASSERT_STS 0x02
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/* EEE LPI indicate status register (16 bit) */
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#define B53_EEE_LPI_INDICATE 0x4
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/* EEE Receiving idle symbols status register (16 bit) */
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#define B53_EEE_RX_IDLE_SYM_STS 0x6
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/* EEE Pipeline timer register (32 bit) */
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#define B53_EEE_PIP_TIMER 0xC
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/* EEE Sleep timer Gig register (32 bit) */
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#define B53_EEE_SLEEP_TIMER_GIG(i) (0x10 + 4 * (i))
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/* EEE Sleep timer FE register (32 bit) */
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#define B53_EEE_SLEEP_TIMER_FE(i) (0x34 + 4 * (i))
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/* EEE Minimum LP timer Gig register (32 bit) */
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#define B53_EEE_MIN_LP_TIMER_GIG(i) (0x58 + 4 * (i))
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/* EEE Minimum LP timer FE register (32 bit) */
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#define B53_EEE_MIN_LP_TIMER_FE(i) (0x7c + 4 * (i))
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/* EEE Wake timer Gig register (16 bit) */
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#define B53_EEE_WAKE_TIMER_GIG(i) (0xa0 + 2 * (i))
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/* EEE Wake timer FE register (16 bit) */
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#define B53_EEE_WAKE_TIMER_FE(i) (0xb2 + 2 * (i))
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/*************************************************************************
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* CFP Configuration Page Registers
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*************************************************************************/
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/* CFP Control Register with ports map (8 bit) */
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#define B53_CFP_CTRL 0x00
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#endif /* !__B53_REGS_H */
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