mirror of https://gitee.com/openkylin/linux.git
578 lines
19 KiB
C
578 lines
19 KiB
C
/*
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* This file contains the functions and defines necessary to modify and
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* use the SuperH page table tree.
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*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2002 - 2005 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of this
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* archive for more details.
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*/
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#ifndef __ASM_SH_PGTABLE_H
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#define __ASM_SH_PGTABLE_H
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#include <asm-generic/pgtable-nopmd.h>
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#include <asm/page.h>
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#ifndef __ASSEMBLY__
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#include <asm/addrspace.h>
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#include <asm/fixmap.h>
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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#endif /* !__ASSEMBLY__ */
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/*
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* traditional two-level paging structure
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*/
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/* PTE bits */
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#ifdef CONFIG_X2TLB
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# define PTE_MAGNITUDE 3 /* 64-bit PTEs on extended mode SH-X2 TLB */
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#else
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# define PTE_MAGNITUDE 2 /* 32-bit PTEs */
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#endif
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#define PTE_SHIFT PAGE_SHIFT
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#define PTE_BITS (PTE_SHIFT - PTE_MAGNITUDE)
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/* PGD bits */
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#define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
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#define PGDIR_BITS (32 - PGDIR_SHIFT)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/* Entries per level */
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#define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE))
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#define PTRS_PER_PGD (PAGE_SIZE / 4)
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#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
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#define FIRST_USER_ADDRESS 0
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#define PTE_PHYS_MASK (0x20000000 - PAGE_SIZE)
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#define VMALLOC_START (P3SEG)
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#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
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/*
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* Linux PTEL encoding.
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*
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* Hardware and software bit definitions for the PTEL value (see below for
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* notes on SH-X2 MMUs and 64-bit PTEs):
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*
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* - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4).
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*
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* - Bit 1 is the SH-bit, but is unused on SH-3 due to an MMU bug (the
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* hardware PTEL value can't have the SH-bit set when MMUCR.IX is set,
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* which is the default in cpu-sh3/mmu_context.h:MMU_CONTROL_INIT).
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*
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* In order to keep this relatively clean, do not use these for defining
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* SH-3 specific flags until all of the other unused bits have been
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* exhausted.
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*
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* - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE.
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*
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* - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages.
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* Bit 10 is used for _PAGE_ACCESSED, bit 11 remains unused.
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*
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* - Bits 31, 30, and 29 remain unused by everyone and can be used for future
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* software flags, although care must be taken to update _PAGE_CLEAR_FLAGS.
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*
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* XXX: Leave the _PAGE_FILE and _PAGE_WT overhaul for a rainy day.
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*
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* SH-X2 MMUs and extended PTEs
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*
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* SH-X2 supports an extended mode TLB with split data arrays due to the
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* number of bits needed for PR and SZ (now EPR and ESZ) encodings. The PR and
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* SZ bit placeholders still exist in data array 1, but are implemented as
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* reserved bits, with the real logic existing in data array 2.
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*
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* The downside to this is that we can no longer fit everything in to a 32-bit
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* PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus
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* side, this gives us quite a few spare bits to play with for future usage.
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*/
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/* Legacy and compat mode bits */
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#define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */
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#define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */
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#define _PAGE_DIRTY 0x004 /* D-bit : page changed */
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#define _PAGE_CACHABLE 0x008 /* C-bit : cachable */
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#ifndef CONFIG_X2TLB
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# define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */
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# define _PAGE_RW 0x020 /* PR0-bit : write access allowed */
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# define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/
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# define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */
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#endif
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#define _PAGE_PRESENT 0x100 /* V-bit : page is valid */
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#define _PAGE_PROTNONE 0x200 /* software: if not present */
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#define _PAGE_ACCESSED 0x400 /* software: page referenced */
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#define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */
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/* Extended mode bits */
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#define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */
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#define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */
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#define _PAGE_EXT_ESZ2 0x0040 /* ESZ2-bit: Size of page */
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#define _PAGE_EXT_ESZ3 0x0080 /* ESZ3-bit: Size of page */
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#define _PAGE_EXT_USER_EXEC 0x0100 /* EPR0-bit: User space executable */
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#define _PAGE_EXT_USER_WRITE 0x0200 /* EPR1-bit: User space writable */
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#define _PAGE_EXT_USER_READ 0x0400 /* EPR2-bit: User space readable */
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#define _PAGE_EXT_KERN_EXEC 0x0800 /* EPR3-bit: Kernel space executable */
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#define _PAGE_EXT_KERN_WRITE 0x1000 /* EPR4-bit: Kernel space writable */
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#define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */
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/* Wrapper for extended mode pgprot twiddling */
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#ifdef CONFIG_X2TLB
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# define _PAGE_EXT(x) ((unsigned long long)(x) << 32)
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#else
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# define _PAGE_EXT(x) (0)
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#endif
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/* software: moves to PTEA.TC (Timing Control) */
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#define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */
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#define _PAGE_PCC_AREA6 0x80000000 /* use BSC registers for area6 */
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/* software: moves to PTEA.SA[2:0] (Space Attributes) */
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#define _PAGE_PCC_IODYN 0x00000001 /* IO space, dynamically sized bus */
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#define _PAGE_PCC_IO8 0x20000000 /* IO space, 8 bit bus */
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#define _PAGE_PCC_IO16 0x20000001 /* IO space, 16 bit bus */
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#define _PAGE_PCC_COM8 0x40000000 /* Common Memory space, 8 bit bus */
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#define _PAGE_PCC_COM16 0x40000001 /* Common Memory space, 16 bit bus */
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#define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */
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#define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */
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/* Mask which drops unused bits from the PTEL value */
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#ifdef CONFIG_CPU_SH3
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#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \
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_PAGE_FILE | _PAGE_SZ1 | \
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_PAGE_HW_SHARED)
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#else
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#define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE)
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#endif
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#define _PAGE_FLAGS_HARDWARE_MASK (0x1fffffff & ~(_PAGE_CLEAR_FLAGS))
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/* Hardware flags, page size encoding */
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#if defined(CONFIG_X2TLB)
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# if defined(CONFIG_PAGE_SIZE_4KB)
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# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ0)
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# elif defined(CONFIG_PAGE_SIZE_8KB)
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# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ1)
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# elif defined(CONFIG_PAGE_SIZE_64KB)
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# define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ2)
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# endif
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#else
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# if defined(CONFIG_PAGE_SIZE_4KB)
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# define _PAGE_FLAGS_HARD _PAGE_SZ0
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# elif defined(CONFIG_PAGE_SIZE_64KB)
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# define _PAGE_FLAGS_HARD _PAGE_SZ1
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# endif
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#endif
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#if defined(CONFIG_X2TLB)
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# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
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# define _PAGE_SZHUGE (_PAGE_EXT_ESZ2)
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# elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
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# define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ2)
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# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
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# define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ1 | _PAGE_EXT_ESZ2)
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# elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
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# define _PAGE_SZHUGE (_PAGE_EXT_ESZ3)
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# elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
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# define _PAGE_SZHUGE (_PAGE_EXT_ESZ2 | _PAGE_EXT_ESZ3)
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# endif
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#else
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# if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
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# define _PAGE_SZHUGE (_PAGE_SZ1)
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# elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
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# define _PAGE_SZHUGE (_PAGE_SZ0 | _PAGE_SZ1)
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# endif
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#endif
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/*
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* Stub out _PAGE_SZHUGE if we don't have a good definition for it,
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* to make pte_mkhuge() happy.
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*/
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#ifndef _PAGE_SZHUGE
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# define _PAGE_SZHUGE (_PAGE_FLAGS_HARD)
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#endif
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#define _PAGE_CHG_MASK \
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(PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
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#ifndef __ASSEMBLY__
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#if defined(CONFIG_X2TLB) /* SH-X2 TLB */
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#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
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_PAGE_ACCESSED | _PAGE_FLAGS_HARD)
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#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
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_PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
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_PAGE_EXT(_PAGE_EXT_USER_READ | \
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_PAGE_EXT_USER_WRITE))
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#define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
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_PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
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_PAGE_EXT(_PAGE_EXT_USER_EXEC | \
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_PAGE_EXT_USER_READ))
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#define PAGE_COPY PAGE_EXECREAD
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#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
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_PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
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_PAGE_EXT(_PAGE_EXT_USER_READ))
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#define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
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_PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
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_PAGE_EXT(_PAGE_EXT_USER_WRITE))
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#define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
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_PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
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_PAGE_EXT(_PAGE_EXT_USER_WRITE | \
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_PAGE_EXT_USER_READ | \
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_PAGE_EXT_USER_EXEC))
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#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
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_PAGE_DIRTY | _PAGE_ACCESSED | \
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_PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
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_PAGE_EXT(_PAGE_EXT_KERN_READ | \
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_PAGE_EXT_KERN_WRITE | \
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_PAGE_EXT_KERN_EXEC))
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#define PAGE_KERNEL_NOCACHE \
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__pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
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_PAGE_ACCESSED | _PAGE_HW_SHARED | \
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_PAGE_FLAGS_HARD | \
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_PAGE_EXT(_PAGE_EXT_KERN_READ | \
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_PAGE_EXT_KERN_WRITE | \
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_PAGE_EXT_KERN_EXEC))
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#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
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_PAGE_DIRTY | _PAGE_ACCESSED | \
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_PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
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_PAGE_EXT(_PAGE_EXT_KERN_READ | \
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_PAGE_EXT_KERN_EXEC))
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#define PAGE_KERNEL_PCC(slot, type) \
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__pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
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_PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
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_PAGE_EXT(_PAGE_EXT_KERN_READ | \
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_PAGE_EXT_KERN_WRITE | \
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_PAGE_EXT_KERN_EXEC) \
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(slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
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(type))
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#elif defined(CONFIG_MMU) /* SH-X TLB */
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#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
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_PAGE_ACCESSED | _PAGE_FLAGS_HARD)
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#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
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_PAGE_CACHABLE | _PAGE_ACCESSED | \
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_PAGE_FLAGS_HARD)
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#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
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_PAGE_ACCESSED | _PAGE_FLAGS_HARD)
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#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
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_PAGE_ACCESSED | _PAGE_FLAGS_HARD)
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#define PAGE_EXECREAD PAGE_READONLY
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#define PAGE_RWX PAGE_SHARED
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#define PAGE_WRITEONLY PAGE_SHARED
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#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | \
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_PAGE_DIRTY | _PAGE_ACCESSED | \
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_PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
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#define PAGE_KERNEL_NOCACHE \
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__pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
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_PAGE_ACCESSED | _PAGE_HW_SHARED | \
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_PAGE_FLAGS_HARD)
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#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
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_PAGE_DIRTY | _PAGE_ACCESSED | \
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_PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
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#define PAGE_KERNEL_PCC(slot, type) \
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__pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
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_PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
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(slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
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(type))
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#else /* no mmu */
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#define PAGE_NONE __pgprot(0)
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#define PAGE_SHARED __pgprot(0)
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#define PAGE_COPY __pgprot(0)
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#define PAGE_EXECREAD __pgprot(0)
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#define PAGE_RWX __pgprot(0)
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#define PAGE_READONLY __pgprot(0)
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#define PAGE_WRITEONLY __pgprot(0)
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#define PAGE_KERNEL __pgprot(0)
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#define PAGE_KERNEL_NOCACHE __pgprot(0)
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#define PAGE_KERNEL_RO __pgprot(0)
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#define PAGE_KERNEL_PCC __pgprot(0)
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#endif
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#endif /* __ASSEMBLY__ */
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/*
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* SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
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* protection for execute, and considers it the same as a read. Also, write
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* permission implies read permission. This is the closest we can get..
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*
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* SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
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* not only supporting separate execute, read, and write bits, but having
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* completely separate permission bits for user and kernel space.
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*/
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/*xwr*/
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#define __P000 PAGE_NONE
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#define __P001 PAGE_READONLY
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#define __P010 PAGE_COPY
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#define __P011 PAGE_COPY
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#define __P100 PAGE_EXECREAD
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#define __P101 PAGE_EXECREAD
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#define __P110 PAGE_COPY
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#define __P111 PAGE_COPY
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#define __S000 PAGE_NONE
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#define __S001 PAGE_READONLY
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#define __S010 PAGE_WRITEONLY
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#define __S011 PAGE_SHARED
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#define __S100 PAGE_EXECREAD
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#define __S101 PAGE_EXECREAD
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#define __S110 PAGE_RWX
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#define __S111 PAGE_RWX
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#ifndef __ASSEMBLY__
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/*
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* Certain architectures need to do special things when PTEs
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* within a page table are directly modified. Thus, the following
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* hook is made available.
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*/
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#ifdef CONFIG_X2TLB
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static inline void set_pte(pte_t *ptep, pte_t pte)
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{
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ptep->pte_high = pte.pte_high;
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smp_wmb();
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ptep->pte_low = pte.pte_low;
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}
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#else
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#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
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#endif
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#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
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/*
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* (pmds are folded into pgds so this doesn't get actually called,
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* but the define is needed for a generic inline function.)
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*/
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#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
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#define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
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#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
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#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
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#define pte_none(x) (!pte_val(x))
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#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
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#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
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#define pmd_none(x) (!pmd_val(x))
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#define pmd_present(x) (pmd_val(x))
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#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
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#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
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#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
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#define pte_page(x) phys_to_page(pte_val(x)&PTE_PHYS_MASK)
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/*
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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#define pte_not_present(pte) (!(pte_val(pte) & _PAGE_PRESENT))
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#define pte_dirty(pte) (pte_val(pte) & _PAGE_DIRTY)
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#define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
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#define pte_file(pte) (pte_val(pte) & _PAGE_FILE)
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#ifdef CONFIG_X2TLB
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#define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE)
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#else
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#define pte_write(pte) (pte_val(pte) & _PAGE_RW)
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#endif
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#define PTE_BIT_FUNC(h,fn,op) \
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static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; }
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#ifdef CONFIG_X2TLB
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/*
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* We cheat a bit in the SH-X2 TLB case. As the permission bits are
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* individually toggled (and user permissions are entirely decoupled from
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* kernel permissions), we attempt to couple them a bit more sanely here.
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*/
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PTE_BIT_FUNC(high, wrprotect, &= ~_PAGE_EXT_USER_WRITE);
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|
PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE);
|
|
PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE);
|
|
#else
|
|
PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW);
|
|
PTE_BIT_FUNC(low, mkwrite, |= _PAGE_RW);
|
|
PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE);
|
|
#endif
|
|
|
|
PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY);
|
|
PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY);
|
|
PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
|
|
PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
|
|
|
|
/*
|
|
* Macro and implementation to make a page protection as uncachable.
|
|
*/
|
|
#define pgprot_noncached pgprot_noncached
|
|
|
|
static inline pgprot_t pgprot_noncached(pgprot_t _prot)
|
|
{
|
|
unsigned long prot = pgprot_val(_prot);
|
|
|
|
prot &= ~_PAGE_CACHABLE;
|
|
return __pgprot(prot);
|
|
}
|
|
|
|
#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
|
|
|
|
/*
|
|
* Conversion functions: convert a page and protection to a page entry,
|
|
* and a page entry and page directory to the page they refer to.
|
|
*
|
|
* extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
|
|
*/
|
|
#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
|
|
|
|
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
|
{
|
|
set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) |
|
|
pgprot_val(newprot)));
|
|
return pte;
|
|
}
|
|
|
|
#define pmd_page_vaddr(pmd) pmd_val(pmd)
|
|
#define pmd_page(pmd) (virt_to_page(pmd_val(pmd)))
|
|
|
|
/* to find an entry in a page-table-directory. */
|
|
#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
|
|
#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
|
|
|
|
/* to find an entry in a kernel page-table-directory */
|
|
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
|
|
|
|
/* Find an entry in the third-level page table.. */
|
|
#define pte_index(address) \
|
|
((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
|
|
#define pte_offset_kernel(dir, address) \
|
|
((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
|
|
#define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
|
|
#define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address)
|
|
#define pte_unmap(pte) do { } while (0)
|
|
#define pte_unmap_nested(pte) do { } while (0)
|
|
|
|
#ifdef CONFIG_X2TLB
|
|
#define pte_ERROR(e) \
|
|
printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \
|
|
&(e), (e).pte_high, (e).pte_low)
|
|
#else
|
|
#define pte_ERROR(e) \
|
|
printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
|
|
#endif
|
|
|
|
#define pgd_ERROR(e) \
|
|
printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
|
|
|
|
struct vm_area_struct;
|
|
extern void update_mmu_cache(struct vm_area_struct * vma,
|
|
unsigned long address, pte_t pte);
|
|
|
|
/*
|
|
* Encode and de-code a swap entry
|
|
*
|
|
* Constraints:
|
|
* _PAGE_FILE at bit 0
|
|
* _PAGE_PRESENT at bit 8
|
|
* _PAGE_PROTNONE at bit 9
|
|
*
|
|
* For the normal case, we encode the swap type into bits 0:7 and the
|
|
* swap offset into bits 10:30. For the 64-bit PTE case, we keep the
|
|
* preserved bits in the low 32-bits and use the upper 32 as the swap
|
|
* offset (along with a 5-bit type), following the same approach as x86
|
|
* PAE. This keeps the logic quite simple, and allows for a full 32
|
|
* PTE_FILE_MAX_BITS, as opposed to the 29-bits we're constrained with
|
|
* in the pte_low case.
|
|
*
|
|
* As is evident by the Alpha code, if we ever get a 64-bit unsigned
|
|
* long (swp_entry_t) to match up with the 64-bit PTEs, this all becomes
|
|
* much cleaner..
|
|
*
|
|
* NOTE: We should set ZEROs at the position of _PAGE_PRESENT
|
|
* and _PAGE_PROTNONE bits
|
|
*/
|
|
#ifdef CONFIG_X2TLB
|
|
#define __swp_type(x) ((x).val & 0x1f)
|
|
#define __swp_offset(x) ((x).val >> 5)
|
|
#define __swp_entry(type, offset) ((swp_entry_t){ (type) | (offset) << 5})
|
|
#define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
|
|
#define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
|
|
|
|
/*
|
|
* Encode and decode a nonlinear file mapping entry
|
|
*/
|
|
#define pte_to_pgoff(pte) ((pte).pte_high)
|
|
#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
|
|
|
|
#define PTE_FILE_MAX_BITS 32
|
|
#else
|
|
#define __swp_type(x) ((x).val & 0xff)
|
|
#define __swp_offset(x) ((x).val >> 10)
|
|
#define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) <<10})
|
|
|
|
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 1 })
|
|
#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 1 })
|
|
|
|
/*
|
|
* Encode and decode a nonlinear file mapping entry
|
|
*/
|
|
#define PTE_FILE_MAX_BITS 29
|
|
#define pte_to_pgoff(pte) (pte_val(pte) >> 1)
|
|
#define pgoff_to_pte(off) ((pte_t) { ((off) << 1) | _PAGE_FILE })
|
|
#endif
|
|
|
|
typedef pte_t *pte_addr_t;
|
|
|
|
#define kern_addr_valid(addr) (1)
|
|
|
|
#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
|
|
remap_pfn_range(vma, vaddr, pfn, size, prot)
|
|
|
|
struct mm_struct;
|
|
|
|
/*
|
|
* No page table caches to initialise
|
|
*/
|
|
#define pgtable_cache_init() do { } while (0)
|
|
|
|
#ifndef CONFIG_MMU
|
|
extern unsigned int kobjsize(const void *objp);
|
|
#endif /* !CONFIG_MMU */
|
|
|
|
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
|
|
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
|
|
extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
|
|
#endif
|
|
|
|
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
|
|
extern void paging_init(void);
|
|
|
|
#include <asm-generic/pgtable.h>
|
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
#endif /* __ASM_SH_PAGE_H */
|