mirror of https://gitee.com/openkylin/linux.git
439 lines
10 KiB
C
439 lines
10 KiB
C
/*
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* PowerPC64 port by Mike Corrigan and Dave Engebretsen
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* {mikejc|engebret}@us.ibm.com
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*
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* Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
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*
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* SMP scalability work:
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* Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* Module name: htab.c
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*
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* Description:
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* PowerPC Hashed Page Table functions
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#include <linux/config.h>
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/proc_fs.h>
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#include <linux/stat.h>
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#include <linux/sysctl.h>
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#include <linux/ctype.h>
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#include <linux/cache.h>
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#include <linux/init.h>
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#include <linux/signal.h>
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#include <asm/ppcdebug.h>
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#include <asm/processor.h>
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/mmu_context.h>
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#include <asm/page.h>
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#include <asm/types.h>
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#include <asm/system.h>
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#include <asm/uaccess.h>
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#include <asm/machdep.h>
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#include <asm/lmb.h>
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#include <asm/abs_addr.h>
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#include <asm/tlbflush.h>
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#include <asm/io.h>
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#include <asm/eeh.h>
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#include <asm/tlb.h>
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#include <asm/cacheflush.h>
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#include <asm/cputable.h>
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#include <asm/abs_addr.h>
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#include <asm/sections.h>
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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/*
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* Note: pte --> Linux PTE
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* HPTE --> PowerPC Hashed Page Table Entry
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*
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* Execution context:
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* htab_initialize is called with the MMU off (of course), but
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* the kernel has been copied down to zero so it can directly
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* reference global data. At this point it is very difficult
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* to print debug info.
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*
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*/
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#ifdef CONFIG_U3_DART
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extern unsigned long dart_tablebase;
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#endif /* CONFIG_U3_DART */
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HPTE *htab_address;
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unsigned long htab_hash_mask;
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extern unsigned long _SDR1;
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#define KB (1024)
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#define MB (1024*KB)
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static inline void loop_forever(void)
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{
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volatile unsigned long x = 1;
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for(;x;x|=1)
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;
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}
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#ifdef CONFIG_PPC_MULTIPLATFORM
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static inline void create_pte_mapping(unsigned long start, unsigned long end,
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unsigned long mode, int large)
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{
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unsigned long addr;
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unsigned int step;
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unsigned long tmp_mode;
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if (large)
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step = 16*MB;
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else
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step = 4*KB;
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for (addr = start; addr < end; addr += step) {
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unsigned long vpn, hash, hpteg;
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unsigned long vsid = get_kernel_vsid(addr);
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unsigned long va = (vsid << 28) | (addr & 0xfffffff);
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int ret;
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if (large)
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vpn = va >> HPAGE_SHIFT;
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else
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vpn = va >> PAGE_SHIFT;
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tmp_mode = mode;
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/* Make non-kernel text non-executable */
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if (!in_kernel_text(addr))
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tmp_mode = mode | HW_NO_EXEC;
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hash = hpt_hash(vpn, large);
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hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
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#ifdef CONFIG_PPC_PSERIES
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if (systemcfg->platform & PLATFORM_LPAR)
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ret = pSeries_lpar_hpte_insert(hpteg, va,
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virt_to_abs(addr) >> PAGE_SHIFT,
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0, tmp_mode, 1, large);
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else
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#endif /* CONFIG_PPC_PSERIES */
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ret = native_hpte_insert(hpteg, va,
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virt_to_abs(addr) >> PAGE_SHIFT,
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0, tmp_mode, 1, large);
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if (ret == -1) {
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ppc64_terminate_msg(0x20, "create_pte_mapping");
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loop_forever();
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}
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}
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}
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void __init htab_initialize(void)
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{
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unsigned long table, htab_size_bytes;
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unsigned long pteg_count;
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unsigned long mode_rw;
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int i, use_largepages = 0;
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unsigned long base = 0, size = 0;
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extern unsigned long tce_alloc_start, tce_alloc_end;
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DBG(" -> htab_initialize()\n");
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/*
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* Calculate the required size of the htab. We want the number of
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* PTEGs to equal one half the number of real pages.
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*/
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htab_size_bytes = 1UL << ppc64_pft_size;
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pteg_count = htab_size_bytes >> 7;
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/* For debug, make the HTAB 1/8 as big as it normally would be. */
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ifppcdebug(PPCDBG_HTABSIZE) {
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pteg_count >>= 3;
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htab_size_bytes = pteg_count << 7;
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}
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htab_hash_mask = pteg_count - 1;
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if (systemcfg->platform & PLATFORM_LPAR) {
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/* Using a hypervisor which owns the htab */
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htab_address = NULL;
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_SDR1 = 0;
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} else {
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/* Find storage for the HPT. Must be contiguous in
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* the absolute address space.
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*/
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table = lmb_alloc(htab_size_bytes, htab_size_bytes);
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DBG("Hash table allocated at %lx, size: %lx\n", table,
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htab_size_bytes);
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if ( !table ) {
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ppc64_terminate_msg(0x20, "hpt space");
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loop_forever();
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}
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htab_address = abs_to_virt(table);
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/* htab absolute addr + encoded htabsize */
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_SDR1 = table + __ilog2(pteg_count) - 11;
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/* Initialize the HPT with no entries */
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memset((void *)table, 0, htab_size_bytes);
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}
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mode_rw = _PAGE_ACCESSED | _PAGE_COHERENT | PP_RWXX;
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/* On U3 based machines, we need to reserve the DART area and
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* _NOT_ map it to avoid cache paradoxes as it's remapped non
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* cacheable later on
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*/
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if (cpu_has_feature(CPU_FTR_16M_PAGE))
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use_largepages = 1;
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/* create bolted the linear mapping in the hash table */
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for (i=0; i < lmb.memory.cnt; i++) {
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base = lmb.memory.region[i].physbase + KERNELBASE;
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size = lmb.memory.region[i].size;
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DBG("creating mapping for region: %lx : %lx\n", base, size);
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#ifdef CONFIG_U3_DART
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/* Do not map the DART space. Fortunately, it will be aligned
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* in such a way that it will not cross two lmb regions and will
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* fit within a single 16Mb page.
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* The DART space is assumed to be a full 16Mb region even if we
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* only use 2Mb of that space. We will use more of it later for
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* AGP GART. We have to use a full 16Mb large page.
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*/
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DBG("DART base: %lx\n", dart_tablebase);
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if (dart_tablebase != 0 && dart_tablebase >= base
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&& dart_tablebase < (base + size)) {
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if (base != dart_tablebase)
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create_pte_mapping(base, dart_tablebase, mode_rw,
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use_largepages);
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if ((base + size) > (dart_tablebase + 16*MB))
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create_pte_mapping(dart_tablebase + 16*MB, base + size,
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mode_rw, use_largepages);
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continue;
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}
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#endif /* CONFIG_U3_DART */
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create_pte_mapping(base, base + size, mode_rw, use_largepages);
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}
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/*
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* If we have a memory_limit and we've allocated TCEs then we need to
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* explicitly map the TCE area at the top of RAM. We also cope with the
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* case that the TCEs start below memory_limit.
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* tce_alloc_start/end are 16MB aligned so the mapping should work
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* for either 4K or 16MB pages.
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*/
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if (tce_alloc_start) {
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tce_alloc_start += KERNELBASE;
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tce_alloc_end += KERNELBASE;
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if (base + size >= tce_alloc_start)
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tce_alloc_start = base + size + 1;
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create_pte_mapping(tce_alloc_start, tce_alloc_end,
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mode_rw, use_largepages);
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}
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DBG(" <- htab_initialize()\n");
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}
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#undef KB
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#undef MB
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#endif /* CONFIG_PPC_MULTIPLATFORM */
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/*
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* Called by asm hashtable.S for doing lazy icache flush
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*/
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unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
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{
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struct page *page;
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if (!pfn_valid(pte_pfn(pte)))
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return pp;
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page = pte_page(pte);
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/* page is dirty */
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if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
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if (trap == 0x400) {
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__flush_dcache_icache(page_address(page));
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set_bit(PG_arch_1, &page->flags);
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} else
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pp |= HW_NO_EXEC;
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}
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return pp;
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}
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/* Result code is:
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* 0 - handled
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* 1 - normal page fault
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* -1 - critical hash insertion error
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*/
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int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
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{
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void *pgdir;
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unsigned long vsid;
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struct mm_struct *mm;
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pte_t *ptep;
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int ret;
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int user_region = 0;
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int local = 0;
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cpumask_t tmp;
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if ((ea & ~REGION_MASK) > EADDR_MASK)
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return 1;
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switch (REGION_ID(ea)) {
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case USER_REGION_ID:
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user_region = 1;
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mm = current->mm;
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if (! mm)
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return 1;
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vsid = get_vsid(mm->context.id, ea);
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break;
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case IO_REGION_ID:
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mm = &ioremap_mm;
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vsid = get_kernel_vsid(ea);
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break;
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case VMALLOC_REGION_ID:
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mm = &init_mm;
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vsid = get_kernel_vsid(ea);
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break;
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#if 0
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case KERNEL_REGION_ID:
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/*
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* Should never get here - entire 0xC0... region is bolted.
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* Send the problem up to do_page_fault
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*/
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#endif
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default:
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/* Not a valid range
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* Send the problem up to do_page_fault
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*/
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return 1;
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break;
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}
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pgdir = mm->pgd;
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if (pgdir == NULL)
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return 1;
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tmp = cpumask_of_cpu(smp_processor_id());
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if (user_region && cpus_equal(mm->cpu_vm_mask, tmp))
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local = 1;
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/* Is this a huge page ? */
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if (unlikely(in_hugepage_area(mm->context, ea)))
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ret = hash_huge_page(mm, access, ea, vsid, local);
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else {
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ptep = find_linux_pte(pgdir, ea);
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if (ptep == NULL)
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return 1;
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ret = __hash_page(ea, access, vsid, ptep, trap, local);
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}
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return ret;
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}
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void flush_hash_page(unsigned long context, unsigned long ea, pte_t pte,
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int local)
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{
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unsigned long vsid, vpn, va, hash, secondary, slot;
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unsigned long huge = pte_huge(pte);
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if (ea < KERNELBASE)
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vsid = get_vsid(context, ea);
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else
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vsid = get_kernel_vsid(ea);
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va = (vsid << 28) | (ea & 0x0fffffff);
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if (huge)
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vpn = va >> HPAGE_SHIFT;
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else
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vpn = va >> PAGE_SHIFT;
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hash = hpt_hash(vpn, huge);
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secondary = (pte_val(pte) & _PAGE_SECONDARY) >> 15;
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if (secondary)
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hash = ~hash;
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slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
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slot += (pte_val(pte) & _PAGE_GROUP_IX) >> 12;
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ppc_md.hpte_invalidate(slot, va, huge, local);
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}
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void flush_hash_range(unsigned long context, unsigned long number, int local)
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{
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if (ppc_md.flush_hash_range) {
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ppc_md.flush_hash_range(context, number, local);
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} else {
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int i;
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struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
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for (i = 0; i < number; i++)
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flush_hash_page(context, batch->addr[i], batch->pte[i],
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local);
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}
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}
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static inline void make_bl(unsigned int *insn_addr, void *func)
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{
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unsigned long funcp = *((unsigned long *)func);
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int offset = funcp - (unsigned long)insn_addr;
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*insn_addr = (unsigned int)(0x48000001 | (offset & 0x03fffffc));
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flush_icache_range((unsigned long)insn_addr, 4+
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(unsigned long)insn_addr);
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}
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/*
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* low_hash_fault is called when we the low level hash code failed
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* to instert a PTE due to an hypervisor error
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*/
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void low_hash_fault(struct pt_regs *regs, unsigned long address)
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{
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if (user_mode(regs)) {
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siginfo_t info;
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info.si_signo = SIGBUS;
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info.si_errno = 0;
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info.si_code = BUS_ADRERR;
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info.si_addr = (void __user *)address;
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force_sig_info(SIGBUS, &info, current);
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return;
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}
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bad_page_fault(regs, address, SIGBUS);
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}
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void __init htab_finish_init(void)
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{
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extern unsigned int *htab_call_hpte_insert1;
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extern unsigned int *htab_call_hpte_insert2;
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extern unsigned int *htab_call_hpte_remove;
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extern unsigned int *htab_call_hpte_updatepp;
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make_bl(htab_call_hpte_insert1, ppc_md.hpte_insert);
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make_bl(htab_call_hpte_insert2, ppc_md.hpte_insert);
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make_bl(htab_call_hpte_remove, ppc_md.hpte_remove);
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make_bl(htab_call_hpte_updatepp, ppc_md.hpte_updatepp);
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}
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