mirror of https://gitee.com/openkylin/linux.git
205 lines
5.0 KiB
C
205 lines
5.0 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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* Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
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*/
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#include <linux/init.h>
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#include <linux/bitops.h>
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#include <linux/memblock.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_clk.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <linux/libfdt.h>
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#include <linux/smp.h>
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#include <asm/addrspace.h>
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#include <asm/bmips.h>
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#include <asm/bootinfo.h>
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#include <asm/cpu-type.h>
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#include <asm/mipsregs.h>
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#include <asm/prom.h>
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#include <asm/smp-ops.h>
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#include <asm/time.h>
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#include <asm/traps.h>
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#define RELO_NORMAL_VEC BIT(18)
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#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
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#define BCM6328_TP1_DISABLED BIT(9)
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static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
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struct bmips_quirk {
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const char *compatible;
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void (*quirk_fn)(void);
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};
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static void kbase_setup(void)
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{
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__raw_writel(kbase | RELO_NORMAL_VEC,
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BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
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ebase = kbase;
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}
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static void bcm3384_viper_quirks(void)
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{
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/*
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* Some experimental CM boxes are set up to let CM own the Viper TP0
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* and let Linux own TP1. This requires moving the kernel
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* load address to a non-conflicting region (e.g. via
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* CONFIG_PHYSICAL_START) and supplying an alternate DTB.
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* If we detect this condition, we need to move the MIPS exception
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* vectors up to an area that we own.
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*
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* This is distinct from the OTHER special case mentioned in
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* smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
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* logical CPU#1). For the Viper TP1 case, SMP is off limits.
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*
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* Also note that many BMIPS435x CPUs do not have a
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* BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
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* write VMLINUX_LOAD_ADDRESS into that register on every SoC.
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*/
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board_ebase_setup = &kbase_setup;
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bmips_smp_enabled = 0;
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}
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static void bcm63xx_fixup_cpu1(void)
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{
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/*
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* The bootloader has set up the CPU1 reset vector at
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* 0xa000_0200.
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* This conflicts with the special interrupt vector (IV).
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* The bootloader has also set up CPU1 to respond to the wrong
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* IPI interrupt.
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* Here we will start up CPU1 in the background and ask it to
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* reconfigure itself then go back to sleep.
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*/
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memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
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__sync();
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set_c0_cause(C_SW0);
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cpumask_set_cpu(1, &bmips_booted_mask);
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}
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static void bcm6328_quirks(void)
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{
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/* Check CPU1 status in OTP (it is usually disabled) */
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if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
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bmips_smp_enabled = 0;
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else
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bcm63xx_fixup_cpu1();
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}
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static void bcm6358_quirks(void)
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{
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/*
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* BCM3368/BCM6358 need special handling for their shared TLB, so
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* disable SMP for now
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*/
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bmips_smp_enabled = 0;
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}
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static void bcm6368_quirks(void)
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{
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bcm63xx_fixup_cpu1();
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}
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static const struct bmips_quirk bmips_quirk_list[] = {
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{ "brcm,bcm3368", &bcm6358_quirks },
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{ "brcm,bcm3384-viper", &bcm3384_viper_quirks },
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{ "brcm,bcm33843-viper", &bcm3384_viper_quirks },
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{ "brcm,bcm6328", &bcm6328_quirks },
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{ "brcm,bcm6358", &bcm6358_quirks },
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{ "brcm,bcm6362", &bcm6368_quirks },
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{ "brcm,bcm6368", &bcm6368_quirks },
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{ "brcm,bcm63168", &bcm6368_quirks },
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{ "brcm,bcm63268", &bcm6368_quirks },
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{ },
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};
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void __init prom_init(void)
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{
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bmips_cpu_setup();
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register_bmips_smp_ops();
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}
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void __init prom_free_prom_memory(void)
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{
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}
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const char *get_system_type(void)
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{
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return "Generic BMIPS kernel";
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}
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void __init plat_time_init(void)
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{
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struct device_node *np;
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u32 freq;
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np = of_find_node_by_name(NULL, "cpus");
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if (!np)
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panic("missing 'cpus' DT node");
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if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
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panic("missing 'mips-hpt-frequency' property");
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of_node_put(np);
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mips_hpt_frequency = freq;
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}
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void __init plat_mem_setup(void)
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{
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void *dtb;
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const struct bmips_quirk *q;
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set_io_port_base(0);
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ioport_resource.start = 0;
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ioport_resource.end = ~0;
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/* intended to somewhat resemble ARM; see Documentation/arm/booting.rst */
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if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
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dtb = phys_to_virt(fw_arg2);
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else if (fw_passed_dtb) /* UHI interface or appended dtb */
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dtb = (void *)fw_passed_dtb;
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else if (__dtb_start != __dtb_end)
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dtb = (void *)__dtb_start;
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else
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panic("no dtb found");
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__dt_setup_arch(dtb);
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for (q = bmips_quirk_list; q->quirk_fn; q++) {
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if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
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q->compatible)) {
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q->quirk_fn();
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}
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}
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}
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void __init device_tree_init(void)
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{
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struct device_node *np;
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unflatten_and_copy_device_tree();
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/* Disable SMP boot unless both CPUs are listed in DT and !disabled */
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np = of_find_node_by_name(NULL, "cpus");
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if (np && of_get_available_child_count(np) <= 1)
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bmips_smp_enabled = 0;
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of_node_put(np);
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}
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static int __init plat_dev_init(void)
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{
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of_clk_init(NULL);
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return 0;
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}
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device_initcall(plat_dev_init);
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