mirror of https://gitee.com/openkylin/linux.git
257 lines
5.2 KiB
C
257 lines
5.2 KiB
C
/*
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* A20R specific code
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <asm/sni.h>
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#include <asm/time.h>
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#define PORT(_base,_irq) \
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{ \
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.iobase = _base, \
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.irq = _irq, \
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.uartclk = 1843200, \
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.iotype = UPIO_PORT, \
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.flags = UPF_BOOT_AUTOCONF, \
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}
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static struct plat_serial8250_port a20r_data[] = {
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PORT(0x3f8, 4),
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PORT(0x2f8, 3),
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{ },
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};
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static struct platform_device a20r_serial8250_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = a20r_data,
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},
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};
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static struct resource a20r_ds1216_rsrc[] = {
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{
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.start = 0x1c081ffc,
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.end = 0x1c081fff,
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.flags = IORESOURCE_MEM
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}
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};
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static struct platform_device a20r_ds1216_device = {
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.name = "rtc-ds1216",
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.num_resources = ARRAY_SIZE(a20r_ds1216_rsrc),
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.resource = a20r_ds1216_rsrc
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};
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static struct resource snirm_82596_rsrc[] = {
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{
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.start = 0x18000000,
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.end = 0x18000004,
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.flags = IORESOURCE_MEM
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},
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{
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.start = 0x18010000,
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.end = 0x18010004,
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.flags = IORESOURCE_MEM
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},
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{
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.start = 0x1ff00000,
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.end = 0x1ff00020,
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.flags = IORESOURCE_MEM
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},
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{
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.start = 22,
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.end = 22,
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.flags = IORESOURCE_IRQ
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},
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{
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.flags = 0x01 /* 16bit mpu port access */
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}
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};
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static struct platform_device snirm_82596_pdev = {
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.name = "snirm_82596",
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.num_resources = ARRAY_SIZE(snirm_82596_rsrc),
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.resource = snirm_82596_rsrc
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};
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static struct resource snirm_53c710_rsrc[] = {
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{
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.start = 0x19000000,
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.end = 0x190fffff,
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.flags = IORESOURCE_MEM
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},
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{
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.start = 19,
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.end = 19,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct platform_device snirm_53c710_pdev = {
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.name = "snirm_53c710",
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.num_resources = ARRAY_SIZE(snirm_53c710_rsrc),
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.resource = snirm_53c710_rsrc
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};
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static struct resource sc26xx_rsrc[] = {
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{
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.start = 0x1c070000,
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.end = 0x1c0700ff,
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.flags = IORESOURCE_MEM
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},
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{
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.start = 20,
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.end = 20,
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.flags = IORESOURCE_IRQ
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}
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};
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#include <linux/platform_data/serial-sccnxp.h>
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static struct sccnxp_pdata sccnxp_data = {
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.reg_shift = 2,
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.mctrl_cfg[0] = MCTRL_SIG(DTR_OP, LINE_OP7) |
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MCTRL_SIG(RTS_OP, LINE_OP3) |
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MCTRL_SIG(DSR_IP, LINE_IP5) |
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MCTRL_SIG(DCD_IP, LINE_IP6),
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.mctrl_cfg[1] = MCTRL_SIG(DTR_OP, LINE_OP2) |
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MCTRL_SIG(RTS_OP, LINE_OP1) |
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MCTRL_SIG(DSR_IP, LINE_IP0) |
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MCTRL_SIG(CTS_IP, LINE_IP1) |
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MCTRL_SIG(DCD_IP, LINE_IP2) |
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MCTRL_SIG(RNG_IP, LINE_IP3),
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};
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static struct platform_device sc26xx_pdev = {
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.name = "sc2681",
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.resource = sc26xx_rsrc,
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.num_resources = ARRAY_SIZE(sc26xx_rsrc),
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.dev = {
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.platform_data = &sccnxp_data,
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},
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};
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/*
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* Trigger chipset to update CPU's CAUSE IP field
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*/
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static u32 a20r_update_cause_ip(void)
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{
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u32 status = read_c0_status();
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write_c0_status(status | 0x00010000);
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asm volatile(
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" .set push \n"
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" .set noat \n"
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" .set noreorder \n"
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" lw $1, 0(%0) \n"
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" sb $0, 0(%1) \n"
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" sync \n"
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" lb %1, 0(%1) \n"
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" b 1f \n"
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" ori %1, $1, 2 \n"
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" .align 8 \n"
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"1: \n"
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" nop \n"
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" sw %1, 0(%0) \n"
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" sync \n"
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" li %1, 0x20 \n"
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"2: \n"
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" nop \n"
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" bnez %1,2b \n"
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" addiu %1, -1 \n"
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" sw $1, 0(%0) \n"
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" sync \n"
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".set pop \n"
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:
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: "Jr" (PCIMT_UCONF), "Jr" (0xbc000000));
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write_c0_status(status);
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return status;
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}
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static inline void unmask_a20r_irq(struct irq_data *d)
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{
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set_c0_status(0x100 << (d->irq - SNI_A20R_IRQ_BASE));
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irq_enable_hazard();
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}
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static inline void mask_a20r_irq(struct irq_data *d)
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{
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clear_c0_status(0x100 << (d->irq - SNI_A20R_IRQ_BASE));
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irq_disable_hazard();
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}
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static struct irq_chip a20r_irq_type = {
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.name = "A20R",
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.irq_mask = mask_a20r_irq,
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.irq_unmask = unmask_a20r_irq,
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};
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/*
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* hwint 0 receive all interrupts
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*/
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static void a20r_hwint(void)
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{
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u32 cause, status;
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int irq;
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clear_c0_status(IE_IRQ0);
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status = a20r_update_cause_ip();
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cause = read_c0_cause();
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irq = ffs(((cause & status) >> 8) & 0xf8);
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if (likely(irq > 0))
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do_IRQ(SNI_A20R_IRQ_BASE + irq - 1);
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a20r_update_cause_ip();
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set_c0_status(IE_IRQ0);
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}
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void __init sni_a20r_irq_init(void)
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{
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int i;
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for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++)
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irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
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sni_hwint = a20r_hwint;
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change_c0_status(ST0_IM, IE_IRQ0);
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if (request_irq(SNI_A20R_IRQ_BASE + 3, sni_isa_irq_handler,
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IRQF_SHARED, "ISA", sni_isa_irq_handler))
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pr_err("Failed to register ISA interrupt\n");
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}
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void sni_a20r_init(void)
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{
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/* FIXME, remove if not needed */
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}
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static int __init snirm_a20r_setup_devinit(void)
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{
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switch (sni_brd_type) {
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case SNI_BRD_TOWER_OASIC:
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case SNI_BRD_MINITOWER:
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platform_device_register(&snirm_82596_pdev);
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platform_device_register(&snirm_53c710_pdev);
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platform_device_register(&sc26xx_pdev);
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platform_device_register(&a20r_serial8250_device);
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platform_device_register(&a20r_ds1216_device);
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sni_eisa_root_init();
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break;
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}
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return 0;
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}
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device_initcall(snirm_a20r_setup_devinit);
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