mirror of https://gitee.com/openkylin/linux.git
392 lines
10 KiB
C
392 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright: 2017-2018 Cadence Design Systems, Inc.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/phy/phy.h>
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#include <linux/phy/phy-mipi-dphy.h>
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#define REG_WAKEUP_TIME_NS 800
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#define DPHY_PLL_RATE_HZ 108000000
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/* DPHY registers */
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#define DPHY_PMA_CMN(reg) (reg)
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#define DPHY_PMA_LCLK(reg) (0x100 + (reg))
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#define DPHY_PMA_LDATA(lane, reg) (0x200 + ((lane) * 0x100) + (reg))
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#define DPHY_PMA_RCLK(reg) (0x600 + (reg))
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#define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg))
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#define DPHY_PCS(reg) (0xb00 + (reg))
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#define DPHY_CMN_SSM DPHY_PMA_CMN(0x20)
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#define DPHY_CMN_SSM_EN BIT(0)
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#define DPHY_CMN_TX_MODE_EN BIT(9)
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#define DPHY_CMN_PWM DPHY_PMA_CMN(0x40)
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#define DPHY_CMN_PWM_DIV(x) ((x) << 20)
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#define DPHY_CMN_PWM_LOW(x) ((x) << 10)
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#define DPHY_CMN_PWM_HIGH(x) (x)
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#define DPHY_CMN_FBDIV DPHY_PMA_CMN(0x4c)
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#define DPHY_CMN_FBDIV_VAL(low, high) (((high) << 11) | ((low) << 22))
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#define DPHY_CMN_FBDIV_FROM_REG (BIT(10) | BIT(21))
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#define DPHY_CMN_OPIPDIV DPHY_PMA_CMN(0x50)
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#define DPHY_CMN_IPDIV_FROM_REG BIT(0)
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#define DPHY_CMN_IPDIV(x) ((x) << 1)
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#define DPHY_CMN_OPDIV_FROM_REG BIT(6)
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#define DPHY_CMN_OPDIV(x) ((x) << 7)
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#define DPHY_PSM_CFG DPHY_PCS(0x4)
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#define DPHY_PSM_CFG_FROM_REG BIT(0)
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#define DPHY_PSM_CLK_DIV(x) ((x) << 1)
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#define DSI_HBP_FRAME_OVERHEAD 12
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#define DSI_HSA_FRAME_OVERHEAD 14
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#define DSI_HFP_FRAME_OVERHEAD 6
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#define DSI_HSS_VSS_VSE_FRAME_OVERHEAD 4
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#define DSI_BLANKING_FRAME_OVERHEAD 6
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#define DSI_NULL_FRAME_OVERHEAD 6
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#define DSI_EOT_PKT_SIZE 4
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struct cdns_dphy_cfg {
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u8 pll_ipdiv;
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u8 pll_opdiv;
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u16 pll_fbdiv;
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unsigned int nlanes;
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};
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enum cdns_dphy_clk_lane_cfg {
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DPHY_CLK_CFG_LEFT_DRIVES_ALL = 0,
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DPHY_CLK_CFG_LEFT_DRIVES_RIGHT = 1,
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DPHY_CLK_CFG_LEFT_DRIVES_LEFT = 2,
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DPHY_CLK_CFG_RIGHT_DRIVES_ALL = 3,
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};
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struct cdns_dphy;
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struct cdns_dphy_ops {
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int (*probe)(struct cdns_dphy *dphy);
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void (*remove)(struct cdns_dphy *dphy);
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void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
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void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
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enum cdns_dphy_clk_lane_cfg cfg);
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void (*set_pll_cfg)(struct cdns_dphy *dphy,
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const struct cdns_dphy_cfg *cfg);
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unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy);
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};
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struct cdns_dphy {
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struct cdns_dphy_cfg cfg;
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void __iomem *regs;
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struct clk *psm_clk;
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struct clk *pll_ref_clk;
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const struct cdns_dphy_ops *ops;
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struct phy *phy;
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};
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static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,
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struct cdns_dphy_cfg *cfg,
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struct phy_configure_opts_mipi_dphy *opts,
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unsigned int *dsi_hfp_ext)
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{
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unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk);
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u64 dlane_bps;
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memset(cfg, 0, sizeof(*cfg));
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if (pll_ref_hz < 9600000 || pll_ref_hz >= 150000000)
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return -EINVAL;
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else if (pll_ref_hz < 19200000)
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cfg->pll_ipdiv = 1;
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else if (pll_ref_hz < 38400000)
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cfg->pll_ipdiv = 2;
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else if (pll_ref_hz < 76800000)
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cfg->pll_ipdiv = 4;
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else
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cfg->pll_ipdiv = 8;
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dlane_bps = opts->hs_clk_rate;
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if (dlane_bps > 2500000000UL || dlane_bps < 160000000UL)
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return -EINVAL;
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else if (dlane_bps >= 1250000000)
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cfg->pll_opdiv = 1;
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else if (dlane_bps >= 630000000)
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cfg->pll_opdiv = 2;
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else if (dlane_bps >= 320000000)
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cfg->pll_opdiv = 4;
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else if (dlane_bps >= 160000000)
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cfg->pll_opdiv = 8;
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cfg->pll_fbdiv = DIV_ROUND_UP_ULL(dlane_bps * 2 * cfg->pll_opdiv *
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cfg->pll_ipdiv,
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pll_ref_hz);
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return 0;
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}
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static int cdns_dphy_setup_psm(struct cdns_dphy *dphy)
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{
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unsigned long psm_clk_hz = clk_get_rate(dphy->psm_clk);
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unsigned long psm_div;
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if (!psm_clk_hz || psm_clk_hz > 100000000)
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return -EINVAL;
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psm_div = DIV_ROUND_CLOSEST(psm_clk_hz, 1000000);
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if (dphy->ops->set_psm_div)
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dphy->ops->set_psm_div(dphy, psm_div);
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return 0;
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}
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static void cdns_dphy_set_clk_lane_cfg(struct cdns_dphy *dphy,
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enum cdns_dphy_clk_lane_cfg cfg)
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{
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if (dphy->ops->set_clk_lane_cfg)
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dphy->ops->set_clk_lane_cfg(dphy, cfg);
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}
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static void cdns_dphy_set_pll_cfg(struct cdns_dphy *dphy,
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const struct cdns_dphy_cfg *cfg)
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{
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if (dphy->ops->set_pll_cfg)
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dphy->ops->set_pll_cfg(dphy, cfg);
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}
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static unsigned long cdns_dphy_get_wakeup_time_ns(struct cdns_dphy *dphy)
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{
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return dphy->ops->get_wakeup_time_ns(dphy);
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}
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static unsigned long cdns_dphy_ref_get_wakeup_time_ns(struct cdns_dphy *dphy)
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{
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/* Default wakeup time is 800 ns (in a simulated environment). */
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return 800;
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}
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static void cdns_dphy_ref_set_pll_cfg(struct cdns_dphy *dphy,
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const struct cdns_dphy_cfg *cfg)
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{
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u32 fbdiv_low, fbdiv_high;
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fbdiv_low = (cfg->pll_fbdiv / 4) - 2;
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fbdiv_high = cfg->pll_fbdiv - fbdiv_low - 2;
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writel(DPHY_CMN_IPDIV_FROM_REG | DPHY_CMN_OPDIV_FROM_REG |
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DPHY_CMN_IPDIV(cfg->pll_ipdiv) |
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DPHY_CMN_OPDIV(cfg->pll_opdiv),
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dphy->regs + DPHY_CMN_OPIPDIV);
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writel(DPHY_CMN_FBDIV_FROM_REG |
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DPHY_CMN_FBDIV_VAL(fbdiv_low, fbdiv_high),
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dphy->regs + DPHY_CMN_FBDIV);
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writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) |
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DPHY_CMN_PWM_DIV(0x8),
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dphy->regs + DPHY_CMN_PWM);
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}
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static void cdns_dphy_ref_set_psm_div(struct cdns_dphy *dphy, u8 div)
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{
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writel(DPHY_PSM_CFG_FROM_REG | DPHY_PSM_CLK_DIV(div),
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dphy->regs + DPHY_PSM_CFG);
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}
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/*
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* This is the reference implementation of DPHY hooks. Specific integration of
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* this IP may have to re-implement some of them depending on how they decided
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* to wire things in the SoC.
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*/
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static const struct cdns_dphy_ops ref_dphy_ops = {
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.get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns,
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.set_pll_cfg = cdns_dphy_ref_set_pll_cfg,
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.set_psm_div = cdns_dphy_ref_set_psm_div,
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};
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static int cdns_dphy_config_from_opts(struct phy *phy,
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struct phy_configure_opts_mipi_dphy *opts,
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struct cdns_dphy_cfg *cfg)
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{
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struct cdns_dphy *dphy = phy_get_drvdata(phy);
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unsigned int dsi_hfp_ext = 0;
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int ret;
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ret = phy_mipi_dphy_config_validate(opts);
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if (ret)
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return ret;
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ret = cdns_dsi_get_dphy_pll_cfg(dphy, cfg,
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opts, &dsi_hfp_ext);
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if (ret)
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return ret;
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opts->wakeup = cdns_dphy_get_wakeup_time_ns(dphy) / 1000;
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return 0;
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}
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static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode,
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union phy_configure_opts *opts)
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{
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struct cdns_dphy_cfg cfg = { 0 };
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if (mode != PHY_MODE_MIPI_DPHY)
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return -EINVAL;
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return cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
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}
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static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
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{
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struct cdns_dphy *dphy = phy_get_drvdata(phy);
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struct cdns_dphy_cfg cfg = { 0 };
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int ret;
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ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
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if (ret)
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return ret;
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/*
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* Configure the internal PSM clk divider so that the DPHY has a
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* 1MHz clk (or something close).
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*/
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ret = cdns_dphy_setup_psm(dphy);
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if (ret)
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return ret;
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/*
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* Configure attach clk lanes to data lanes: the DPHY has 2 clk lanes
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* and 8 data lanes, each clk lane can be attache different set of
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* data lanes. The 2 groups are named 'left' and 'right', so here we
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* just say that we want the 'left' clk lane to drive the 'left' data
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* lanes.
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*/
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cdns_dphy_set_clk_lane_cfg(dphy, DPHY_CLK_CFG_LEFT_DRIVES_LEFT);
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/*
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* Configure the DPHY PLL that will be used to generate the TX byte
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* clk.
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*/
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cdns_dphy_set_pll_cfg(dphy, &cfg);
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return 0;
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}
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static int cdns_dphy_power_on(struct phy *phy)
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{
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struct cdns_dphy *dphy = phy_get_drvdata(phy);
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clk_prepare_enable(dphy->psm_clk);
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clk_prepare_enable(dphy->pll_ref_clk);
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/* Start TX state machine. */
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writel(DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
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dphy->regs + DPHY_CMN_SSM);
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return 0;
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}
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static int cdns_dphy_power_off(struct phy *phy)
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{
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struct cdns_dphy *dphy = phy_get_drvdata(phy);
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clk_disable_unprepare(dphy->pll_ref_clk);
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clk_disable_unprepare(dphy->psm_clk);
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return 0;
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}
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static const struct phy_ops cdns_dphy_ops = {
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.configure = cdns_dphy_configure,
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.validate = cdns_dphy_validate,
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.power_on = cdns_dphy_power_on,
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.power_off = cdns_dphy_power_off,
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};
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static int cdns_dphy_probe(struct platform_device *pdev)
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{
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struct phy_provider *phy_provider;
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struct cdns_dphy *dphy;
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struct resource *res;
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int ret;
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dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
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if (!dphy)
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return -ENOMEM;
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dev_set_drvdata(&pdev->dev, dphy);
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dphy->ops = of_device_get_match_data(&pdev->dev);
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if (!dphy->ops)
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return -EINVAL;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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dphy->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(dphy->regs))
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return PTR_ERR(dphy->regs);
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dphy->psm_clk = devm_clk_get(&pdev->dev, "psm");
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if (IS_ERR(dphy->psm_clk))
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return PTR_ERR(dphy->psm_clk);
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dphy->pll_ref_clk = devm_clk_get(&pdev->dev, "pll_ref");
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if (IS_ERR(dphy->pll_ref_clk))
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return PTR_ERR(dphy->pll_ref_clk);
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if (dphy->ops->probe) {
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ret = dphy->ops->probe(dphy);
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if (ret)
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return ret;
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}
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dphy->phy = devm_phy_create(&pdev->dev, NULL, &cdns_dphy_ops);
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if (IS_ERR(dphy->phy)) {
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dev_err(&pdev->dev, "failed to create PHY\n");
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if (dphy->ops->remove)
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dphy->ops->remove(dphy);
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return PTR_ERR(dphy->phy);
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}
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phy_set_drvdata(dphy->phy, dphy);
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phy_provider = devm_of_phy_provider_register(&pdev->dev,
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of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static int cdns_dphy_remove(struct platform_device *pdev)
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{
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struct cdns_dphy *dphy = dev_get_drvdata(&pdev->dev);
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if (dphy->ops->remove)
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dphy->ops->remove(dphy);
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return 0;
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}
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static const struct of_device_id cdns_dphy_of_match[] = {
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{ .compatible = "cdns,dphy", .data = &ref_dphy_ops },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, cdns_dphy_of_match);
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static struct platform_driver cdns_dphy_platform_driver = {
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.probe = cdns_dphy_probe,
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.remove = cdns_dphy_remove,
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.driver = {
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.name = "cdns-mipi-dphy",
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.of_match_table = cdns_dphy_of_match,
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},
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};
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module_platform_driver(cdns_dphy_platform_driver);
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MODULE_AUTHOR("Maxime Ripard <maxime.ripard@bootlin.com>");
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MODULE_DESCRIPTION("Cadence MIPI D-PHY Driver");
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MODULE_LICENSE("GPL");
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